IRF IRF6603

PD - 94364E
IRF6603
HEXFET®
l
Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l High Cdv/dt Immunity
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount
Techniques
Power MOSFET
VDSS
RDS(on) max
Qg(typ.)
30V
3.4mΩ@VGS = 10V
5.5mΩ@VGS = 4.5V
48nC
DirectFET™ ISOMETRIC
MT
Applicable DirectFET Outline and Substrate Outline (see p.9,10 for details)
SQ
SX
ST
MQ
MX
MT
Description
The IRF6603 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and process. The DirectFET package
allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6603 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation
of processors operating at higher frequencies. The IRF6603 has been optimized for parameters that are critical in synchronous buck
converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6603 offers particularly low Rds(on) and high Cdv/
dt immunity for synchronous FET applications.
Absolute Maximum Ratings
Parameter
VDS
VGS
Drain-to-Source Voltage
Max.
Units
30
V
ID @ TC = 25°C
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
+20/-12
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
27
ID @ TA = 70°C
22
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
200
PD @TA = 25°C
Power Dissipation
3.6
92
c
PD @TA = 70°C
g
Power Dissipation g
PD @TC = 25°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
A
2.3
W
42
0.029
-40 to + 150
W/°C
°C
Thermal Resistance
Parameter
Typ.
Max.
–––
35
12.5
–––
20
–––
RθJC
fj
Junction-to-Ambient gj
Junction-to-Ambient hj
Junction-to-Case ij
–––
3.0
RθJ-PCB
Junction-to-PCB Mounted
1.0
–––
RθJA
RθJA
RθJA
Junction-to-Ambient
Units
°C/W
Notes  through ˆ are on page 11
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1
4/8/04
IRF6603
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
30
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
V
Conditions
–––
–––
–––
28
–––
–––
2.4
3.4
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 25A
–––
3.9
5.5
VGS = 4.5V, ID = 20A
VGS(th)
Gate Threshold Voltage
1.4
–––
2.5
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-6.3
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
–––
–––
30
µA
VDS = 24V, VGS = 0V
–––
–––
50
µA
VDS = 30V, VGS = 0V
–––
–––
100
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
56
–––
–––
Total Gate Charge
–––
48
72
Qgs1
Pre-Vth Gate-to-Source Charge
–––
15.6
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
5.2
–––
Qgd
Gate-to-Drain Charge
–––
16.1
–––
ID = 20A
Qgodr
–––
11.1
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
21.3
–––
Qoss
Output Charge
–––
28
–––
nC
RG
Gate Resistance
–––
1.0
2.0
Ω
IGSS
gfs
Qg
e
e
VDS = 24V, VGS = 0V, TJ = 70°C
nA
VGS = 20V
VGS = -12V
S
VDS = 15V, ID = 20A
nC
VGS = 4.5V
VDS = 15V
VDS = 16V, VGS = 0V
td(on)
Turn-On Delay Time
–––
20
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
9.9
–––
ID = 20A
td(off)
Turn-Off Delay Time
–––
24
–––
tf
Fall Time
–––
71
–––
Ciss
Input Capacitance
–––
6590
–––
Coss
Output Capacitance
–––
1250
–––
Crss
Reverse Transfer Capacitance
–––
520
–––
e
ns
Clamped Inductive Load
pF
VDS = 15V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
49
Units
mJ
–––
20
A
–––
4.1
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
25
ISM
(Body Diode)
Pulsed Source Current
–––
–––
200
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
1.0
1.3
V
p-n junction diode.
TJ = 25°C, IS = 20A, VGS = 0V
trr
Reverse Recovery Time
–––
45
68
ns
Qrr
Reverse Recovery Charge
–––
60
90
nC
2
c
MOSFET symbol
A
D
G
S
e
TJ = 25°C, IF = 20A
di/dt = 100A/µs
e
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IRF6603
10000
1000
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
1000
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
1
0.1
2.7V
100
10
2.7V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
0.01
0.1
1
10
0.1
100
1
Fig 1. Typical Output Characteristics
2.0
10.00
T J = 25°C
VDS = 15V
20µs PULSE WIDTH
0.10
2.0
3.0
4.0
5.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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6.0
I D = 25A
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
T J = 150°C
1.00
100
Fig 2. Typical Output Characteristics
1000.00
100.00
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
160
( ° C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF6603
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
Coss
1000
Crss
6.0
ID= 20A
VGS, Gate-to-Source Voltage (V)
100000
VDS= 15V
5.0
4.0
3.0
2.0
1.0
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
10
20
30
40
50
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
I SD , Reverse Drain Current (A)
100
TJ = 150 ° C
10
T J = 25 ° C
1
V GS = 0 V
0.2
0.5
0.7
1.0
1.2
V SD,Source-to-Drain Voltage (V)
1msec
1
0.1
0.1
1.5
100µsec
10
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
Fig 8. Maximum Safe Operating Area
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IRF6603
100
2.5
VGS(th) Gate threshold Voltage (V)
90
ID, Drain Current (A)
80
70
60
50
40
30
20
2.0
ID = 250µA
1.5
1.0
10
0.5
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
(Z thJA )
100
D = 0.50
10
0.20
0.10
Thermal Response
0.05
1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
0.1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
0.1
t1/ t 2
J = P DM x Z thJA
1
+TA
10
100
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF6603
120
ID
8.9A
16A
20A
15V
TOP
100
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
BOTTOM
DRIVER
L
VDS
80
60
40
20
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
VGS
Current Sampling Resistors
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF6603
D.U.T
Driver Gate Drive
+
ƒ
+
‚
P.W.
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF6603
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )
 2

This can be expanded and approximated by;
Ploss = (Irms × Rds(on ) )
*dissipated primarily in Q1.
2

 
Qgs 2

Qgd
+I ×
× Vin × f  +  I ×
× Vin × f 
ig
ig

 

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF6603
DirectFET™ Outline Dimension, MT Outline
(Medium Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
NOTE: CONTROLLING
DIMENSIONS ARE IN MM
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METRIC
MAX
CODE MIN
6.35
A
6.25
5.05
B
4.80
3.95
C
3.85
0.45
D
0.35
0.82
E
0.78
0.92
F
0.88
1.82
G
1.78
H
0.98 1.02
0.67
J
0.63
K
O.88 1.01
2.63
L
2.46
0.70
M
0.59
0.08
N
0.03
0.17
P
0.08
IMPERIAL
MIN
MAX
0.246
0.250
0.189
0.199
0.152
0.156
0.014
0.018
0.031
0.032
0.035
0.036
0.070
0.072
0.039
0.040
0.025
0.026
0.035
0.039
0.097
0.104
0.023
0.028
0.001
0.003
0.003
0.007
9
IRF6603
DirectFET™ Substrate and PCB Layout, MT Outline
(MediumSize Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
6
3
1
1- Drain
2- Drain
3- Source
4- Source
5- Gate
6- Drain
7- Drain
5
7
4
2
DirectFET™ Tape & Reel Dimension
(Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6603). For 1000 parts on 7" reel,
order IRF6603TR1
REEL DIMENSIONS
TR1 OPTION (QTY 1000)
STANDARD OPTION (QTY 4800)
METRIC
METRIC
IMPERIAL
IMPERIAL
MIN
MIN
MAX
CODE
MIN
MAX
MIN
MAX
MAX
12.992
A
6.9
N.C
177.77 N.C
N.C
330.0
N.C
0.795
B
0.75
N.C
19.06
N.C
20.2
N.C
N.C
0.504
C
0.53
0.50
13.5
12.8
0.520
12.8
13.2
0.059
D
0.059
N.C
1.5
N.C
1.5
N.C
N.C
3.937
E
2.31
58.72
100.0
N.C
N.C
N.C
N.C
F
N.C
N.C
0.53
N.C
N.C
0.724
13.50
18.4
G
0.488
0.47
11.9
12.4
N.C
0.567
12.01
14.4
H
0.469
0.47
11.9
11.9
0.606
N.C
12.01
15.4
10
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IRF6603
DirectFET™ Part Marking
6603
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.24mH
RG = 25Ω, IAS = 20A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Surface mounted on 1 in. square Cu board.
… Used double sided cooling , mounting pad.
† Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
‡ TC measured with thermal couple mounted to top (Drain) of
part.
ˆ Rθ is measured at TJ of approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/04
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