IRF IRF6607TR1

PD - 94574B
IRF6607
HEXFET®
Power MOSFET
l
VDSS
RDS(on) max
Qg(typ.)
l
30V
3.3mΩ@VGS = 10V
4.4mΩ@VGS = 4.5V
50nC
Application Specific MOSFETs
Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l High Cdv/dt Immunity
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface
Mount Techniques
DirectFET™ ISOMETRIC
MT
Applicable DirectFET Outline and Substrate Outline (see p.9,10 for details)
SQ
SX
ST
MQ
MX
MT
Description
The IRF6607 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging
to achieve the lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The
DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and
vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the
manufacturing methods and process. The DirectFET package allows dual sided cooling to maximize thermal transfer in
power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6607 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power
the latest generation of processors operating at higher frequencies. The IRF6607 has been optimized for parameters that
are critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The
IRF6607 offers particularly low Rds(on) and high Cdv/dt immunity for synchronous FET applications.
Absolute Maximum Ratings
Parameter
VDS
VGS
ID @ TC = 25°C
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
PD @TA = 70°C
PD @TC = 25°C
TJ
TSTG
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
c
Pulsed Drain Current
Power Dissipation
Power Dissipation
Power Dissipation
Linear Derating Factor
Operating Junction and
Storage Temperature Range
g
g
Max.
Units
30
±12
94
27
22
220
3.6
2.3
42
0.029
-40 to + 150
V
A
W
W/°C
°C
Thermal Resistance
Parameter
RθJA
RθJA
RθJA
RθJC
RθJ-PCB
fj
gj
hj
ij
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB Mounted
Typ.
Max.
Units
–––
12.5
20
–––
–––
35
–––
–––
3.0
1.0
°C/W
Notes  through ˆ are on page 11
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1
4/8/04
IRF6607
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
29
–––
RDS(on)
Static Drain-to-Source On-Resistance
V
Conditions
VGS = 0V, ID = 250µA
–––
2.5
3.3
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 25A
–––
3.4
4.4
VGS = 4.5V, ID = 20A
VGS(th)
Gate Threshold Voltage
1.3
–––
2.0
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-5.3
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
e
e
VDS = VGS, ID = 250µA
–––
–––
30
µA
VDS = 24V, VGS = 0V
–––
–––
50
µA
VDS = 30V, VGS = 0V
nA
VGS = 12V
–––
–––
100
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
120
–––
–––
Total Gate Charge
–––
50
75
Qgs1
Pre-Vth Gate-to-Source Charge
–––
13
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
4.0
–––
Qgd
Gate-to-Drain Charge
–––
16
–––
ID = 20A
Qgodr
–––
18
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
20
–––
Qoss
Output Charge
–––
30
–––
nC
RG
Gate Resistance
–––
0.6
1.9
Ω
td(on)
Turn-On Delay Time
–––
60
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
8.0
–––
ID = 20A
td(off)
Turn-Off Delay Time
–––
32
–––
tf
Fall Time
–––
13
–––
Ciss
Input Capacitance
–––
6930
–––
Coss
Output Capacitance
–––
1260
–––
Crss
Reverse Transfer Capacitance
–––
510
–––
IGSS
Gate-to-Source Forward Leakage
gfs
Qg
VDS = 24V, VGS = 0V, TJ = 70°C
VGS = -12V
S
VDS = 15V, ID = 20A
nC
VGS = 4.5V
VDS = 15V
VDS = 16V, VGS = 0V
e
ns
Clamped Inductive Load
pF
VDS = 15V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
51
Units
mJ
–––
20
A
–––
0.36
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
27
ISM
(Body Diode)
Pulsed Source Current
–––
–––
220
VSD
(Body Diode)
Diode Forward Voltage
–––
1.0
1.3
trr
Reverse Recovery Time
–––
46
69
ns
Qrr
Reverse Recovery Charge
–––
54
81
nC
2
c
Conditions
MOSFET symbol
A
V
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 20A, VGS = 0V
S
e
TJ = 25°C, IF = 20A
di/dt = 100A/µs
e
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IRF6607
1000
1000
100
BOTTOM
10
1
2.0V
0.1
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
12V
10V
4.5V
3.0V
2.7V
2.5V
2.2V
2.0V
100
BOTTOM
10
2.0V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
0.01
0.1
1
10
100
0.1
1000
1
Fig 1. Typical Output Characteristics
2.0
10.00
T J = 25°C
1.00
VDS = 15V
20µs PULSE WIDTH
0.10
2.5
3.0
3.5
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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1000
4.0
I D = 25A
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
T J = 150°C
2.0
100
Fig 2. Typical Output Characteristics
1000.00
100.00
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (Α)
VGS
12V
10V
4.5V
3.0V
2.7V
2.5V
2.2V
2.0V
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
160
TJ, Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF6607
100000
6.0
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
ID= 20A
10000
Ciss
Coss
1000
Crss
VDS= 24V
VDS= 15V
5.0
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Coss = Cds + Cgd
4.0
3.0
2.0
1.0
0.0
100
1
10
100
0
VDS, Drain-to-Source Voltage (V)
10
20
30
40
50
60
Q G Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000.00
100.00
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 150°C
10.00
1.00
T J = 25°C
100µsec
10
1msec
10msec
1
T A = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.1
0.10
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF6607
2.0
VGS(th) Gate threshold Voltage (V)
30
25
I D , Drain Current (A)
20
15
10
5
1.5
ID = 250µA
1.0
0.5
0
25
50
75
100
125
150
TA, Ambient Temperature (°C)
-75
-50
-25
0
25
50
75
100 125 150
T J , Temperature ( °C )
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 10. Threshold Voltage Vs. Temperature
(Z thJA)
100
D = 0.50
10
0.20
0.10
Thermal Response
0.05
1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
0.1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
0.1
t1/ t 2
J = P DM x Z thJA
1
+TA
10
100
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF6607
120
15V
ID
TOP
8.9A
16A
20A
100
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
BOTTOM
DRIVER
L
VDS
80
60
40
20
0
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
VGS
Current Sampling Resistors
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF6607
D.U.T
Driver Gate Drive
+
ƒ
+
‚
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
Period
P.W.
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF6607
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )
 2

This can be expanded and approximated by;
Ploss = (Irms × Rds(on ) )
*dissipated primarily in Q1.
2

 
Qgs 2

Qgd
+I ×
× Vin × f  +  I ×
× Vin × f 
ig
ig

 

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF6607
DirectFET™ Outline Dimension, MT Outline
(Medium Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
NOTE: CONTROLLING
DIMENSIONS ARE IN MM
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METRIC
MAX
CODE MIN
6.35
A
6.25
5.05
B
4.80
3.95
C
3.85
0.45
D
0.35
0.82
E
0.78
0.92
F
0.88
1.82
G
1.78
H
0.98 1.02
0.67
J
0.63
K
O.88 1.01
2.63
L
2.46
0.70
M
0.59
0.08
N
0.03
0.17
P
0.08
IMPERIAL
MIN
MAX
0.246
0.250
0.189
0.199
0.152
0.156
0.014
0.018
0.031
0.032
0.035
0.036
0.070
0.072
0.039
0.040
0.025
0.026
0.035
0.039
0.097
0.104
0.023
0.028
0.001
0.003
0.003
0.007
9
IRF6607
DirectFET™ Substrate and PCB Layout, MT Outline
(MediumSize Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
6
3
1
1- Drain
2- Drain
3- Source
4- Source
5- Gate
6- Drain
7- Drain
5
7
4
2
DirectFET™ Tape & Reel Dimension
(Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6607). For 1000 parts on 7" reel,
order IRF6607TR1
REEL DIMENSIONS
TR1 OPTION (QTY 1000)
STANDARD OPTION (QTY 4800)
METRIC
METRIC
IMPERIAL
IMPERIAL
MIN
MIN
MAX
MAX
CODE
MIN
MIN
MAX
MAX
12.992 N.C
6.9
N.C
A
177.77 N.C
330.0
N.C
0.795
0.75
B
N.C
19.06
20.2
N.C
N.C
N.C
0.504
C
0.53
0.50
13.5
12.8
0.520
12.8
13.2
0.059
D
0.059
1.5
1.5
N.C
N.C
N.C
N.C
3.937
E
2.31
58.72
100.0
N.C
N.C
N.C
N.C
F
N.C
N.C
0.53
N.C
N.C
0.724
13.50
18.4
G
0.488
0.47
11.9
12.4
N.C
0.567
12.01
14.4
H
0.469
0.47
11.9
11.9
N.C
0.606
12.01
15.4
10
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IRF6607
DirectFET™ Part Marking
6607
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.25mH
RG = 25Ω, IAS = 20A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Surface mounted on 1 in. square Cu board.
… Used double sided cooling , mounting pad.
† Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
‡ TC measured with thermal couple mounted to top (Drain) of
part.
ˆ Rθ is measured at TJ of approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/04
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11