INFINEON TUA6020

Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
TUA6020 Version 1.2
Specification April 2000
preliminary
Revision History: Current Version: 04.00
Previous Version:Target Data Sheet
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
5-8, 5-9
5-8, 5-9
oscillator phase noise data
all
all
status: target to preliminary
5-27
Input impedance of VHF mixer
5-29
Output impedance of IF output
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Edition 03.04.00
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TUA6020
preliminary
Product Info
Product Info
General Description
Features
The TUA6020 is a 5 V mixer/oscillator Package
and synthesizer for analog and digital
TV and VCR tuners.
General
Suitable for analog and digital terrestrial TV tuner
Full ESD protection
Mixer/Oscillator
High impedance mixer input for
LOW/MID band
Low impedance mixer input for
HIGH band
4 pin oscillator for LOW/MID band
4 pin oscillator for HIGH band
IF-Amplifier
balanced SAW preamplifier
Low output impedance
PLL
PLL with short lock-in time
High voltage VCO tuning output
Application
Fast I2C bus
3 NPN bandswitch buffers
Internal LOW-MID/HIGH switch
Lock-in flag
Power-down reset
Programmable reference divider
ratios: 24, 64, 80, 128
Programmable charge pump current
The IC is suitable for PAL tuner in TV- and VCR-sets or set-top receivers for
analog TV and Digital Video Broadcasting.
Ordering Information
Wireless Components
Type
Ordering Code
Package
TUA6020
Q67037-A1127-A701
(tape and reel)
P-TSSOP-28-1
Product Info
Specification, April 2000
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
2.2
2.3
2.4
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
3.1
3.2
3.3
3.4
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4
4.1
4.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3
5
5.1
5.1.1
5.1.2
5.1.3
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 IC frequency range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3
I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13
Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14
Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14
Noise Figure Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . 5-15
TUA6020
preliminarytarget
Table of Contents
5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16
5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Wireless Components
Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-17
Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17
Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18
Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
1-2
Specification, April 2000
2
Product Description
Contents of this Chapter
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA6020
targetpreliminary
Product Description
2.1 General Description
The TUA6020 device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports. A flag is set when the
loop is locked. It can be read by the processor via the I2C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
Suitable for analog and digital terrestrial TV tuner
Full ESD protection
Mixer/Oscillator
High impedance mixer input for LOW/MID band
Low impedance mixer input for HIGH band
4 pin oscillator for LOW/MID band
4 pin oscillator for HIGH band
IF-Amplifier
balanced SAW preamplifier
Low output impedance
PLL
Wireless Components
PLL with short lock-in time
High voltage VCO tuning output
Fast I2C bus
3 NPN bandswitch buffers
Internal LOW-MID/HIGH switch
Lock-in flag
Power-down reset
2-2
Specification, April 2000
TUA6020
targetpreliminary
Product Description
Programmable reference divider ratios: 24, 64, 80, 128
Programmable charge pump current
2.3 Application
The IC is suitable for PAL tuners in TV- and VCR-sets or set-top receivers
for analog TV and Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-3
Specification, April 2000
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4
3.4.1
3.4.2
3.4.3
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TUA6020
preliminarytarget
Functional Description
3.1 Pin Configuration
HIGHIN
1
28
OSCHIGHIN
HIGHIN
2
27
OSCHIGHOUT
LOW/MIDIN
3
26
OSCHIGHOUT
VCC
4
25
OSCHIGHIN
MIXOUT
5
24
OSCLOW/MIDIN
MIXOUT
6
23
OSCLOW/MIDOUT
PLLGND
7
22
OSCLOW/MIDOUT
SDA
8
21
OSCLOW/MIDIN
SCL
TUA6020
9
20
RFGND
AS
10
19
VCC *)
XTAL
11
18
IFOUT
PHIGH
12
17
IFOUT
PLOW
13
16
VT
PMID
14
15
CP
*) for future purposes
Pin_config
Figure 3-1
Wireless Components
Pin Configuration
3-2
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function
Pin No.
Symbol
1
HIGHIN
2
HIGHIN
3
LOW/MIDIN
Equivalent I/O-Schematic
1
Average DC voltage
2
LOW/MID
HIGH
0.0 V
0.9 V
0.0 V
0.9 V
1.8 V
0.0 V
5.0 V
5.0 V
3.8 V
3.8 V
3.8 V
3.8 V
0.0 V
0.0 V
3
4
VCC
5
MIXOUT
supply voltage
IF Amp.
6
MIXOUT
5
6
Oscillator
7
PLLGND
Wireless Components
digital ground
3-3
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
8
Symbol
Equivalent I/O-Schematic
SDA
Average DC voltage
LOW/MID
HIGH
n.a.
n.a.
n.a.
n.a.
VAS
VAS
3.0 V
3.0 V
8
9
SCL
9
10
AS
10
11
XTAL
11
Wireless Components
3-4
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
12
Symbol
Equivalent I/O-Schematic
Average DC voltage
PHIGH
13
PLOW
14
PMID
15
CP
12
13
14
LOW/MID
HIGH
5V
VCE
5 V or V CE
5V
5 V or V CE
5V
1.9 V
1.9 V
VT
VT
2.3 V
2.3 V
2.3 V
2.3 V
15
16
VT
16
17
IFOUT
17
18
18
IFOUT
19
VCC
supply voltage
5.0 V
5.0 V
20
RFGND
analog ground
0.0 V
0.0 V
Wireless Components
3-5
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
1.6 V
0.0 V
2.3 V
0.0 V
21
OSCLOW/
MIDIN
22
OSCLOW/
MIDOUT
23
OSCLOW/
MIDOUT
2.3 V
0.0 V
24
OSCLOW/
MIDIN
1.6 V
0.0 V
25
OSCHIGHIN
0.0 V
1.6 V
26
OSCHIGHOUT
0.0 V
2.8 V
27
OSCHIGHOUT
0.0 V
2.8 V
28
OSCHIGHIN
0.0 V
1.6 V
Wireless Components
22
23
21
24
26
27
25
28
3-6
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
OSCHIGHIN
OSCHIGHOUT
OSCHIGHOUT
OSCHIGHIN
OSCLOW/MIDIN
OSCLOW/MIDOUT
OSCLOW/MIDOUT
OSCLOW/MIDIN
RFGND
VCC
IFOUT
IFOUT
VT
CP
3.3 Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Charge
Pump
Oscillator
HIGH
HIGH
Oscillator
LOW/MID
SAW
Driver
Phase/
Frequency
Comparator
LOW
or MID
CP, OS
fdiv
Prog.
Divider
fref
Reference
Divider
Mixer
HIGH
HIGH
Mixer
LOW/MID
Lock
Detector
LOW
or MID
RF Input
HIGH
HIGH
RF Input
LOW/MID
Crystal
Oscillator
FL
LOW
or MID
I2C Bus
PORTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HIGHIN
HIGHIN
LOW/MIDIN
VCC
MIXOUT
MIXOUT
PLLGND
SDA
SCL
AS
XTAL
PHIGH
PLOW
PMID
VCC
Block_diag
Figure 3-2
Wireless Components
Block Diagram
3-7
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
3.4 Circuit Description
3.4.1
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW/MID and HIGH, an IF amplifier, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.2
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or
166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the I- current
source pulses. If the two signals are in phase, the charge pump output (CP)
goes into the high-impedance state (PLL is locked). An active low-pass filter
integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pull-up resistor at TUNE and external RC circuitry). The
charge pump output is also switched into the high-impedance state if the control
bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning voltage
can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. TUNE may be switched off by the control bit
OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V (VTH).
By means of control bit CP the pump current can be switched between two values by software. This programmability permits alteration of the control response
time of the PLL in the locked-in state. In this way different VCO gains can be
compensated, for example.
Wireless Components
3-8
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bits T0 = 0 and T1 = 1, switch the test signals
fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PMID and PLOW respectively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed frequency is given by
αf == I P Γ (KVCO / fXTAL) Γ=(C1+C2) / (C1ΓC2)
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter ( see Figure 4-1 Evaluation board, PAL application on page 2). As the charge pump pulses at i.e. 62.5
kHz (= fref), it takes a maximum of 16=←s for FL to be reset after the loop has lost
lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144=←s for FL to be set after the loop regains lock.
3.4.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 10)
should be referred to the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL
from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
Wireless Components
3-9
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 11).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset
at the end of a READ operation.
Wireless Components
3 - 10
Specification, April 2000
4
Applications
Contents of this Chapter
4.1
4.2
Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3
TUA6020
preliminarytarget
Applications
4.1 Evaluation board, PAL application
560
10n
2k7
1k8
1k8
IFOUT
RLoad = 75 Ω
4n7
1k
100k
BA892
BB565
+ 33 V
100n
2k7
BB659
33k
220
82p
15p
1p
L1
L2
L3
100n
1k
3k3
VCC
120p
C2
2n2
2:10**)
22k
12p
C1
47n
4n7
1p2
1p2
28
27
1p2
26
1p2
25
2p7
24
2p2
23
2p2
22
2p7
21
20
19
18
17
16
15
10
11
12
13
14
TUA6020
1
2
3
4
5
6
7
8
9
2p2
22p
22p
18p
1n
L4
68p
1:1*)
68p
47n
4n7
220
220
4 MHz
100p
100p
4n7
4n7
4n7
4n7
LOW/
MID
HIGH
RGen = 75 Ω
VCC
RGen = 75 Ω
SDA
SCL
AS
PHIGH PLOW
PMID
Application Circuit
Figure 4-1
Evaluation board, PAL application
Table 4-1 Recommended band limits in MHz
RF input
Table 4-1 Coils
Oscillator
turns
⍪
wire ⍪
min
max
min
max
L1
1.5
2.4 mm
0.5 mm
LOW
48.25
140.25
87.15
179.15
L2
2.5
3 mm
0.5 mm
MID
147.25
423.25
186.15
462.15
L3
8.5
3.2 mm
0.5 mm
HIGH
431.25
855.25
470.15
894.15
L4
14.5
4 mm
0.3 mm
Wireless Components
4-2
*)
TOKO B4F Type 617DB-1023
**)
TOKO 7KL600 GCS-A1010DX
Specification, April 2000
TUA6020
preliminarytarget
Applications
4.2 Evaluation board, low phase noise application
560
47n
22n
2k7
1k8
1k8
IFOUT
RLoad = 75 Ω
4n7
1k
100k
BA892
BB565
+ 33 V
100n
2k7
BB659
33k
15p
1p
L1
L2
L3
560
220
82p
100n
1k
3k3
VCC
120p
C2
2n2
2:10**)
12k
12p
C1
100n
4n7
1p2
28
1p2
27
1p2
26
1p2
25
2p7
24
2p2
23
2p2
22
2p7
21
20
19
18
17
16
15
10
11
12
13
14
TUA6020
1
2
3
4
5
6
7
8
9
2p2
22p
22p
18p
1n
L4
68p
1:1*)
68p
220
47n
4n7
220
4 MHz
100p
100p
4n7
4n7
4n7
4n7
LOW/
MID
HIGH
RGen = 75 Ω
VCC
RGen = 75 Ω
SDA
SCL
AS
PHIGH PLOW
PMID
Application Circuit digital
Figure 4-2
Evaluation board, low phase noise application
Table 4-1 Recommended band limits in MHz
RF input
min
max
Table 4-1 Coils
Oscillator
turns
⍪
wire ⍪
2.4 mm
0.5 mm
min
max
L1
1.5
LOW
48.25
140.25
87.15
179.15
L2
2.5
3 mm
0.5 mm
MID
147.25
423.25
186.15
462.15
L3
8.5
3.2 mm
0.5 mm
HIGH
431.25
855.25
470.15
894.15
L4
14.5
4 mm
0.3 mm
Wireless Components
4-3
*)
TOKO B4F Type 617DB-1023
**)
TOKO 7KL600 GCS-A1010DX
Specification, April 2000
5
Reference
Contents of this Chapter
5.1
5.1.1
5.1.2
5.1.3
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 IC frequency range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3
I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13
Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14
Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14
Noise Figure Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . 5-15
Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15
Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16
Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-17
Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17
Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18
Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
TUA6020
preliminarytarget
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20°C ... + 85°C
Parameter 1).
Symbol
Supply voltage
VCC
Junction temperature
TJ
Storage temperature
TStg
Thermal resistance
(junction to ambient)
RthJA
Limit Values
Unit
min
max
-0.3
6
V
+150
C
+125
C
120
K/W
-40
Remarks
PLL
CP
VCP
-0.3
ICP
Crystal oscillator pin XTAL
VXTAL
3
V
1
mA
VCC
V
IXTAL
-5
Bus input/output SDA
VSDA
-0.3
Bus output current SDA
ISDA(L)
Bus input SCL
VSCL
-0.3
VCC
V
Chip address switch AS
VAS
-0.3
VCC
V
Tuning voltage output (loop filter)
VT
-0.3
35
V
Port outputs PLOW, PMID, PHIGH
VP
-0.3
VCC
V
IP(L)
-1
25
mA
tmax = 0.1 sec.
at 5.5 V
40
mA
tmax = 0.1 sec.
at 5.5 V
3
V
2
V
6
mA
Total port output current
mA
VCC
5
πIP(L)
V
mA
open collector
Mixer-Oscillator
Mixer inputs LOW/MID
Vi
Mixer inputs HIGH
Vi
-0.3
Ii
Wireless Components
-5
5-2
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20°C ... + 85°C (continued)
Parameter 1)
Symbol
Oscillator base voltage
VB
Oscillator collector voltage
VC
Limit Values
Unit
min
max
-0.3
3
V
VCC
V
2
kV
Remarks
ESD-Protection 2).
all pins
VESD
1). All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flow into the pin and currents with a negative sign flow out of pin.
2). According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standardS5.1 - 1993
Wireless Components
5-3
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
min
max
Unit
Supply voltage
VCC
+4.5
+5.5
Programmable divider factor
N
256
32767
LOW/MID Mixer input frequency
range
fi
30
500
MHz
HIGH Mixer input frequency
range
fi
400
900
MHz
LOW/MID Oscillator frequency
range
fO
65
560
MHz
HIGH Oscillator frequency range
fO
430
950
MHz
Ambient temperature
TAMB
-20
+85
C
Wireless Components
5-4
Test Conditions
L
Item
V
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC
Symbol
Limit Values
Unit
min
typ
max
Test Conditions
L
Item
Supply
Supply voltage
VCC
4.5
5
5.5
V
Current consumption
ICC
56
70
84
mA
4.0
4.8
MHz
series resonance
100
τ
series resonance
Digital Unit
PLL
Crystal oscillator connections XTAL
Crystal frequency
fXTAL
3.2
Crystal resistance
RXTAL
10
Oscillation frequency
fXTAL
3,99975
4,000
4,00025
MHz
fXTAL = 4 MHz
Input impedance
ZXTAL
-500
-700
-900
τ
fXTAL = 4 MHz
Charge pump output CP
HIGH output current
ICPH
90
220
300
µA
CP = 1, V CP = 2 V
LOW output current
ICPL
22
50
75
µA
CP = 0, V CP = 2 V
Tristate current
ICPZ
nA
T0 = 1, T1 = 0,
VCP = 2 V
Output voltage
VCP
2.5
V
PLL locked
+1
1.0
Drive output VT (open collector)
HIGH output current
ITH
10
µA
VTH = 33 V, T0 = 1,
T1 = 0
LOW output voltage
VTL
0.4
V
ITL = 1.0 mA
I2C-Bus
Bus inputs SCL, SDA
HIGH input voltage
VIH
3
5.5
V
LOW input voltage
VIL
0
1.5
V
HIGH input current
IIH
10
µA
VIH = V CC
LOW input current
IIL
µA
VIL = 0 V
µA
VOH = 5.5 V
-10
Bus output SDA (open collector)
HIGH output current
Wireless Components
IOH
10
5-5
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
LOW output voltage
typ
Unit
Test Conditions
L
Item
max
VOL
0.4
V
Rise time
tr
300
ns
Fall time
tf
300
ns
400
kHz
IOL = 3 mA
Edge speed SCL,SDA
Clock timing SCL
Frequency
fSCL
HIGH pulse width
tH
0.6
µs
LOW pulse width
tL
1.3
µs
Set-up time
tsusta
0.6
µs
Hold time
thsta
0.6
µs
Set up time
tsusto
0.6
µs
Bus free
tbuf
1.3
µs
Set-up time
tsudat
0.1
µs
Hold time
thdat
0
µs
Input hysteresis
SCL, SDA
Vhys
Pulse width of spikes
which are suppressed
tsp
Capacitive load for
each bus line
CL
0
Start condition
Stop condition
Data transfer
200
mV
0
50
ns
400
pF
Port outputs PLOW, PMID, PHIGH (open collector)
HIGH output current
IPOH
1
µA
VPOH = 5 V
LOW output voltage
VPOL
0.5
V
IPOL = 25 mA
50
µA
VASH = 5 V
µA
VASL = 0 V
Address selection input AS
HIGH input current
IASH
LOW input current
IASL
Wireless Components
-50
5-6
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
23
26
dB
fRF = 43.25 to 463.25
MHz, fIF = 33.4 to
58.75 MHz
11
dB
fRF = 43.25 to 463.25
MHz
L
Item
Analog Unit
LOW/MID Band Section (including IF amplifier)
Voltage gain
GV
Mixer noise figure
NF
9
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.6 on
page 15
Vi
118
dBµV
fRFw = 48.25 MHz
Vi
117
dBµV
fRFw = 399.25 MHz
Input IP2
IIP2
137
dBµV
fRF1 = 48.25 MHz
fRF2 = 98.50 MHz,
PRF1 = P RF2
IIP2
137
dBµV
fRF1 = 415.25 MHz
fRF2 = 832.50 MHz,
PRF1 = P RF2
IIP3
119
dBµV
fRF1 = 48.25 MHz
fRF2 = 49.25 MHz
PRF1 = P RF2
IIP3
119
dBµV
fRF1 = 252.25 MHz
fRF2 = 253.25 MHz,
PRF1 = P RF2
Output voltage causing 1 dB compression
Vo
121
dBµV
fRF = 48.25 MHz
Vo
121
dBµV
fRF = 252.25 MHz
Mixer input
impedance
Ri
Input IP3
20
0.5
Ci
1
1.5
kτ
parallel equivalent
circuit, fRF = 100 MHz
2
3
pF
parallel equivalent
circuit, fRF = 100 MHz
Oscillator frequency
shift, PLL unlocked
αfOsc(V)
400
kHz
VS = 5 V10%
Oscillator frequency
drift, PLL unlocked
αfOsc(T)
500
kHz
αT = 25=C
Oscillator frequency
drift, PLL unlocked
αfOsc(t)
100
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
Vi
Vi
Wireless Components
100
108
dBµV
αf = 10 kHz
fRF = 48.25 MHz
100
108
dBµV
αf = 10 kHz
fRF = 399.25 MHz
5-7
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
N + 5 pulling,
PLL unlocked
Oscillator
phase noise1).
IF suppression
typ
Unit
Test Conditions
L
Item
max
N+5
-50
dBc
fRF = 48.25 MHz,
fRF1 = 83.25 MHz,
PRF=P RF1 = 80dBµV
N+5
-50
dBc
fRF = 399.25 MHz,
fRF1 = 439.25 MHz,
PRF=P RF1 = 80dBµV
χ OSC
-58
-60
dBc/Hz
fm = 1kHz
χ OSC
-88
-90
dBc/Hz
fm = 10kHz
a
15
20
dB
Vi = 80 dBµV
HIGH Band Section (including IF amplifier)
Voltage gain
GV
Mixer noise figure
NF
31
34
37
dB
fRF = 367.25 MHz to
863.25 MHz,
fIF = 33.4MHz to
58.75 MHz
6
9
dB
fRF = 367.25 to
615.25 MHz
7
10
dB
fRF = 623.25 to
863.25 MHz
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.7 on
page 16
Vi
116
dBµV
fRFw = 503.25 MHz
Vi
117
dBµV
fRFw = 799.25 MHz
Input IP2
IIP2
139
dBµV
fRF1 = 423.25 MHz
fRF2 = 848.50 MHz,
PRF1 = PRF2
Input IP3
IIP3
108
dBµV
fRF1 = 503.25 MHz
fRF2 = 504.25 MHz
PRF1 = PRF2
IIP3
108
dBµV
fRF1 = 799.25 MHz
fRF2 = 800.25 MHz
PRF1 = PRF2
Output voltage causing 1 dB compression
Vo
121
dBµV
fRF = 503.25 MHz
Vo
121
dBµV
fRF = 799.25 MHz
Mixer input
impedance
Ri
14
20
26
τ
serial equivalent circuit, fRF = 600 MHz
Li
6
10
14
nH
serial equivalent circuit, fRF = 600 MHz
400
kHz
VS = 5 V10%
Oscillator frequency
shift, PLL unlocked
Wireless Components
αfOsc(V)
5-8
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
typ
Unit
Test Conditions
αfOsc(T)
800
kHz
αT = 25=C
Oscillator frequency
drift, PLL unlocked
αfOsc(t)
100
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
Vi
N + 5 pulling,
PLL unlocked
Oscillator
phase noise 1)
IF suppression
Item
max
Oscillator frequency
drift, PLL unlocked
Vi
L
100
108
dBµV
αf = 10 kHz
fRF = 375.25 MHz
100
108
dBµV
αf = 10 kHz
fRF = 847.25 MHz
Vi
-50
dBc
fRF = 471.25 MHz,
fRF1 = 511.25 MHz,
PRF =PRF1 = 80dBµV
Vi
-50
dBc
fRF = 847.25 MHz,
fRF1 = 887.25 MHz,
PRF=P RF1 = 80 dBµV
χ OSC
-58
-60
dBc/Hz
fm = 1kHz
χ OSC
-88
-90
dBc/Hz
fm = 10kHz
a
15
20
dB
Vi = 80 dBµV
serial equivalent
circuit,
fIF = 38.9 MHz
SAW preamplifier
IF output impedance,
double ended
RIF
125
τ
LIF
10
nH
IF output impedance,
single ended
RIF
75
τ
LIF
5
nH
serial equivalent
circuit,
fIF = 38.9 MHz
Rejection at the IF outputs
Divider interference
level 2).
Vo
Channel S02 beat
INT S02
rejection
30
66
dBµV
dBc
3).
fRF = 76.25 MHz
PRF = 80 dBµV
This value is only guaranteed in lab.
1). Measured in the evaluation board (see Chapter 4), worst case in band
2). This is the level of divider interferences close to the IF frequency. For example channel S3:
fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Measured in the evaluation
board (see Chapter 4).
3). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz.
The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in evaluation board
(see Chapter 4).
Wireless Components
5-9
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Address Byte
1
1
0
0
0
MA1
MA0
0
A
Progr. Divider Byte 1
0
N14
N13
N12
N11
N10
N9
N8
A
Progr. Divider Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1
CP
T1
T0
FP
RSA
RSB
OS
A
Bandswitch Byte
x
x
x
x
x
PHIGH
PLOW
PMID
A
1).
1).2).
1). 2).
Write Data
Read Data
Address Byte
Status Byte
1
1
0
0
0
MA1
MA0
1
A
POR
FL
x
x
x
x
x
x
A
1). see Table 5-9 IC frequency range selection on page 11
2). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Table 5-5 Description of symbols
Description
Symbol
MA0, MA1
Address selection bits (see Table 5-6 Address selection on page 11)
N14 to N0
programmable divider bits:
N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0
CP
Charge pump current:
T1, T0
test bits (see Table 5-7 Test modes on page 11)
FP
reserved for future purposes, actually ignored, default: 1
RSA, RSB
reference divider bits (see Table 5-8 Reference divider ratio on page 11)
OS
Tuning amplifier control bit: bit = 0: enable VT
bit = 1: disable VT
PLOW, PMID, PHIGH
NPN ports control bits:
FL
PLL lock flag, bit = 1: loop is locked
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
Wireless Components
bit = 0: charge pump current = 50 µA
bit = 1: charge pump current = 220µA
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
(see Table 5-9 IC frequency range selection on page 11)
5 - 10
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-6 Address selection
Voltage at AS
MA1
MA0
(0...0.1) * V CC
0
0
open circuit
0
1
(0.4...0.6) * V CC
1
0
(0.9...1) * V CC
1
1
Test mode
T1
T0
Normal operation
0
0
Charge pump output, CP is in high-impedance state
0
1
PLOW = fdiv output, PMID = fref output
1
0
not used
1
1
Table 5-7 Test modes
Table 5-8 Reference divider ratio
fref1).
RSA
RSB
80
50 kHz
0
0
128
31.25 kHz
0
1
24
166.7 kHz
1
0
64
62.5 kHz
1
1
Bit 2 (PHIGH)
Bit 1 (PLOW)1).
Bit 0 (PMID) 1.)
LOW/MID (VHF)
0
1
0
LOW/MID (VHF)
0
0
1
HIGH (UHF)
1
0
0
Reference divider ratio
1). With a 4 MHz quartz.
Table 5-9
IC frequency range selection
Frequency range
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Wireless Components
5 - 11
Specification, April 2000
Wireless Components
Ack.
1st Byte
Ack.
2nd Byte Ack.
MA MA R/W
5 - 12
Note: SDA:
SCL:
Telegram examples:
Abbreviations:
Start-ADB-DB1-DB2-CB-BB-Stop
Start= start condition
Start-ADB-CB-BB-DB1-DB2-Stop
ADB= address byte
Start-ADB-DB1-DB2-Stop
DB1= prog. divider byte 1
Start-ADB-CB-BB-Stop
DB2= prog. divider byte 2
3rd Byte Ack. 4th Byte
Ack.
5.3 I2C Bus Timing Diagram
Addressing
TUA6020
Stop= stop condition
preliminarytarget
BB= Bandswitch byte
Reference
Specification, April 2000
CB= Control byte
TUA6020
preliminarytarget
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID band
LOW/
MIDIN
50 Ω
Vmeas
50 Ω
V
RMS
Votmeter
IFOUT
Device
under
Test
Vi
Transformer
N1
N2
50 Ω
spectrum
analyser
V0
C
V'meas
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
5.4.2
Zi >> 50 τ => V i = 2 x Vmeas = 80 dBµV
Vi = Vmeas + 6dB = 80 dBµV
V0 = V’meas + 16 dB (transformer ratio N1:N2 and transformer loss)
Gv = 20 log(V0 / Vi)
Gain (GV) test Set-up in HIGH band
HIGHIN IFOUT
50 Ω
Vmeas
RMS
Votmeter
V
50 Ω
Vi
Balun
1:1
Device
under
Test
Transformer
N1
N2
V0
C
V'meas
50 Ω
spectrum
analyser
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
Vi = Vmeas = 70 dBµV
V0 = V’meas + 16 dB (transformer ratio N1:N2 and transformer loss)
Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
Wireless Components
5 - 13
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID band
22p
15p
1n
In
1n
In
Out
Out
7 turns
wire ⍪ 0.5 mm
coil ⍪ 5.5 mm
22p
50 τ semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
Nfm
For fRF = 50 MHz
For fRF = 150 MHz
loss = 0 dB
image suppression = 16 dB
loss = 1.3 dB
image suppression = 13 dB
5.4.4
Noise
Source
Noise Figure Test Set-up in LOW/MID band
IN
OUT
Matching
Circuit
LOW/
MIDIN
IFOUT
Transformer
Device
under
Test
N1
N2
Noise
Figure
Meter
C
IFOUT
N1 : N2 = 10 : 2 turns
NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 14
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.5
Noise Figure Test Set-up in HIGH band
Noise
Source
HIGHIN IFOUT
Device
under
Test
Balun
1:1
Noise
Figure
Meter
Transformer
N1
N2
C
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6
Cross modulation Test Set-up in LOW/MID band
Vmeas
50 Ω
RMS
Votmeter
unwanted
signal
source
AM = 80 %
A
LOW/
MIDIN
C
50 Ω
Hybrid
Vi
50 Ω
B
wanted
signal
source
V
D
IFOUT
Device
under
Test
Transformer
N1
18 dB
attenuator
N2
38.9 MHz
V0
C
V
V'meas
IFOUT
N1 : N2 = 10 : 2 turns
50 Ω
50 Ω
modulation
analyser
RMS
Votmeter
XVHF2
Wireless Components
Zi >> 50 τ => Vi = 2 x Vmeas
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
5 - 15
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.7
Cross modulation Test Set-up in HIGH band
Vmeas
V
50 Ω
RMS
Votmeter
unwanted
signal
source
AM = 80 %
A
C
HIGHIN IFOUT
50 Ω
Hybrid
Vi
Device
under
Test
Balun
1:1
50 Ω
B
D
Transformer
N1
N2
38.9 MHz
V0
C
V
V'meas
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
wanted
signal
source
18 dB
attenuator
50 Ω
50 Ω
modulation
analyser
RMS
Votmeter
XUHF2
5.4.8
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0
18p
4 MHz
Device under
Test
5k
PMID
5k
fref
PLOW
fdiv
Counter
Counter
fQ = fref * R
R: reference divider ratio
fVCO = fdiv * N
N: divider ratio
MEAS_COF
Wireless Components
5 - 16
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.5 Electrical Diagrams
5.5.1
Input admittance (S11) of the LOW/MID band mixer input
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS (single ended)
0.4
3
0.3
4
0.2
5
0.1
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
20
20
0
48.25 MHz
20
10
0.1
407.25 MHz
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
5.5.2
Input impedance (S11) of the HIGH band mixer input
1.5
1
0.9
0.8
0.5
2
0.6
0.7
Z0 = 50 τ (balanced)
0.4
3
0.3
4
5
0.2
855.25 MHz
10
0.1
415.25 MHz
20
10
5
4
3
2
1.5
0.8
0.9
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
0
Rdiff
20
0.1
10
0.2
5
4
0.3
3
Wireless Components
5 - 17
1.5
1
0.8
0.9
0.7
0.6
2
0.5
0.4
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.5.3
Output admittance (S22) of the Mixer output
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS (balanced)
0.4
3
0.3
4
0.2
5
0.1
10
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
0.1
0
20
20
Rdiff
38.9 MHz
20
10
0.1
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
5.5.4
Output impedance (S22) of the IF output
1.5
1
0.9
0.8
0.5
2
0.6
0.7
Z0 = 50 τ (single/ double ended)
0.4
3
0.3
4
5
0.2
10
0.1
Rse
20
10
5
4
3
2
1.5
0.8
0.9
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
0
Rdiff
20
0.1
10
0.2
5
4
0.3
3
Wireless Components
5 - 18
1.5
1
0.8
0.9
0.7
0.6
2
0.5
0.4
Specification, April 2000