Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHT6N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Surface mounting package QUICK REFERENCE DATA ID = 5.9 A RDS(ON) ≤ 30 mΩ (VGS = 5 V) g s GENERAL DESCRIPTION VDSS = 30 V d PINNING N-channel enhancement mode logic level field-effect power transistor using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. PIN SOT223 DESCRIPTION 1 gate 2 drain 3 source tab RDS(ON) ≤ 28 mΩ (VGS = 10 V) 4 drain 2 1 The PHT6N03LT is supplied in the SOT223 surface mounting package. 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 30 30 ± 13 5.9 4.1 23.6 1.8 150 V V V A A A W ˚C MIN. MAX. UNIT - 2 kV Tamb = 25 ˚C; VGS = 10 V Tamb = 100 ˚C; VGS = 10 V Tamb = 25 ˚C ESD LIMITING VALUE SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 kΩ) THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-sp mounted on any pcb - - 15 K/W mounted on test pcb of fig:17 - 70 - K/W Rth j-a Thermal resistance junction to solder point Thermal resistance junction to ambient January 1998 MIN. 1 TYP. MAX. UNIT Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N03LT ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = 0.25 mA; Tj = -55˚C IG = 1 mA VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C RDS(ON) gfs IDSS IGSS Drain-source on-state resistance VGS = 5 V; ID = 3.2 A VGS = 10 V; ID = 3.2 A VGS = 5 V; ID = 3.2 A; Tj = 150˚C Forward transconductance VDS = 25 V; ID = 5.9 A Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 150˚C Gate source leakage current VGS = ±5 V; VDS = 0 V Tj = 150˚C TYP. MAX. UNIT 30 27 10 - - V V V 1 0.6 8 - 1.5 24 18 14 0.05 0.02 - 2 2.3 30 28 51 10 500 1 10 V V V mΩ mΩ mΩ S µA µA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 5.9 A; VDD = 24 V; VGS = 5 V - 24 3 11 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 5.9 A; VGS = 5 V; RG = 5 Ω Resistive load - 30 80 95 40 45 130 135 55 ns ns ns ns Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad - 3.5 3.5 7.5 - nH nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 270 140 - pF pF pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM January 1998 CONDITIONS MIN. TYP. MAX. UNIT - - 5.9 A - - 10 A IF = 5.9 A; VGS = 0 V - 0.75 1.2 V IF = 5.9 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 100 0.4 - ns µC 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N03LT AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS ID = 5.9 A; VDD ≤ 15 V; VGS = 10 V; RGS = 50 Ω; Tamb = 25 ˚C Drain-source non-repetitive unclamped inductive turn-off energy 120 Normalised Power Derating PD% 100 MAX. UNIT - 60 mJ ID / A 7830-30 110 DS 100 90 MIN. ) ON 10 / ID =V S( tp = 10 us RD 80 70 100 us 60 1 1 ms 50 DC 40 10 ms 30 0.1 100 ms 20 10 0 0 20 40 60 80 100 Tamb / C 120 0.01 0.1 140 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tamb) 120 1 100 1000 Fig.3. Safe operating area. Tamb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 10 VDS / V 1E+02 110 100 90 1E+01 80 70 60 1E+00 BUKX83 Zth j-amb / (K/W) D= 0.5 0.2 0.1 0.05 0.02 50 PD tp D= 40 30 tp T 1E-01 20 10 0 0 20 40 60 80 100 Ambient temperature, Tamb (C) 120 1E-02 1E-07 140 1E-05 1E-03 1E-01 1E+01 1E+03 t/s Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tamb); conditions: VGS ≥ 5 V January 1998 t T 0 Fig.4. Transient thermal impedance. Zth j-amb = f(t); parameter D = tp/T 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET ID / A 10 60 PHT6N03LT BUK9830-30 5 gfs / S 20 4.5 9830-30 6 50 Tj / C = 25 4 40 150 VGS / V = 3.5 30 20 3 10 0 10 2.5 0 2 4 6 8 0 10 0 10 20 VDS / V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 60 RDS(ON) / mOhm 3 40 50 60 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 9830-30 4 3.5 30 ID / A 2 a SOT223 30V Trench Normalised RDS(ON) = f(Tj) 50 1.5 40 4.5 5 30 10 20 6 0.5 VGS / V = 10 0 1 0 10 20 30 ID / A 40 50 0 -50 60 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 60 ID / A 0 50 Tj / C 100 150 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 3.2 A; VGS = 5 V 9830-30 2.5 BUK959-60 VGS(TO) / V max. 50 2 Tj / C = 25 40 typ. 1.5 150 30 min. 1 20 0.5 10 0 0 1 2 3 VGS / V 4 5 0 -100 6 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj January 1998 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N03LT Sub-Threshold Conduction 1E-01 60 IF / A 9830-30 50 1E-02 40 2% 1E-03 typ 98% 30 Tj / C = 150 1E-04 20 1E-05 10 0 1E-05 0 0.5 1 1.5 2 2.5 C / pF 0.5 1 VSDS / V 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 10000 0 25 1.5 2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 9528-30 120 WDSS% 110 100 90 80 Ciss 70 60 1000 50 40 Coss 30 Crss 20 10 100 0.1 1 10 0 100 20 VDS / V 40 60 80 100 120 140 Ambient temperature, Tamb (C) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz VGS / V Fig.15. Normalised avalanche energy rating. WDSS% = f(Tamb); conditions: ID = 5.9 A 9830-30 5 VDS / V = 6 4 VDD + 24 L VDS - 3 VGS -ID/100 2 0 1 0 T.U.T. RGS 0 5 10 15 20 R 01 shunt 25 QG / nC Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 5.9 A; parameter VDS January 1998 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHT6N03LT PRINTED CIRCUIT BOARD Dimensions in mm. 36 18 60 4.5 4.6 9 10 7 15 50 Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). January 1998 6 Rev 1.300