1/7 ◇Structure ◇Product Series ◇Type ◇Applications ◇Functions Silicon monolithic integrated circuit Lens control LSI BU24026GU Digital still cameras ・Waveforming circuit (3 channels) ・PI driving circuit (2 channels) ・Driver block (1-6 channels) : Constant voltage control type H-bridge ・Driver block (7 channel) : Constant current control type H-bridge ◇Absolute maximum ratings (Ta 25C) Parameter Input voltage Symbol DVDD MVCC VDDAMP VIN Input/output current IIN Power supply voltage Limits -0.3～4.5 -0.3～7.0 -0.3～7.0 -0.3～DVDD+0.3 ±500 ＋100 -55～125 -20～85 1.37 Unit Symbol DVDD MVCC Limits 2.7～3.6 2.7～5.5 Unit Ｖ Ｖ VDDAMP 2.7～5.5 Ｖ FCLK 1～27.5 ＭＨｚ Storage temperature range TSTG Operating temperature range TOPE Permissible dissipation PD This product is not designed for anti-radiation applications. *1To use at a temperature higher than Ta=25℃, derate 13.7mW per 1℃. Remark V V V V ｍＡ ｍＡ ℃ ℃ Ｗ Driver block (by MVCC pin) by PIOUT pin *1 (At mounting 50 mm × 58 mm × 1.75mm glass epoxy board. ) ◇Operating conditions(Ta 25C) Parameter Digital power supply voltage Driver power supply voltage Constant current control amplifier power supply voltage clock operating frequency REV. B Remark DVDD≦MVCC Reference clock 2/7 ◇Electrical characteristics (Unless otherwise specified, Ta25C, DVDD3.0V, MVCC5.0V, VDDAMP5.0V, DVSSMGND0.0V) Parameter MIN. Limits TYP. MIN. - 30 0 8.5 100 5 15.0 VIL VIH IIL IIH VOL VOH DVSS 0.7DVDD 0 0 DVSS 0.8DVDD － － － － － － 0.3DVDD DVDD 10 10 0.2DVDD DVDD PIVO - 0.28 0.5 1/2DVDD - 0.1 Symbol <current consumption> Quiescence (DVDD) (MVCC) (DVDD) Operation <Logic block> Low-level input voltage High-level input voltage Low-level input current High-level input current Low-level output voltage High-level output voltage <PI driving circuit> Output voltage <Waveforming circuit 1ch> Detective voltage range Detective voltage error ISSD ISSVM IDDD Vth V <Waveforming circuit 2,3ch> High-level threshold voltage ＶｔｈＨ1 Low-level threshold voltage ＶｔｈＬ1 Hysteresis width ＨＹＳ threshold voltage ＶｔｈＨ2 <Constant voltage driver block> ON-resistance Ron OFF-leak current IOZ Turn-ON time tON Turn-OFF time tOFF Average voltage accuracy Vdiff <Constant current driver block> ON-resistance Ron OFF-leak current IOZ Output voltage Turn-ON time Turn-OFF time VO tON tOFF Unit μＡ μＡ ｍＡ V V μＡ Condition CMD_RS=0 CMD_RS=0 CMD_RS=1 μＡ V V VIL = DVSS VIH = DVDD IOL = 1.0mA IOH = 1.0mA 0.50 V IIH = 50mA 1/2DVDD 2. 5 1/2DVDD + 0.1 V Ｖ SI1 Waveforming Vth = 20h setting － 0.6 0.2 1.0 － － － － 1.9 － 0.6 1.85 V V V V SI2、SI3 (DVDD=3.25V), Hys ON -10 -5 1.5 0 0.15 0.1 - 2.0 10 1.0 0.5 +5 Ω μＡ μＳ μＳ ％ -10 188 - 0.9 0 200 0.15 0.1 1.5 10 212 1.0 0.5 Ω μＡ mV μＳ μＳ REV. B SI2、SI3 (DVDD=3.25V), Hys ON SI2、SI3 (DVDD=3.25V), Hys ON SI2、SI3 (DVDD=3.25V), Hys OFF IO = ±100mA Output Hiz setting Vdiff = 2.0V setting. IO = ±100mA Output Hiz setting DAC setting: 1010_0111, RRNF=1[Ω] 3/7 ◇3-wire serial interface Control commands are framed by 16-bit serial input (MSB first) and input through the CSB, SCLK, and SDATA pins. 4 higher-order bits specify addresses, while the remaining 12 bits specify data. Data of every bit is input through the SDATA pin, retrieved on the rising edges of SCLK. Data becomes valid in the CSB Low area. The loading timing is different in the resistor. (as shown in “Note 5,6”) Furthermore, the interface will be synchronized with the falling edges of SCLK to output the SOUT data of the 12 bits. CSB SCLK x SDATA D15 D14 D13 D12 D11 D10 D9 D8 D7 Address D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 x Data x SOUT D6 D11 D10 D9 D8 D7 D6 Hiz Hiz <Register map> 15 0 Address[3:0] 14 13 0 0 12 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 0 Addresses other than those above 11 10 ModeA[1:0] 0 0 0 0 1 1 EnA RtA Ach status[1:0] ModeB[1:0] 0 0 0 0 1 1 EnB RtB Bch status[1:0] ModeC[1:0] 0 0 0 0 1 0 1 1 1 1 EnC RtC Cch status[1:0] 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 0 1 1 9 8 SelA[1:0] 0 0 1 0 1 0 7 0 Data[11:0] 6 5 4 3 2 1 0 Ach different output voltage[6:0] Ach Cycle[7:0] Ach Cycle[15:8] 0 0 APOS[1:0] 0 0 0 ASTOP Ach Pulse[9:0] Ach operation pulse number[9:0] SelB[1:0] 0 Bch different output voltage [6:0] 0 0 Bch Cycle[7:0] 1 0 Bch Cycle[15:8] 1 0 0 0 BPOS[1:0] 0 0 0 BSTOP Bch Pulse[9:0] Bch operation pulse number[9:0] SelC[1:0] 0 Cch different output voltage [6:0] 0 0 Cch Cycle[7:0] 1 0 Cch Cycle[15:8] 1 5_PWM_Ct[1:0] 5ch different output voltage[6:0] 0 6_PWM_Ct[1:0] 6ch different output voltage[6:0] 1 0 0 0 CPOS[1:0] 0 0 0 CSTOP Cch Pulse[9:0] Cch operation pulse number[9:0] Chopping[1:0] CacheM SEL56[2:0] P_CTRL CLK_DIV[2:0] PI_CTRL1 PI_CTRL2 0 0 0 0 0 0 0 0 1 0 0 5_PULSE_CNT 5_PULSE_BASE[1:0] 0 6_PULSE_CNT 6_PULSE_BASE[1:0] 0 0 5_PULSE_COUNT[7:0] 0 1 6_PULSE_COUNT[7:0] 1 0 0 EXT_EN 0 EXT_RT EXT_NUM[3:0] 0 0 EXT_PAT1 EXT_PAT0 0 1 EXT_PAT3 EXT_PAT2 1 0 EXT_PAT5 EXT_PAT4 1 1 EXT_PAT7 EXT_PAT6 0 0 EXT_PAT9 EXT_PAT8 0 1 EXT_PAT11 EXT_PAT10 1 0 EXT_PAT13 EXT_PAT12 1 1 EXT_PAT15 EXT_PAT14 0 0 Constant current driver reference voltage adjustment 8bit DAC[7:0] 0 0 0 0 0 0 0 0 7_CTRL[1:0] 0 0 0 0 Wavefoming circuit 1 Vthh[5:0] 0 1 0 0 Wavefoming circuit 1 Vthl[5:0] 1 0 0 0 0 0 0 0 HYS3 HYS2 0 0 0 0 0 0 0 0 0 CMD_RS Setting prohibited (Note 1) The notations A, B, C in the register map correspond to Ach, Bch and Cch respectively. (Note 2) The Ach is defined as 1ch and 2ch driver output, the Bch as 3ch and 4ch driver output, and Cch as 5ch and 6ch driver output. (Note 3) After resetting (Power ON reset, and CMD_RS), “initial setting” is saved in all registers. REV. B 4/7 (Note 4) The addresses 4’b0011, 4’b0111, and 4’b1011 have data (status[1:0] ,operation pulse number[9:0]), which are internal register values and output from the SOUT pin. (Note 5) For Mode, different output voltage, Cycle, En, and Rt registers, data that are written before the access to the Pulse register becomes valid, and determined at the rising edge of CSB after the access to the Pulse register. (The Mode, different output voltage, Cycle, En, Rt, and Pulse registers contain Cache registers, but any registers other than those do not contain with such registers.) (Note 6) For POS, STOP, PWM_Ct, and different output voltage registers, data are determined at the rising edge of CSB, and for any registers other than those, data are determined at the rising edge of 16th SCLK . DVDD DVDD SO1 SI1 SO2 SI2 SO3 SI3 PIOUT1 PIOUT2 ◇Block Diagram DVDD MVCC34 MVCC56 PreDriver PreDriver OUT5B OUT5A MGND56 DVDD MGND34 DVDD Analog Feed-Back Analog Feed-Back Low Power Voltage On Detect Reset MVCC56 Thermal Shut-Down MVCC34 PreDriver PreDriver OUT6B OUT6A OUT3A OUT3B OUT4A OUT4B MGND56 MGND34 Analog Feed-Back Analog Feed-Back MVCC12 VDDAMP PreDriver OUT2A OUT2B RNF MGND12 DAC Logic + OUT7B OUT7A Analog Feed-Back MVCC12 MGND7 PreDriver SENSE OUT1A OUT1B MGND12 REV. B IN56 IN7 FCLK CSB CS SDATA SCLK SOUT STATE1 STATE2 STATE3 DVSS DVDD Analog Feed-Back 5/7 ◇Pin functions Land E6 Pin name DVDD Power Function - Digital power Ground I/O supply E2 DVSS - C2 FCLK DVDD main clock logic input D4 CSB DVDD B3 SCLK DVDD D3 SDATA B5 Power supply GND Handling of unused pins - I pull down(DVSS) Serial control chip select input I pull up(DVDD) I pull down(DVSS) DVDD Serial control clock input Serial control data input I pull down(DVSS) SOUT DVDD Serial control data output O open E4 STATE1 DVDD STATE1 1,2ch condition logic output O open F4 STATE2 DVDD STATE2 3,4ch condition logic output O open F5 STATE3 DVDD STATE 3 5,6ch condition logic output / 5,6ch control logic input I／O(initial condition：O) open D5 IN56 DVDD 5,6ch control logic input I pull down(DVSS) C5 IN7 DVDD 7ch control logic input I pull down(DVSS) E3 PIOUT1 DVDD O open D2 PIOUT2 DVDD PI driving output1 PI driving output2 O open E5 SI1 DVDD 1ch waveforming input(With adjustment function of threshold voltage) I pull down(DVSS) B4 SI2 DVDD 2ch waveforming input I pull down(DVSS) C6 SI3 DVDD 3ch waveforming input I pull down(DVSS) F3 SO1 DVDD 1ch waveforming output O open C4 SO2 DVDD 2ch waveforming output O open D6 SO3 DVDD O open A1, B2※ MVCC12 - 3ch waveforming output 1-2channel driver power supply A4 MGND12 - 1-2channel driver ground A2 OUT1A A3 OUT1B A5 OUT2A A6 OUT2B Power supply GND - MVCC12 1-channel driver A output MVCC12 1-channel driver B output O O open MVCC12 2-channel driver A output MVCC12 2-channel driver B output O open A7, B6※ MVCC34 - 3-4channel driver power supply D7 MGND34 - 3-4channel driver ground B7 OUT3A C7 OUT3B E7 OUT4A F7 OUT4B G5 MVCC56 - 5-6channel driver power supply G3 MGND56 - 5-6channel driver ground G6 OUT5A O Power supply GND open open - MVCC34 3-channel driver A output MVCC34 3-channel driver B output O open O open MVCC34 4-channel driver A output MVCC34 4-channel driver B output O open O Power supply GND open - MVCC56 5-channel driver A output MVCC56 5-channel driver B output O O open MVCC56 6-channel driver A output MVCC56 6-channel driver B output O open O open F6, G7※ OUT5B G4 OUT6A G2 OUT6B D1 RNF - 7-channel driver power supply B1 MGND7 - 7-channel driver ground VDDAMP - Power supply of constant current driver control F2, G1※ - Power supply VDDAMP Negative input for constant current driver control open - GND - Power supply - F1 SENSE I pull down(MGND7) E1 OUT7A RNF 7-channel driver A output O open C1 OUT7B RNF 7-channel driver B output O open C3 INDEX - Index pin - - ※It is not possible to use corner pin only. (Corner pins are A1, A7, G1, and G7.) Please use A1-B2, A7-B6, F2-G1, F6-G7 pair respectively or using B2, B6, F2, F6 only. REV. B 6/7 ◇Pin related equivalent circuit diagrams Pin Equivalent circuit diagram FCLK, CSB, DVDD SCLK Pin Equivalent circuit diagram SENSE DVDD VDDAMP VDDAMP SDATA, IN56, IN7, SI2, SI3 P + - P *SI2,SI3 are the Schmitt inputs. DVSS DVSS MGND7 SOUT, STATE1, PIOUT1, PIOUT2 DVDD DVDD STATE2, MGND7 DVDD SO1, SO2, SO3 P P DVSS DVSS OUT1A, OUT1B, DVSS ＭVCC34 OUT3A, OUT3B, ＭVCC12 OUT2A, OUT2B OUT4A, OUT4B P P P P MGND34 MGND12 ＭVCC56 OUT5A, OUT5B OUT7A, OUT7B OUT6A, OUT6B P RNF RNF P P P P MGND56 STATE3 DVDD MGND7 SI1 DVDD DVDD P DVDD P DVSS DVSS DVSS DVSS REV. B 7/7 ◇Pin assignment diagram (reverse side) ◇Outline dimensions/Marking figure G VDDAMP OUT６B MGND５６ OUT６A MVCC５６ OUT５A OUT５B F SENSE VDDAMP SO１ STATE２ STATE３ OUT５B OUT４B E OUT７A DVSS PIOUT１ STATE１ SI１ DVDD OUT４A D RNF PIOUT2 SDATA CSB IN５６ SO３ MGND３４ C OUT7B FCLK SO２ IN７ SI３ OUT３B B MGND７ MVCC12 SCLK SI２ SOUT MVCC３４ OUT３A A MVCC12 OUT1A OUT1B MGND１２ OUT2A OUT２B MVCC３４ 1 2 3 4 5 6 7 Ｕ24026 Ｌｏｔ Ｎｏ． (UNIT : mm) VCSP85H3 ◇Cautions on use (1) Absolute maximum ratings If applied voltage, operating temperature range, or other absolute maximum ratings are exceeded, the LSI may be damaged. Do not apply voltages or temperatures that exceed the absolute maximum ratings. If you expect that any voltage or temperature could be exceeding the absolute maximum ratings, take physical safety measures such as fuses to prevent any conditions exceeding the absolute maximum ratings from being applied to the LSI. (2) GND potential Maintain the GND pin at the minimum voltage even under any operating conditions. Actually check to be sure that none of the pins have voltage lower than that of GND pin, including transient phenomena. (3) Thermal design With consideration given to the permissible dissipation under actual use conditions, perform thermal design so that adequate margins will be provided. (4) Short circuit between pins and malfunctions To mount the LSI on a board, pay utmost attention to the orientation and displacement of the LSI. Faulty mounting to apply a voltage to the LSI may cause damage to the LSI. Furthermore, the LSI may also be damaged if any foreign matters enter between pins, between pin and power supply, or between pin and GND of the LSI. (5) Operation in strong magnetic field Make a thorough evaluation on use of the LSI in a strong magnetic field. Not doing so may malfunction the LSI. REV. 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