CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com N-Channel NexFET™ Power MOSFETs Check for Samples: CSD16301Q2 FEATURES 1 • • • • • • 2 PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Pb Free Terminal Plating RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package Drain to Source Voltage 25 V Qg Gate Charge Total (–4.5V) 2 nC Qgd Gate Charge Gate to Drain RDS(on) The NexFET™ power MOSFET has been designed to minimize losses in power conversion and load management applications. The SON 2x2 offers excellent thermal performance for the size of the package. Figure 1. Top View 5 D D D 2 G 3 S 4 S mΩ 19 mΩ V Media SON 2-mm × 2-mm Plastic Package Qty Ship 13-Inch Reel 3000 Tape and Reel 7-Inch Reel 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +10 / –8 V 5 A Continuous Drain Current, TC = 25°C Continuous Drain Current(1) 5 A IDM Pulsed Drain Current, TA = 25°C(2) 20 A PD Power Dissipation(1) 2.3 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 14A, L = 0.1mH, RG = 25Ω 10 mJ RDS(on) vs VGS GATE CHARGE 80 8 ID = 4A 70 7 60 50 VG − Gate Voltage − V RDS(on) − On-State Resistance − mΩ 23 (1) Packaged Limited (2) Pulse duration 10μs, duty cycle ≤2% P0108-01 TC = 125°C 40 30 20 10 0 VGS = 4.5V VGS = 8V TA = 25°C unless otherwise stated ID D mΩ 1.1 Package CSD16301Q2 6 27 Threshold Voltage Device DESCRIPTION 1 nC VGS = 3V ORDERING INFORMATION DC-DC Converters Battery and Load Management Applications D 0.4 Drain to Source On Resistance VGS(th) APPLICATIONS • • VDS 1 2 3 6 5 4 3 2 1 TC = 25°C 0 ID = 4A VDS = 12.5V 4 5 6 7 VGS − Gate to Source Voltage − V 8 9 10 G006 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Qg − Gate Charge − nC G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/–8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA 25 0.9 VGS = 3V, IDS = 4A RDS(on) gfs Drain to Source On Resistance Transconductance V 1 μA 100 nA 1.1 1.55 27 34 mΩ V VGS = 4.5V, IDS = 4A 23 29 mΩ VGS = 8V, IDS = 4A 19 24 mΩ VDS = 15V, IDS = 4A 16.5 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance 260 340 165 215 CRSS pF Reverse Transfer Capacitance 13 17 pF 1.3 2.6 Ω 2 2.8 nC VGS = 0V, VDS = 12.5V, f = 1MHz Rg Series Gate Resistance Qg Gate Charge Total (4.5V) Qgd Gate Charge – Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VDS = 10V, IDS = 4A 0.4 nC 0.6 nC 0.3 nC 3 nC 2.7 ns 4.4 ns 4.1 ns 1.7 ns VDS = 12.5V, VGS = 0V VDS = 12.5V, VGS = 4.5V, IDS = 4A RG = 2Ω pF Diode Characteristics VSD Diode Forward Voltage IDS = 4A, VGS = 0V 0.8 Qrr Reverse Recovery Charge VDD = 12.5V, IF = 4A, di/dt = 200A/μs 5.1 1 nC V trr Reverse Recovery Time VDD = 12.5V, IF = 4A, di/dt = 200A/μs 11 ns THERMAL INFORMATION THERMAL METRIC (1) (2) 69 (3) 8.4 Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter θJCbot Junction-to-case (bottom) thermal resistance (4) 2 6 PINS (3) (4) θJA (1) (2) (3) CSD16301Q2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Copyright © 2009–2011, Texas Instruments Incorporated CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com GATE GATE Source N-Chan N-Chan Max RθJA = 69°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 220°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0164-02 M0164-01 TYPICAL MOSFET CHARACTERISTICS TA = 25°C, unless otherwise specified ZθJA − Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.1 Duty Cycle = t1/t2 0.05 0.01 P 0.02 0.01 t1 t2 Single Pulse Typical RqJA = 177oC/W (min Cu) TJ = P x ZqJA x RqJA 0.001 0.0001 0.001 0.01 0.1 1 t P − Pulse Duration − s 10 100 1k G012 Figure 2. Transient Thermal Impedance Copyright © 2009–2011, Texas Instruments Incorporated 3 CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C, unless otherwise specified 10 10 8 7 VGS = 3.5V 6 VGS = 2.5V 5 4 VGS = 2V 3 2 VGS = 1.5V 1 0 0.0 0.5 VDS = 5V 9 VGS = 4.5V ID − Drain Current − A ID − Drain Current − A 9 8 7 TC = 125°C 6 5 TC = 25°C 4 3 2 TC = −55°C 1 1.0 1.5 0 1.00 2.0 VDS − Drain to Source Voltage − V 1.25 C − Capacitance − nF VG − Gate Voltage − V 5 4 3 2 COSS = CDS + CGD 0.4 G002 0.5 1.0 1.5 2.0 2.5 3.0 0.2 0.0 3.5 CISS = CGD + CGS 0.3 CRSS = CGD 0.1 Qg − Gate Charge − nC 0 5 10 15 20 25 VDS − Drain to Source Voltage − V G003 Figure 5. Gate Charge G004 Figure 6. Capacitance 1.4 80 ID = 250µA 1.2 RDS(on) − On-State Resistance − mΩ VGS(th) − Threshold Voltage − V 2.50 f = 1MHz VGS = 0V 0.5 1 1.0 0.8 0.6 0.4 0.2 −25 25 75 125 175 TC − Case Temperature − °C Figure 7. Threshold Voltage vs. Temperature 4 2.25 0.6 ID = 4A VDS = 12.5V 6 0.0 −75 2.00 Figure 4. Transfer Characteristics 8 0 0.0 1.75 VGS − Gate to Source Voltage − V G001 Figure 3. Saturation Characteristics 7 1.50 G005 ID = 4A 70 60 50 TC = 125°C 40 30 20 10 0 TC = 25°C 0 1 2 3 4 5 6 7 VGS − Gate to Source Voltage − V 8 9 10 G006 Figure 8. On-State Resistance vs. Gate to Source Voltage Copyright © 2009–2011, Texas Instruments Incorporated CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C, unless otherwise specified 10 ID = 4A VGS = 4.5V 1.6 1.4 ISD − Source to Drain Current − A Normalized On-State Resistance 1.8 1.2 1.0 0.8 0.6 0.4 1 0.1 TC = 125°C 0.01 TC = 25°C 0.001 0.2 0.0 −75 −25 25 75 125 0.0001 0.0 175 TC − Case Temperature − °C 0.2 0.6 0.8 VSD − Source to Drain Voltage − V G007 Figure 9. Normalized On-State Resistance vs. Temperature 1.0 G008 Figure 10. Typical Diode Forward Voltage 100 I(AV) − Peak Avalanche Current − A 100 ID − Drain Current − A 0.4 100ms 10 1ms 1 10ms Area Limited by RDS(on) 0.1 100ms 1s Single Pulse Typical RqJA = 177oC/W (min Cu) 0.01 0.01 0.1 DC 1 10 o 10 TC = 125 C 1 0.01 100 VD - Drain Voltage - V o TC = 25 C 0.1 1 10 100 t(AV) − Time in Avalanche − ms G009 Figure 11. Maximum Safe Operating Area Figure 12. Single Pulse Unclamped Inductive Switching 6 ID − Drain Current − A 5 4 3 2 1 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C 150 175 G011 Figure 13. Maximum Drain Current vs. Temperature Copyright © 2009–2011, Texas Instruments Incorporated 5 CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com MECHANICAL DATA Q2 Package Dimensions D2 D K3 K1 K K2 4 1 2 3 4 5 6 3 2 1 K4 E E1 E2 5 E3 6 L Pin 1 Dot Top View Pin 1 ID e b D1 A A1 C Bottom View Front View M0165-01 DIM MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 0.012 0.014 0.300 C 0.203 TYP D 2.000 TYP D1 0.900 0.950 D2 0.300 TYP E 2.000 TYP E1 0.900 1.000 0.002 0.008 TYP 0.080 TYP 1.000 0.036 0.038 0.080 TYP 1.100 0.036 0.040 0.280 TYP 0.0112 TYP E3 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP L 0.470 TYP 0.200 0.25 0.040 0.012 TYP E2 K4 6 INCHES 0.044 0.0188 TYP 0.300 0.008 0.010 0.012 Copyright © 2009–2011, Texas Instruments Incorporated CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com Recommended PCB Pattern 1.40 0.85 1.05 0.22 2.30 1.10 0.65 TYP 1 0.46 0.40 TYP 0.25 M0167-01 Note: All dimensions are in mm, unless otherwise specified. For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. Copyright © 2009–2011, Texas Instruments Incorporated 7 CSD16301Q2 SLPS235C – OCTOBER 2009 – REVISED JULY 2011 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A • Page Changed the Electrical Characteristics table - VGS(th) MAX value From: 1.4V To 1.55V ...................................................... 2 Changes from Revision A (December 2009) to Revision B Page • Added title to Figure 12 - Single Pulse Unclamped Inductive Switching .............................................................................. 5 • Deleted the Package Marking Information section ............................................................................................................... 7 Changes from Revision B (April 2010) to Revision C • 8 Page Added a 7-Inch Reel option to the Ordering Information Table ............................................................................................. 1 Copyright © 2009–2011, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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