SONY CXA3314ER

CXA3314ER
6GHz PLL
Description
The CXA3314ER is a general-purpose PLL IC
which directly frequency divides RF up to 6GHz in
combination with an external VCO and loop.
Features
• Low current consumption: 9mA (typ. at VCC = 3V)
• Low voltage operation: 2.7 to 3.3V
• Small package: 24-pin VQFN (plastic)
• Supports sleep mode: 10µA (max. at VCC = 3V)
• Data setting by a 3-wire interface
• Reference frequency divider
Reference counter: 15 bits (3 to 32767)
• Comparison frequency divider
Fixed frequency division: 4
Swallow counter:
5 bits (0 to 31)
Main counter:
13 bits (3 to 8191)
Comparison frequency
division value:
4 × (992 to 262143)
• Built-in charge pump circuit with high-speed pull-in
and normal modes
• Lock signal output function
24 pin VQFN (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
3.6
V
• Operating temperature
Topr –30 to +85 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
900
mW
Operating Condition
Supply voltage
VCC
2.7 to 3.3
V
Applications
This IC is ideal for the synthesizers of microwave
communications equipment up to 6GHz and
general-purpose PLL synthesizers such as in highspeed, high frequency measurement equipment.
• ETC (ITS) related
• VCO modules
• Wireless LAN communications
• High-speed, high frequency measurement
equipment
Structure
Bipolar silicon monolithic IC
Note on ESD strength
This product has a low ESD strength to ensure the high frequency characteristics.
Sony semiconductor devices are classified into ESD strength ranks from A to E based on ESD test results
according to Sony original criteria.
These ESD ranks are set for each test, and indicate the ESD risk for each breakdown model.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00782E2Z-PS
CXA3314ER
CPGND
DMPSW
REXT
REFIN
VSS
VSS
Block Diagram and Pin Configuration
18
17
16
15
14
13
CPOUT 19
Test
Circuit
Lock
Detector
CP
(Fast/Slow)
CPVCC 20
Buffer
I/2I
Reference
Counter
(15 bits)
Intermittent
Operation
Control Circuit
High-speed
Pull-in Control
SUB 21
12 LKDET
11 CEX
10 DATA
3-wire Control
PFD
RFINN 22
CLK
8
LE
7
TESTDIS
Main Counter
(13 bits)
2
3
NC
4
5
6
VDD
1
NC
Dual Modulus
(32, 33) Prescaler
VCC
GND 24
Swallow Counter
(5 bits)
VDD
Fixed
Frequency
Division
(4)
Prescaler
NC
RFINP 23
9
–2–
CXA3314ER
Pin Description
Pin
No.
Symbol
Standard DC
voltage [V]
Equivalent circuit
VCC
1
VCC
3
1
21
SUB
0
SUB
Power supply.
GND
0
Substrate.
Connect to GND normally.
Analog
circuit
block
21
24
Description
Ground.
24
GND
2, 3,
NC
4
—
No connected.
5
5, 6
VDD
3
VDD
6
Power supply for output stage.
Digtal
circuit
block
SUB
21
13, 14 VSS
0
Ground.
13
VSS
14
6
100
15
REFIN
1/2VCC
VDD
200 100k
15
Reference frequency signal
input.
13
21
VSS
SUB
6
VDD
I
16
REXT
0.15
8.5k
16
13 VSS
Internal reference current
setting.
Connect to GND via a external
resistor (1.8kΩ).
Icp = I × 6.7
I ≈ IRext
Icp: Charge pump current
I: Internal reference current
IRext: External resistor current
Internal charge pump current
switching.
21
SUB
–3–
CXA3314ER
Pin
No.
Symbol
Standard DC
voltage [V]
Equivalent circuit
Description
6
333
17
DMPSW
VDD
666
Connect to the loop filter via a
resistor.
17
—
13 VSS
21
SUB
CPVCC
18
CPGND
0
19
CPOUT
—
Ground for the charge pump
output.
20
19
Charge pump output.
SUB
21
20
CPVCC
3
Power supply for the charge
pump output.
18
CPGND
VCC
1
22
RFINN
Vcc – 0.9
22
23
2000
23
RFINP
2000
Vcc – 0.9
24
GND
–4–
VCO signal input.
CXA3314ER
Pin Description
Pin
No.
7
Symbol
TESTDIS
Equivalent circuit
I/O
I
5
Description
Test mode switch pin.
VDD
High: Active
Low: Test mode
6
8
LE
I
9
CLK
I
10
DATA
I
Latch input.
Clock input.
IN
Data input.
13
11
CEX
I
14
5
VSS
Power save function pins.
High: Power save
Low: Active
VDD
6
12
LKDET
O
Lock detection signal output.
•Active mode
High: Lock
Low: Unlock
•Test mode
Refer to “2. Test mode setting” on page 12.
OUT 12
13
14
VSS
–5–
CXA3314ER
Electrical Characteristics
Item
(VCC = 3V, Ta = 25°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
9
14
mA
10
µA
2
6
GHz
Current consumption
ICC
Current flowing to Pins 1, 6
and 20 during operation
(Pin 11 (CEX): 0)
Current consumption
(in sleep mode)
ICC
(PS)
Current flowing to Pins 1, 6
and 20 in sleep mode
(Pin 11 (CEX): High)
Operating frequency
F-RF
V-RF = –10dBm
Input level
V-RF
F-RF = 5.845GHz
–12
+10
dBm
Reference input operating
frequency
F-REF
V-REF = 0.2Vp-p
10
30
MHz
Reference input level
V-REF
F-REF = 10MHz
0.2
2.0
Vp-p
Max.
Unit
Design Reference Values
Item
CEX
DATA
CLK
LE
Symbol
Conditions
Min.
Typ.
High input voltage
VIH
—
VCC – 0.2
VCC
V
High input current
IIH
—
–1
+1
µA
Low input voltage
VIL
—
0
GND + 0.2
V
Low input current
IIL
—
–1
+1
µA
REFIN input resistance
RIREF
DC resistance value
100
kΩ
RFINN input resistance
RIRF
DC resistance value
2000
Ω
Pin 17 input resistance
ON
DC resistance value
3000
Ω
–6–
CXA3314ER
Electrical Characteristics Measurement Circuit and Application Circuit
51
1.8k
18
17
16
15
14
13
CPGND
DMPSW
REXT
REFIN
VSS
VSS
1000p
19 CPOUT
LKDET 12
0.1µ
20 CPVCC
3V
CEX 11
21 SUB
51
100p
51
100p
DATA 10
22 RFINN
CLK
9
23 RFINP
LE
8
TESTDIS
7
NC
NC
NC
VDD
VDD
0.1µ
VCC
24 GND
1
2
3
4
5
6
3V
0.1µ
3V
SMA
Terminal
Plane GND
Power line
50Ω strip
0.3mm line
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–7–
CXA3314ER
Description of Operation
The CXA3314ER can make the following operation settings using the three DT, CK and LE signals.
Item
Item number
Counter frequency division value and pull-in mode settings
1
Reference counter (R counter) frequency division value setting
1-1
Swallow counter and main counter (N counter) frequency division value settings
1-2
Pull-in mode setting
1-3
Initialization
1-4
Test mode
1-5
Test mode setting
2
Standby mode setting
3
1. Counter frequency division value and pull-in mode setting method
The CXA3314ER sets data using the three DT, CK and LE signals. At this time, serial data is input as
described below.
21-bit serial data is loaded via DT in order from the MSB at the rising edge of CK. After 21 bits have been
input, the data is actually set at the rising edge of LE.
DT
E = MSB
C2
C1 = LSB
MSB'
(F, Ven)
CK
LE
or
tch
teh
tcwl
tcs
tes
tew
tcwh
However, as mentioned above, if the counter overlaps with the preset timing of the frequency division value,
there is the risk that an incorrect preset value may be preset in the counter. Therefore, the frequency division
value should be set in sync with the counter output so as to avoid the preset timing. That is to say, the counter
frequency division value is set after waiting for up to one cycle of the previous comparison cycle. Therefore, CK
input is prohibited for the previous comparison cycle (Tcmp) after LE.
The AC characteristics are as follows.
Symbol
tcs
tch
tcwh
tcwl
tew
tes
teh
Item
Min.
Unit
Data to clock setup time
50
ns
Data to clock hold time
10
ns
Clock pulse width high
50
ns
Clock pulse width low
50
ns
Load enable pulse width
50
ns
Clock to load enable setup time
50
ns
Tcmp
ns
Clock load enable hold time
Tcmp: Previous comparison cycle
–8–
CXA3314ER
The final two bits of the serial input are the control bits (C1, C2), and the setting item is selected according to
these values. The setting items corresponding to the control bit values are as follows.
C1
C2
Setting item
0
0
R counter frequency division value setting, pull-in mode setting
1
0
N counter frequency division value setting, pull-in start/end
1
1
Initialization
0
1
Test mode setting
1-1. Reference counter (R counter) frequency division value setting
When the control bits [C1, C2] = [0, 0], the 15 bits (R15 to R1) of the serially input 21 bits are set as the reference
counter frequency division value R. The value input as the frequency division value must satisfy the condition
3 ≤ R ≤ 32767.
In addition, (S, I, E) of the upper 4 bits are set simultaneously with the R value as the pull-in mode. The serial
input format is as follows.
LSB
MSB
C1 C2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 S
∗
I
E
Reference counter frequency division value
Pull-in mode selection
Control bits = [0, 0]
Pull-in mode end judgment
∗ Always set to "0".
15-bit reference counter frequency division value R (3 ≤ R ≤ 32767)
R
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–9–
CXA3314ER
1-2. Swallow counter and main counter (N counter) frequency division value setting
The N counter is comprised of a 5-bit swallow counter and a 13-bit main counter. When the control bits [C1, C2] =
[1, 0], the 18 bits (N18 to N1) of the serially input 21 bits are set as the N counter frequency division value N =
32 × M + S. The values input as the frequency division values must satisfy the conditions 0 ≤ S ≤ 31 and S ≤ M
≤ 8191. Adding the condition that the N value be a continuous value, the optional setting range is 992 ≤ N ≤
262143.
Note that in the CXA3314ER, the input to the N counter is the fixed 1/4 frequency division of the VCO output.
Therefore, care must be taken as VCO frequency/comparison frequency (VCK) = 4 × N.
In addition, the uppermost bit (F) is set simultaneously with the N value as the pull-in start/end bit. The serial
input format is as follows.
LSB
MSB
C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 F
Swallow/main counter frequency division value
Pull-in mode start/end
Control bits = [1, 0]
5-bit swallow counter frequency division value S (0 ≤ S ≤ 31, S ≤ M)
S
N5
N4
N3
N2
N1
0
0
0
0
0
0
1
0
0
0
0
1
:
:
:
:
:
:
31
1
1
1
1
1
13-bit main counter frequency division value M (3 ≤ M ≤ 8191)
M
N18
N17
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
3
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
8191
1
1
1
1
1
1
1
1
1
1
1
1
1
– 10 –
CXA3314ER
1-3. Pull-in mode setting
The uppermost bit (F) set simultaneously with the N value and (S, I, E) of the upper 4 bits set simultaneously
with the R value are used for various settings in pull-in mode.
LSB
N counter setting
MSB
C1 C2
F
Pull-in mode setting (F)
Control bits = [1, 0]
LSB
R counter setting
MSB
C1 C2
S
∗
I
Control bits = [0, 0]
E
Pull-in mode setting (E, I, S)
∗ Always set to "0".
The meaning of each bit is as follows.
F:
Pull-in mode start/end flag
Pull-in mode is activated and the lock detector is cleared when the F flag is set to "1".
Pull-in mode ends when the F flag is set to "0".
E: Pull-in mode end judgment flag
Pull-in mode automatically ends when the E flag is "1" and lock is detected.
When the E flag is "0", pull-in mode continues until the F flag is set to "0".
IS: Pull-in mode flags
These flags select the high-speed pull-in method used in pull-in mode.
The various methods are active at the following timings.
Loop filter saturation reset
When the S flag is "1".
CP current doubled
When the I flag is "1".
Damping resistance value halved
When either of the S or I flags is "1".
1-4. Initialization
When the control bits [C1, C2] = [1, 1], the counter frequency division value and pull-in mode setting bits are
initialized and set to R = 40, N = 5795, F = 1, SI = 11, and E = 1. The serial input format is as follows.
LSB
MSB
C1 C2
Control bits = [1, 1]
– 11 –
CXA3314ER
1-5. Test mode
When the control bits [C1, C2] = [0, 1], the test command is set. The serial input format is as follows. Test mode
operation is described in detail in the following section.
LSB
MSB
C1 C2
T0 T1 T2 T3
Test mode selection
Control bits = [0, 1]
2. Test mode setting
Switching between normal operation mode and test mode is controlled by the TESTDIS pin. Normal operation
mode results when TESTDIS is “1”, and test mode when “0”.
In test mode, the mode settings can also be controlled by 3-wire interface input. The input format is the same
as that described above. Note that the settings are valid only while TESTDIS is “0”. When TESTDIS is “1”, T0,
T1, T2 and T3 are all initialized to “0”.
The test mode operations set by the setting bits are shown in the table below.
T0
T1
T2
T3
x
x
x
0
Frequency division error detection flag function off
x
x
x
1
Frequency division error detection flag function on; output to LKDET pin
0
0
x
0
RCK signal output to LKDET pin
1
0
x
0
VCK signal output to LKDET pin
0
1
x
0
MOD signal output to LKDET pin
1
1
x
0
Pull-in ON/OFF signal output to LKDET pin
x: don’t care
3. Standby mode setting
Standby operation is controlled by the CEX pin. Normal operation mode results when CEX is “0”, and standby
mode when “1”.
In standby mode, the R counter, N counter, PFD and lock detector are all cleared, and the CP output is
maintained at high impedance. In addition, the counter frequency division value setting and pull-in mode
setting are saved.
– 12 –
CXA3314ER
Loop Filter Constant Settings
The loop filter constant calculation method is shown below.
Parameter definitions
N:
Counter frequency division value∗1
KVCO: VCO sensitivity (rad/s/V) ∗2
ωn:
Natural angular frequency (rad/s)
fn:
Natural frequency (Hz)
KPD: Charge pump gain (A/rad) ∗3
ξ:
Damping factor∗4
LUT: Lock-up time (s)
KPD × KVCO
= 2πfn
N×C
5π
ωn
1
(∴LUT =
)
fn =
=
ωn
2π
LUT
2.5
ωn =
R=
2×ξ
ωn × C
∗1 Frequency division value N = (VCO oscillation frequency) ÷ (Comparison frequency)
∗2 The KVCO unit is normally expressed as MHz/V, but here it is multiplied by 2π to adjust the dimensions and
expressed as rad/s/V.
∗3 The charge pump is a current output type. Here, the current capacitance is divided by 2π to adjust the
dimensions and expressed as A/rad. Note that the charge pump current capacitance of this IC is
approximately 300µA in normal mode and approximately 600µA in CP current doubled mode (REXT =
1.8kΩ).
∗4 ξ = √0.5 ≈ 0.7 (typ.)
R1
R2
GND
17 DMPSW
C2
C1
19 CPOUT
Loop filter
• Set C1 and R1 to the C and R values obtained by the formula above.
• C2 is generally set to 1/10 the value of C1.
• Set R2 so that the composite resistance of R1//R2 is the R value obtained by the formula above when
the charge pump current value is doubled. (See ∗3.)
– 13 –
CXA3314ER
Example of Representative Characteristics
REFIN input sensitivity characteristics
5
VCC = 3.0V, Ta = 26˚C
0
REF input level [dBm]
–5
–10
–15
–20
–25
–30
–35
0
20
40
60
100
80
120
140
REF input frequency [MHz]
RFIN input sensitivity characteristics
20
10
VCC = 3.0V, Ta = 26˚C
RF input level [dBm]
–0
–10
–20
–30
–40
–50
–60
0
1
2
3
4
5
6
7
8
9
10 11
4.5
5.0
RF input frequency [GHz]
Current consumption
16
VCC = 3.0V, Ta = 26˚C
Current consumption [mA]
14
12
10
8
6
4
2
2.5
3.0
3.5
4.0
Supply voltage [V]
– 14 –
CXA3314ER
• Example of 3-wire Serial Data Settings
N value
R value
0 000 000 000 000 000 011 00
R=3
0 000 111 111 111 111 100 00
R = 32764
0 000 000 001 111 100 000 01
N = 992
0 001 100 001 101 010 000 01
N = 50000
0 111 111 111 111 111 111 01
N = 262143
110 0 000 000 000 000 000 01
Reset
0 000 000 001 010 010 000 11
Initialize
0 000 000 000 001 100 100 00 0 000 000 000 011 111 010 01
R = 100, N = 250
0 000 000 000 001 100 100 00 0 000 000 100 111 000 100 01
R = 100, N = 2500
1 100 000 000 001 100 100 00
↓
R = 100, E = 1, I = 1, N = 2500
1 001 000 000 001 100 100 00
↓
R = 100, E = 1, S = 1, N = 2500
0 101 000 000 001 100 100 00 1 000 000 100 111 000 100 01
MSB
LSB MSB
LSB
– 15 –
R = 100, I, S = 1, N = 2500, F = 1
CXA3314ER
Unit: mm
24PIN VQFN(PLASTIC)
0.9 ± 0.1
4.0
0.6 ± 0.1
3.6
A
0.7
C
13
18
19
0.05
12
S
B
.3
78
(0
4.
9)
PIN 1 INDEX
24
˚
45
6
S
x4
5)
1.0
(0
0.1 S A-B C
.1
0.4
C
1
0.
6
7
x4
0.1 S A-B C
0.225 ± 0.03
0.2 ± 0.01
0.03 ± 0.03 (∗1)
(Stand Off)
0.05 M S A-B C
Solder Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.04g
VQFN-24P-03
SONY CODE
24PIN VQFN(PLASTIC)
0.9 ± 0.1
4.0
0.6 ± 0.1
3.6
A
19
0.05
0.7
C
13
18
12
S
B
.3
78
(0
4.
9)
PIN 1 INDEX
24
˚
45
S
1.0
(0
0.1 S A-B C
5)
x4
.1
6
0.4
C
1
0.
6
7
x4
0.2 ± 0.01
0.05 M S A-B C
0.225 ± 0.03
0.1 S A-B C
0.03 ± 0.03 (∗1)
(Stand Off)
Package Outline
Solder Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.04g
VQFN-24P-03
SONY CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 16 –
Sony Corporation