CXB1572Q Post amplifier for Optical Fiber Communication Receiver Description The CXB1572Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. 32 pin QFP (Plastic) Features • Auto-offset canceler circuit • Signal interruption alarm output • 2-level switching function of identification maximum voltage amplitude for alarm block • Single 3.3 V power supply Applications • FDDI • SONET/SDH • ESCON • Fiber channel • ATM : 125 Mb/s : 155.52 Mb/s : 200 Mb/s : 265.625 Mb/s : 155.52 Mb/s Absolute Maximum Ratings • Supply voltage VCC – VEE • • • • Tstg Vdif Vi IO Storage temperature Input voltage difference : I VD – VD I SW input voltage Output current (Continuous) (Surge current) Recommended Operating Conditions • Supply voltage VCC – VEE • Termination voltage (for data/alarm) VCC – VT1 • Termination voltage (for alarm 2) VT2 • Termination resistance (for data/alarm) RT1 • Termination resistance (for alarm 2) RT2 • Operating temperature Ta –0.3 to +7.0 –65 to +150 0 to +2.5 VEE to VCC 0 to 50 0 to 100 V °C V V mA mA 3.0 to 3.6 1.8 to 2.2 VEE 46 to 56 460 to 560 –40 to +85 V V V Ω Ω °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96638-TE CXB1572Q NC 25 NC 26 VCCDA SD SD VCCDA Q Q NC 21 20 19 18 17 Alarm Block 28 29 30 Limiting Amplifier Block 15 VCCD 14 VEED 13 VCCA 12 VEEA 11 CAP1 R2 R1 10 R3K R1 9 R2K 32 Rp —2— 4 5 6 7 8 D VCCA CAP1 3 D 2 SW 1 VEEI R3 VCCA VCCA NC R4 31 VCCP UP 16 27 R2 DOWN 22 peak hold CAP2 23 peak hold CAP3 24 ∆V NC VCCD Block Diagram and Pin Configuration CXB1572Q Pin Description Pin No. Symbol 1 2 Typical pin voltage (V) DC AC Equivalent circuit Description VCCP VCCA 32 0V 5 1 Positive power supply for external power supply. 2 VccA Generates the default voltage between UP and DOWN. The voltage (5.3 mV for input conversion) can be generated between UP and DOWN (Pins 30 and 31) as alarm setting level 1 by this pin to Open. The voltage (12 mV for input conversion) can be generated as alarm setting level 2 by connecting this pin to VEEA. 986 123.4 123.4 31 3 VEEI –3.3 V 30 Vcs SW VEEA 3 VCCA 60k 4 SW 40k 0V (OPEN) or –3.3 V VREF 4 Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 50 mVp-p. Low voltage when connecting this pin to VEE; the amplitude becomes 20 mVp-p. VEEA 5 D 6 D 7 VCCA –0.9 V to –1.7 V –0.9 V –1.3 V to –1.7 V –1.3 V Limiting amplifier block input. Be sure to make this input with AC coupled. VCCA 0V 100 11 5 8 CAP1 –1.8 V 6 10k 100p 200 3k 10 100 1.5k 10k 200 2k 9 8 9 R2K 10 R3K 11 CAP1 1.5k VEEA –1.8 V —3— Positive power supply for analog block. Pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 2 kΩ is connected between Pins 8 and 9; 3 kΩ between Pins 10 and 11. A resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and DC feedback gain can be varied due to compensate the input duty cycle distortion. CXB1572Q Pin No. Symbol Typical pin voltage (V) DC AC 12 VEEA –3.3 V 13 VCCA 0V 14 VEED –3.3 V 15 VCCD 0V Equivalent circuit Description Negative power supply for analog block. Positive power supply for analog block. Negative power supply for digital block. Positive power supply for digital block. 16 NC No connected. 17 18 VCCDA –0.9 V to –1.7 V Q 19 19 20 21 –0.9 V to –1.7 V Q VCCDA 18 VEED Positive power supply for output buffer. 0V VCCDA –0.9 V to –1.7 V SD 21 22 –0.9 V to –1.7 V SD 23 VCCDA 0V 24 VCCD 0V 25 26 27 NC Data signal output. Terminate this pin in 50 Ω at VTT = –2 V. Alarm signal output. Terminate this pin in 50 Ω at VTT = –2 V. 22 VEED Positive power supply for digital block. Positive power supply for digital block. No connected. —4— CXB1572Q Pin No. Symbol Typical pin voltage (V) DC AC Equivalent circuit 28 29 28 Description VCCA CAP3 –1.8 V 80 10p 10p 80 200 29 200 5µA CAP2 –1.8 V 5µA VEEA Connects a peak hold circuit capacitor for alarm block. 470 pF should be connected to VCCA each. CAP2 pin → Peak hold capacitor connection for alarm level setting block. CAP3 pin → Peak hold capacitor connection for limiting amplifier signal. VccA 30 –1090 mV (for DOWN VEEI = –3.3 V) 986 123.4 123.4 31 30 Vcs 31 32 UP VCCA –1020 mV (for VEEI = –3.3 V) SW Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor. (Please refer to pin description of pin No. 3.) VEEA 3 Positive power supply for analog block. 0V —5— CXB1572Q Electrical Characteristics • DC characteristics (VCC = GND, VEE = –3.0 V to –3.6 V, Ta = –40 to +85 °C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Symbol Power supply IEE Q/Q SD/SD High output voltage VOH Q/Q SD/SD Low output voltage VOL SD/SD High output voltage 2 VOHb SD/SD Low output voltage 2 VOLb SW High input voltage Conditions RT1 = 51 Ω, VT1 = VCC–2 V termination, Ta=0 to 85 °C Min. Typ. Max. Unit –56 –40 –29 mA –1025 –830 –1810 –1550 –1025 –700 –1860 –1500 VIH –500 0 SW Low input voltage VIL VEE VEE+500 SW High input current IIH SW Low input current IIL –60 D/D input resistance Rin 1109 1479 1849 Internal resistance 1 for alarm level setting Ra1 Refer to Fig. 3. 739 986 1233 Internal resistance 2 for alarm level setting Ra2A, B Refer to Fig. 3. 93 123 154 Resistance between VCCA and VCCP RP 3.3 5 6.9 Pare ratio of internal resistance 2 for alarm level setting δRa2 Resistance between CAP1 and R2K R3 1470 1970 2470 Resistance between CAP1 and R3K R4 2210 2960 3700 RT2 = 510 Ω, VT2 =VEE termination, Ta=0 to 85 °C 2 Ra2A/Ra2B —6— 0.97 mV µA Ω 1.03 Ω CXB1572Q • AC characteristics (VCC = GND, VEE = –3.0 V to –3.6 V, Ta = –40 to +85 °C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Symbol Maximum input voltage amplitude Vmax Amplifier gain (except for output buffer) GL Identification maximum voltage amplitude of alarm level VminA1 Conditions Single-ended input SW pin: Low, single-ended input Hysteresis width ∆P SD response assert time Tas SW pin: Open High, single-ended input Alarm level is default value Low → High∗1 SD response deassert time Tdas SD response assert time for alarm level default VminA2 Min. Typ. Max. 1600 mVpp 52 dB 20 mVpp 50 3 6 7 0 100 High → Low∗2 2.3 100 Tasd Low → High∗3 0 100 SD response deassert time for alarm level default Tdasd High → Low∗4 2.3 100 Alarm setting level 1 for default Vdef1 UP,DOWN,VEEI pins ;Open,connect SW pin to VEE 4.3 Alarm setting level 2 for default Vdef2 UP,DOWN,SW pins ;Open,connect VEEI to VEE 10.5 12.0 13.5 Propagation delay time TPD D to Q 1.2 1.7 2.6 Q/Q SD/SD rise time Tr 0.45 0.85 1.3 Q/Q SD/SD fall time ∗1 ∗2 ∗3 ∗4 Tf RT1 = 50 Ω, VT1 = VCC–2 V termination, VEE=–3.3 V, Ta=0 to 85 °C 20 % to 80 % VUP – VDOWN = 100 mV, Vin = 100 mVpp (single ended), SW pin: High Peak hold capacitance of 470 pF; connect VEEI to VEE. VUP – VDOWN = 100 mV, Vin = 1 Vpp (single ended), SW pin: High Peak hold capacitance of 470 pF; connect VEEI to VEE. Vin = 50 mVpp (single ended), SW pin: Low Peak hold capacitance of 470 pF; connect VEEI to VEE. Vin = 1 Vpp (single ended), SW pin: Low Peak hold capacitance of 470 pF; connect VEEI to VEE. —7— Unit 5.3 dB µs 6.3 mV ns 0.45 0.85 1.3 CXB1572Q DC Electrical Characteristics Measurement Circuit V 24 23 VT1 –2V 51 51 V 21 22 V 19 20 V 51 51 17 18 25 16 26 15 27 Alarm Block C3 14 Limiting Amplifier Block 28 R2 ∆V 30 12 R2 29 13 peak hold peak hold C3 11 V 31 R1 V R4 C2 10 32 V 9 R1 V V R3 RP 1 2 5 4 3 6 7 8 V V A C1 VS V C1 A VD VEE —8— –5V CXB1572Q AC Electrical Characteristics Measurement Circuit Oscilloscope 50Ωinput Z0=50 Z0=50 Z0=50 Z0=50 24 23 21 22 20 19 17 18 25 16 26 15 27 Alarm Block 14 Limiting Amplifier Block 28 V ∆V 30 REX1 12 R2 29 13 peak hold peak hold 470pF R2 470pF 11 31 R1 R4 10 32 0.22µF 9 REX2 R1 R3 RP 1 2 3 5 4 0.022µF 6 7 8 0.022µF VEE +3V —9— VCC +2V CXB1572Q Application Circuit VT1 51 24 23 –2V 51 22 51 21 20 51 19 18 17 25 16 26 15 27 Alarm Block 14 28 Limiting Amplifier Block R2 ∆V 30 12 R2 29 13 peak hold peak hold C3 330pF 11 31 R1 R4 10 32 9 R1 C2 0.22µF R3 RP 1 2 3 4 5 C1 0.022µF 6 7 C1 0.022µF 8 VEE –5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —10— CXB1572Q Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5 kΩ R2 (internal): 10 kΩ f2: 4.8 kHz f1: 72 Hz C1 (external): 0.022 µF C2 (external): 0.22 µF 2 kΩ is incorporated between Pins 8 and 9; 3 kΩ between Pins 10 and 11. A resistance value which is to be inserted in parallel with a capacitor C2 can be selected 5 ways (∞, 5 kΩ, 3 kΩ, 2 kΩ, 2 k//3 kΩ) by external wiring, and DC feedback can be varied. D 5 C1 To IC interior 6 C1 R1 R1 8 R3 R2 R4 R2 9 C2 10 11 Fig. 1 Gain Feedback frequency response f1 f2 Frequency Fig. 2 —11— Amplifier frequency response CXB1572Q 2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 30 and 31 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to leave Pins 30 and 31 open to set an alarm level default value (5.3 mV or 12 mV for input conversion). Default value of alarm level is 5.3 mV for input conversion by leaving Pin3 to open,12 mV by connecting Pin3 to VEE. The other is to connect Pin 3 to VEE and set a desired alarm level using the external resistors REX1 and REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 30 and 31, or connect REX3 between Pin 30 and VCC when less alarm level is desired to be set than its default value; connect REX2 between Pin 31 and VCC potential when more alarm level is desired to be set than its default value. However, the Pin 31 voltage must be higher than that of Pin 30. Refer to Figs. 7 to 9 for this alarm level setting. This IC also features two-level setting of identification maximum voltage amplitude for the alarm function. The amplitude is set to 50 mVp-p when Pin 4 is left open (High level) and it is set to 20 mVp-p when Pin 4 is Low level. Therefore, noise margin can be increased by setting Pin 4 to Low level when small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6 dB) as shown in Fig. 4. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. The typical values of REX1, REX2, REX3 and C3 are as follows: (Approximately 10 pF capacitor is built in Pins 28 and 29 each.) REX1 : 400 Ω (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE) REX2 : 4k Ω (when the alarm level is set to 15 mV for input conversion.connect Pin3 to VEE, Pin4; open) REX3 : 6.2 kΩ (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE) C3 : 470 pF The table below shows the alarm logic. Optical signal input state SD SD Signal input High level Low level Signal interruption Low level High level Ra1, Ra2A and Ra2B values are typical values From Limiting Amplifier Peak hold VCCA Ra1 Ra2A 123.4 SD SD 986 Ra2B 123.4 Peak hold Vcs VccA ∆V 4 3 31 VccA 10p 30 10p 28 29 VEEA Internal IC 31 30 C3 C3 3 REX2 External IC Vcc Fig. 3 —12— REX1 REX3 Vcc Vcc Vcc CXB1572Q VDAS → Deassert level VAS → Assert level Peak hold output voltage Low level VAS VDAS Small Large 3dB 3dB Alarm setting input level SW→Low SW→Open High 0 20mVpp 50mVpp Input voltage (Vp-p) Hysteresis Input electrical signal amplitude Fig. 4 Fig. 5 Hysteresis width Data input (D) Alarm setting level Data output (Q) Alarm output (SD) Assert time Deassert time Fig. 6 AAAAAAAAAAA A A A A A A A A AAAAAAAAAAA A A A A A A A A AAAAAAAAAAA AAAA AAAA AAAAAAAAAAA A A A A A A A A AAAAAAAAAAA A A A A A A A A AAAAAAAAAAA AAAA AAAA AAAAAAAAAAA A A A A A A A A AAAAAAAAAAA AAAA AAAA 5.0 4.5 Alarm setting level (mV) SD output High level 4.0 3.5 3.0 2.5 2.0 VEEI=open SW=VEE Ta=27˚C 1.5 1.0 102 103 REX1 (Ω) Fig. 7 —13— 104 CXB1572Q 30 25 20 15 AAAAAAAAAAA A AAAAAAAAAAAA A A A A A A A A A A AA AAAAAAAAAAAA A A A A A A A A A A AA AAAAAAAAAAAA A A A A A A A A A A AA AAAAAAAAAAAA A A A A A A A A A A AA AAAAAAAAAAA A AAAAAAAAAAAA A A A A A A A A A A AA A A A A A A A A A A AA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA A 10 101 VEEI=VEE SW=open Ta=27˚C 102 103 REX2 (Ω) 104 5.0 4.5 Alarm setting level (mV) Alarm setting level (mV) 35 105 Fig. 8 4.0 3.5 3.0 2.5 2.0 1.5 AAAAAAAAAAAA AAAAAA AAA A A A A A A AAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA A A A AA A A A A A A AAAAAAAAAAAA A A A AA A A A A A A AAAAAAAAAAAA AAAAAA AAA A A A A A A AAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA A A A AA A A A A A A AAAAAAAAAAAA A A A AA A A A A A A AAAAAAAAAAAA AAAA AAA AAAA 1.0 103 VEEI=open SW=VEE Ta=27˚C 104 REX3 (Ω) Fig. 9 3. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. —14— 105 CXB1572Q Example of Representative Characteristics AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A AAAAAAAAAAA A A A A A A A A A A A A Bit error rate vs. Input amplitude level 10-3 Bit error rate 10-4 10-5 10-6 10-7 VEE=–3.3V Ta=27°C D=155.52Mb/s Vin=3mVp-p, Single Input pattern : PRBS223–1 10-8 10-9 0.2 0.4 0.6 0.8 1 Data input level (mVp-p) 1.2 Fig. 10 Output RMS Jitter vs. Data input level Output RMS Jitter (ps) 70 60 VEE=3.3V Ta=27°C D=155.52Mbps Vin=3mVp-p, Single Input pattern : PRBS223–1 50 40 30 20 10 0 1 10 100 1000 Data input level (mVp-p) Fig. 11 Q Output waveform VEE=3.3V Ta=27°C D=155.52Mbps Vin=3mVp-p, Single Input pattern : PRBS223–1 16.4400ns 26.4400ns Ch. 1 = 200.0 mVolts/div Timebase = 2.00 ns/div 36.4400ns Offset Delay = 680.0 mVolts = 26.4400 ns —15— CXB1572Q Package Outline Unit : mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE —16— 0.50 8