CY2287 100-MHz Spread Spectrum Clock Synthesizer/Driver with USB, Hublink, and SDRAM Support Features Benefits • Mixed 2.5V and 3.3V Operation Usable with Pentium II, K6, and 6x86 Processors • Multiple output clocks at different frequencies — Three CPU clocks at 2.5V, up to 100 MHz — Nine 3.3V SDRAM clocks at 100 MHz — Eight synchronous PCI clocks at 33 MHz — Two synchronous APIC clocks at 16.67 MHz or 33 MHz — Two 3V66 clocks at 66 MHz — Two USB clocks at 48 MHz — One reference clock at 14.318 MHz Single-chip main motherboard clock generator — High-Speed Processor Support — Supports Two 4-Clock SDRAM DIMMs — Support for Six PCI Slots — Synchronous to the CPU Clock — Hublink Support — Universal Serial Bus Support — Also used as an input strap to determine APIC frequency • Spread Spectrum clocking — 31 kHz modulation frequency — EPROM programmable percentage of spreading — Default is –0.6%, which is recommended by Intel® — Additional options of –0.25% and –0.4% available Enables reduction of EMI • Power-down features Supports mobile systems • I2C™ Interface Dynamic output control • Low skew and low jitter outputs Meets tight system timing requirements at high frequency • Test Mode Enables ATE and “bed of nails” testing • 56-pin SSOP package Widely available, standard package enables lower cost Logic Block Diagram SSOP Top View CPU [0–2] (66/100 MHz) XTALIN XTALOUT 14.318 MHz OSC. CPU PLL EPROM Configurable Logic PCI [0–7] (33MHz) SEL0 SEL1 SDRAM [0-8] (100 MHz) EPROM APIC [0–1] (16.67/33MHz) 3V66 [0–1] (66MHz) PWR_DWN SYS PLL SCLK SDATA USB [0–1] (48MHz) SERIAL INTERFACE CONTROL LOGIC REF0/SEL33 VDDREF 1 56 VSSAPIC 2 55 APIC0 XTAL_IN 3 54 APIC1 XTAL_OUT 4 53 VDDAPIC VSSREF 5 52 CPU0 VSS3V66 6 51 VDDCPU 3V66_0 7 50 CPU1 3V66_1 8 49 CPU2 VDD3V66 VDDPCI 9 48 10 47 VSSCPU VSSSDRAM PCI0 11 46 SDRAM0 PCI1 45 SDRAM1 PCI2 12 13 44 VDDSDRAM VSSPCI 14 PCI3 15 CY2287 REF0/SEL33 (14.318 MHz) 43 SDRAM2 42 SDRAM3 PCI4 16 41 VSSPCI PCI5 17 40 VSSSDRAM SDRAM4 18 39 SDRAM5 PCI6 PCI7 19 38 20 37 VDDSDRAM SDRAM6 VDDPCI 21 36 SDRAM7 AVDD AVSS 22 35 23 34 VSSSDRAM SDRAM8 VSSUSB 24 25 33 VDDSDRAM 32 PWRDWN USB0 USB1 26 31 SCLK VDDUSB 27 30 SEL0 28 29 SDATA SEL1 Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 23, 1999 CY2287 Pin Summary Name Pins Description REF/SEL33 1 3.3V 14.31818-MHz clock output and power-on external select strap option for APIC clock frequency. Strap LOW: APIC = PCI/2 Strap HIGH: APIC = 33.3 MHz XTAL_IN[1] 3 14.31818-MHz crystal input XTAL_OUT[1] 4 14.31818-MHz crystal output PCI [0–7] 11, 12, 13, 15, 16, 18, 19, 20 3.3V PCI clock outputs 3V66 [0–1] 7, 8 3.3V Fixed 66.67-MHz clock outputs USB [0–1] 25, 26 3.3V Fixed 48-MHz clock outputs SEL [0–1] 28, 29 3.3V LVTTL compatible inputs for logic selection PWRDWN 32 3.3V LVTTL compatible input. Device enters powerdown mode when held LOW CPU [0–2] 49, 50, 52 2.5V 66.67-MHz or 100-MHz (selectable) host bus clock output SDRAM [0–8] 35, 36, 37, 39, 40, 42, 43, 45, 46 3.3V SDRAM clock outputs running 100 MHz APIC [0–1] 54, 55 2.5V APIC clock outputs running synchronous with PCI clock frequency. Selectable 16.67 MHz or 33.3 MHz SDATA 30 I2C compatible SDATA input SCLK 31 I2C compatible SCLK input VDDREF 2 3.3V Power supply for REF output VSSREF 5 REF ground VSS3V66 6 3V66 Ground VDD3V66 9 3.3V Power supply for 3V66 outputs VDDPCI 10, 21 3.3V Power supply for PCI outputs VSSPCI 14, 17 PCI ground AVDD 22 3.3V Analog power supply AVSS 23 Analog ground VSSUSB 24 USB ground VDDUSB 27 3.3V Power supply for USB outputs VDDSDRAM 33, 38, 44 3.3V Power supply for SDRAM outputs VSSSDRAM 35, 41, 47 SDRAM ground VSSCPU 48 CPU ground VDDCPU 51 2.5V Power supply for CPU outputs VDDAPIC 53 2.5V Power supply for APIC outputs VSSAPIC 56 APIC ground Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator Topics.” 2 CY2287 Function Table SEL2 [2] 0 SEL1 SEL0 0 0 CPU (MHz) SDRAM (MHz) Hi-Z [3] 3V66 (MHz) PCI (MHz) USB (MHz) REF (MHz) APIC[4] (MHz) APIC [5] (MHz) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 TCLK /2 TCLK/2 TCLK/3 TCLK/8 TCLK/2 TCLK TCLK/16 TCLK/8 0 1 0 66.67 100 66.67 33.33 48 14.318 16.67 33.33 0 1 1 100 100 66.67 33.33 48 14.318 16.67 33.33 1 0 0 66.67 100 66.67 33.33 48 14.318 16.67 33.33 1 0 1 100 100 66.67 33.33 48 14.318 16.67 33.33 1 1 0 66.67 100 66.67 33.33 48 14.318 16.67 33.33 1 1 1 100 100 66.67 33.33 48 14.318 16.67 33.33 Spread Spectrum[2] SEL2[2] SEL1 SEL0 Spread Spectrum Margin X 0 0 0 N/A X 0 0 1 N/A 0 X X X N/A 1 0 1 0 –0.6% 1 0 1 1 –0.6% 1 1 0 0 –0.25% 1 1 0 1 –0.25% 1 1 1 0 –0.4% 1 1 1 1 –0.4% Actual Clock Frequency Values Target Frequency (MHz) Actual Frequency (MHz) PPM CPUCLK 66.67 66.288 –5230 CPUCLK 100.0 99.432 –5680 USBCLK 48.0 48.008 +167 Clock Output Notes: 2. 3. 4. 5. Not a dedicated input pin. This selection must be addressed via I 2C interface. TCLK supplied on the XTALIN pin in Test Mode. SEL33 = LOW (power-on latch input). SEL33 = HIGH (power-on latch input). 3 CY2287 Serial Configuration Map Byte 2: PCI Control Register (1 = Enable, 0 = Disable) Default = Enable (for Bit [1:7]) Default = Disable (for Bit 0) • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Bit Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Description . Bit 7 20 PCI7 . Bit 6 19 PCI6 Bit 5 18 PCI5 Bit 4 16 PCI4 Bit 3 15 PCI3 Bit 2 13 PCI2 Bit 1 12 PCI1 Bit 0 11 Reserved Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits must be programmed to “0”. • I2C Address for the CY2287 is: A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 Byte 0: Spread Spectrum, USB, SDRAM8 Control Register (1 = Enable, 0 = Disable) Default = Enable (for Bit [0:2]) Default = Disable (for Bit [3:7]) Bit Pin # Pin # Byte 3: Peripheral Control Register (0 = Enable, 1 = Disable) Default = Enable Bit Description Pin # Description Bit 7 8 3V66_1 Bit 7 -- Reserved Bit 6 7 3V66_0 Bit 6 -- Reserved Bit 5 11 PCI0 Bit 5 -- Reserved Bit 4 34 SDRAM8 Bit4 -- SEL2 Bit 3 54 APIC1 Bit3 -- Spread Spectrum (Default = Disable) Bit 2 55 APIC0 Bit2 26 USB1 Bit 1 50 CPU1 Bit1 25 USB0 Bit 0 52 CPU0 Bit0 49 CPU2 Byte 4: Reserved Register (0 = Enable, 1 = Disable) Default = Disable Byte 1: SDRAM Control Register (1 = Enable, 0 = Disable) Default = Enable Bit Pin # Bit Description Bit 7 36 SDRAM7 Bit 6 37 SDRAM6 Bit 5 39 SDRAM5 Bit 4 40 SDRAM4 Bit 3 42 SDRAM3 Bit 2 43 SDRAM2 Bit 1 45 SDRAM1 Bit 0 46 SDRAM0 4 Pin # Description Bit 7 -- Reserved Bit 6 -- Reserved Bit 5 -- Reserved Bit 4 -- Reserved Bit 3 -- Reserved Bit 2 -- Reserved Bit 1 -- Reserved Bit 0 -- Reserved CY2287 Storage Temperature (Non-Condensing) ... –65°C to +150°C Maximum Ratings Max. Soldering Temperature (10 sec) ...................... +260°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ............................................... +150°C Supply Voltage ..................................................–0.5 to +7.0V Package Power Dissipation .............................................. 1W Input Voltage .............................................. –0.5V to VDD+0.5 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Over Which Electrical Parameters are Guaranteed Min. Max. Unit VDD3.3V Parameter 3.3V Supply Voltages Description 3.135 3.465 V VDD2.5V 2.5V Supply Voltages 2.375 2.625 V TA Operating Temperature, Ambient 0 70 °C CL Max. Capacitive Load on CPU, USB, REF, APIC SDRAM, PCI, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter VIH VIL Description High-level Input Voltage Low-level Input Voltage Test Conditions Min. Typ Max. Unit All inputs except SCLK/SDATA and crystal inputs[6] 2.0 V SCLK/SDATA 0.7 VDD [6] All inputs except SCLK/SDATA and crystal inputs 0.8 V SCLK/SDATA 0.3 VDD IIH Input High Current 0 < VIN < VDD –10 +10 µA IIL Input Low Current 0 < VIN < VDD –10 +10 µA IOH High-level Output Current CPU VOH = 2.0V –16 -60 mA USB, REF VOH = 2.4V –15 –51 SDRAM VOH = 2.4V –30 –100 PCI, 3V66 VOH = 2.4V –30 –100 APIC VOH = 2.0V –16 -60 CPU VOL = 0.4V 19 49 USB, REF VOL = 0.4V 10 24 SDRAM VOL = 0.4V 20 49 PCI, 3V66 VOL = 0.4V 20 49 APIC VOL = 0.4V 19 49 IOL Low-level Output Current mA IOZ Output Leakage Current Three-state 10 µA IDD2 2.5V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 100 MHz 100 mA IDD3 3.3V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 100 MHz 280 mA IDDPD2 IDDPD3 2.5V Shutdown Current 3.3V Shutdown Current [7] <1 500 µA [7] <9 500 µA AVDD/VDD33 = 3.465V, VDD25 = 2.625V AVDD/VDDQ3 = 3.465V, V DD25 = 2.625V Notes: 6. Crystal inputs have CMOS thresholds, nominally VDD/2. 7. Tested @ 500 µA. Actual performance is much better. Call Cypress if tighter spec is required. 5 CY2287 CY2287 Switching Characteristics[8] Over the Operating Range Parameter Output Description [9] Test Conditions Min. Max. Unit t1 All Output Duty Cycle t1A/(t1A + t1B) 45 55 % t2 CPU, APIC Rising Edge Rate Between 0.4V and 2.0V 1.0 4.0 V/ns t2 USB, REF Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t2 PCI, 3V66 Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t2 SDRAM Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU, APIC Falling Edge Rate Between 2.0V and 0.4V 1.0 4.0 V/ns t3 USB, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 V/ns t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t3 SDRAM Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t4 CPU CPU-CPU Skew Measured at 1.25V 175 ps t4 SDRAM SDRAM-SDRAM Skew Measured at 1.5V 250 ps t4 APIC APIC-APIC Skew Measured at 1.25V 250 ps t4 PCI PCI-PCI Skew Measured at 1.5V 500 ps t4 3V66 3V66-3V66 Skew Measured at 1.5V 175 ps 4.0 ns 500 ps 500 ps 8.0 ns 500 ps 3.0 ns t4 t4 3V66, PCI APIC, PCI 3V66-PCI Clock Skew APIC-PCI Clock Skew 3V66 leads [10] Coincident every edge 1.5 [10, 11] t5 SDRAM, 3V66 SDRAM-3V66 Clock Skew Coincident every other 3V66 edge t6_66 CPU, 3V66 CPU-3V66 Clock Skew CPU leads[10] t6_100 t7_66 CPU, 3V66 CPU, SDRAM CPU-3V66 Clock Skew CPU-SDRAM Clock Skew 7.0 Coincident every other 3V66 edge SDRAM leads [10] [10] [10, 12] 2.0 [10] t7_100 CPU, SDRAM CPU-SDRAM Clock Skew CPU leads, measured every edge 5.5 ns t8 CPU Cycle-Cycle Clock Jitter Measured at 1.25V, t8A – t8B 250 ps t8 SDRAM Cycle-Cycle Clock Jitter Measured at 1.5V, t8A – t8B 250 ps t8 APIC Cycle-Cycle Clock Jitter Measured at 1.25V, t8A – t8B 500 ps t8 USB Cycle-Cycle Clock Jitter Measured at 1.5V, t8A – t8B 500 ps t8 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V, t8A – t8B 500 ps t8 REF Cycle-Cycle Clock Jitter Measured at 1.5V, t8A – t8B 1000 ps tSTABLE All Outputs Settle Time All clock stabilization from power-up 3 ms Notes: 8. All parameters specified with loaded outputs as follows: CPU, APIC, REF, USB = 12.5 pF: SDRAM, 3V66, PCI=20 pF. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 10. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks. 11. Coincident every other APIC edge if APIC running at 16 MHz. 12. Measured every third CPU edge. 6 4.5 CY2287 Switching Waveforms Duty Cycle Timing t1A t1B All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 CLK-CLK Output Skew CLKA CLKB t4 Cycle-Cycle Clock Jitter t8A t8B CLK [13, 14, 15] PWR_DOWN CPUCLK Peripheral Clocks PWR_DWN VCO Crystal Notes: 13. Once the PWR_DWN signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 14. Waveforms are not to scale. 15. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. 7 CY2287 Switching Waveforms (continued) CLK-CLK Output Skew (CPU @ 66 MHz) 10 ns 0 ns 20 ns 30 ns 40 ns CPU 66 MHz SDRAM 100 MHz t5 3V66 66 MHz SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window) CLK-CLK Output Skew (CPU @ 66 MHz) 10 ns 0 ns 20 ns 30 ns 40 ns CPU 66 MHz t6_66 3V66 66 MHz SDRAM 100 MHz CPU to 3V66 Skew, CPU leads 3V66 by 7.5ns (500-ps window) CLK-CLK Output Skew (CPU @ 66 MHz) 10 ns 0 ns CPU 66 MHz 20 ns 30 ns t7_66 SDRAM 100 MHz 3V66 66 MHz CPU to SDRAM Skew, SDRAM leads CPU by 2.5 ns (500-ps window) 8 40 ns CY2287 Switching Waveforms (continued) CLK-CLK Output Skew (CPU @ 100 MHz) 0 ns 10 ns 20 ns 30 ns 40 ns CPU 100 MHz SDRAM 100 MHz t5 3V66 66 MHz SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window) CLK-CLK Output Skew (CPU @ 100 MHz) 0 ns 10 ns 20 ns 30 ns 40 ns t 6_100 CPU 100 MHz 3V66 66 MHz SDRAM 100 MHz CPU to 3V66 Skew, CPU leads 3V66 by 0.0 ns (500-ps window) CLK-CLK Output Skew (CPU @ 100 MHz) 0 ns 10 ns 20 ns 30 ns t7_100 CPU 100 MHz SDRAM 100 MHz 3V66 66 MHz CPU to SRAM Skew, CPU leads SDRAM by 5.0 ns (500-ps window) 9 40 ns CY2287 Switching Waveforms (continued) Window Measurement Clarification 500-ps window Earliest of Group A 1.5V Group A 1.5V Group B Latest of Group B Example of SDRAM to 3V66 Skew Measurement (CPU @ 66 or 100 MHz) SDRAM leads 3V66 by 0.0 ns (500-ps window) Window Measurement Clarification 8.0-ns window (max) 7.0-ns window (min) Latest of CPU Group Earliest of CPU Group 1.25V CPU Group Earliest of 3V66 Group 1.5V 3V66 Group Latest of 3V66 Group Example of CPU to 3V66 Skew Measurement (CPU @ 66 MHz) CPU leads 3V66 by 7.5 ns (500-ps window) 10 CY2287 Switching Waveforms (continued) SPREAD SPECTRUM CLOCKING Output Description Min. Max. Unit Modulation Frequency CPU, PCI, SDRAM, APIC, 3V66 30.0 33.0 kHz Down Spread Margin at the Fundamental Frequency CPU, PCI, SDRAM, APIC, 3V66 –0.25 –0.6 % Spread Spectrum Disabled Amplitude (dB) Spread Spectrum Enabled Selectable Downspread Margins –0.25% –0.4% –0.6% Frequency (MHz) 11 CY2287 Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Application Circuit XTALIN XTALOUT Cx Rs SEL0 SEL1 PWR_DWN SEL0 SEL1 PWR_DWN CPU SDRAM PCI HUBLINK APIC REF USB CPU SDRAM PCI 3V66 APIC REF USB 3.3V VDD VDD3.3V Cd Ct 2.5V VDD VDD2.5V Cd VSS CY2287-1 56 Pin SSOP Cd = Decoupling Capacitors (NOTE: May use 0.1µF, but value will vary with frequency of operation and output current) Ct = Optional EMI-Reducing Capacitors Cx = Optional Load Matching Capacitors Rs = Termination Resistor Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 2.2 nF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (CPU/APIC = 29 Ohm, USB/REF = 40 Ohm, SDRAM (3.3V)= 16 Ohm, PCI/3V66 = 30 Ohm - all nominal driver output impedances), and Rseries is the series terminating resistor. Rseries > R trace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 12 cy2287: May 26, 1998 Revision: June 23, 1999 CY2287 Test Circuit VDD3.3V 5, 6, 14, 17, 23, 24, 34, 41, 47, 48, 56 2, 9, 10, 21, 22, 27, 32, 38, 44 CY2287 VDD2.5V OUTPUTS CLOAD 51, 53 Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible. Ordering Information Ordering Code CY2287PVC–1 Package Name O56 Package Type 56-Pin SSOP Operating Range Commercial Document #: 38–00711–A Package Diagram 56-Lead Shrunk Small Outline Package O56 51-85062-B © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.