Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY54/74FCT646T 8-Bit Registered Transceiver SCCS031 - July 1994 - Revised March 2000 Features Functional Description • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.4 ns max. (Com’l) FCT-A speed at 6.3 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature permits live insertion • Matched rise and fall times • Fully compatible with TTL input and output logic levels • ESD > 2000V • Sink current 64 mA (Com’l), 48 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) • Independent register for A and B buses • Extended commercial range of −40˚C to +85˚C The FCT646T consists of a bus transceiver circuit with three-state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a HIGH logic level. Enable Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register, or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (enable Control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register. The outputs of the FCT646T are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations Function Block Diagrams QSOP, SOIC Top View A6 A5 A4 NC A3 DIR CPBA SBA CPAB SAB D A7 A8 GND NC B8 B7 B6 B1 A1 D 11 10 9 8 7 6 5 12 4 3 13 2 14 1 15 16 28 27 17 18 26 19 20 21 22 23 24 25 DIR SAB CPAB NC VCC CPBA SBA B5 B4 B3 NC B2 B1 G C A2 A1 LCC Top View G CPAB 1 24 VCC SAB 2 23 CPBA DIR 3 22 SBA A1 4 21 G A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 A8 11 14 B7 GND 12 13 B8 Logic Block Diagram C A1 CPAB SAB DIR A2 A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 CPBA SBA G B1 TO 7 OTHER CHANNELS Pin Description Name A B CPAB, CPBA SAB, SBA DIR, G Description Data Register A Inputs, Data Register B Outputs Data Register B Inputs, Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs Copyright © 2000, Texas Instruments Incorporated CY54/74FCT646T BUS A DIR L G L CPAB X CPBA X SAB X BUS B BUS A SBA L DIR H BUS B G L CPAB X Real-Time Transfer Bus B to Bus A G L L H CPAB CPBA X X SAB L SBA X Real-Time Transfer Bus A to Bus B BUS A DIR H L X CPBA X BUS B BUS A SBA X X X DIR [1] L H SAB X X X BUS A G L L CPAB X H or L Storage from A and/or B CPBA H or L X SAB X H SBA H X Transfer Stored Data to A and/or B Function Table[2] Data I/O[3] Inputs Operation or Function G DIR CPAB CPBA SAB SBA A1 thru A8 B1 thru B8 FCT646T H H X X H or L H or L X X X X Input Input Isolation Store A and B Data L L L L X X X H or L X X L H Output Input Real Time B Data to A Bus Stored B Data to A Bus L L H H X H or L X X L H X X Input Output Real Time A Data to B Bus Stored A Data to B Bus Notes: 1. Cannot transfer data to A bus and B bus simultaneously. 2. H = HIGH Voltage Level, L = LOW Voltage Level, = LOW-to-HIGH Transition, X = Don’t Care. 3. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. 2 CY54/74FCT646T Maximum Ratings[4, 5] Power Dissipation .......................................................... 0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied .............................................–65°C to +135°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V DC Output Voltage ......................................... –0.5V to +7.0V Range Range Ambient Temperature VCC Commercial All –40°C to +85°C 5V ± 5% Military[6] All –55°C to +125°C 5V ± 10% DC Output Current (Maximum Sink Current/Pin).......120 mA Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min. Typ.[7] Max. Unit VCC=Min., IOH=–32 mA Com’l 2.0 V VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V VCC=Min., IOH=–12 mA Mil 2.4 3.3 V VCC=Min., IOL=64 mA Com’l 0.3 0.55 V VCC=Min., IOL=48 mA Mil 0.3 0.55 V VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage VH Hysteresis[8] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 II Input HIGH Current 0.8 V V –1.2 V VCC=Max., VIN=VCC 5 µA Input HIGH Current[8] VCC=Max., VIN=2.7V ±1 µA IIL Input LOW Current[8] VCC=Max., VIN=0.5V IOS Output Short Circuit Current[9] VCC=Max., VOUT=0.0V IOFF Power-Off Disable VCC=0V, VOUT=4.5V IIH –60 –120 ±1 µA –225 mA ±1 µA Capacitance[8] Parameter Description Typ.[7] Max. Unit CIN Input Capacitance 6 10 pF COUT Output Capacitance 8 12 pF Notes: 4. Unless otherwise noted, these limits are over the operating free-air temperature range. 5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 6. TA is the “instant on” case temperature. 7. Typical values are at VCC=5.0V, TA=+25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY54/74FCT646T Power Supply Characteristics Parameter ICC Description Test Conditions Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V Typ.[7] Max. Unit 0.1 0.2 mA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max., VIN=3.4V, f1=0, Outputs Open 0.5 2.0 mA ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, G=DIR=GND, GAB=GBA=GND, VIN≤0.2V or VIN≥VCC–0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[12] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, G=DIR=GND, GAB=GBA=GND, VIN≤0.2V or VIN≥VCC–0.2V 0.7 1.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, G=DIR=GND, GAB=GBA=GND, VIN=3.4V or VIN=GND 1.2 3.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, G=DIR=GND, GAB=GBA=GND, VIN≤0.2V or VIN≥VCC–0.2V 2.8 5.6[13] mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, G=DIR=GND, GAB=GBA=GND, VIN=3.4V or VIN=GND 5.1 14.6[13] mA [10] Notes: 10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 12. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY54/74FCT646T Switching Characteristics Over the Operating Range[14] FCT646T Military Parameter Description FCT646AT Commercial Commercial Min. Max. Min. Max. Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Bus to Bus 2.0 11.0 1.5 9.0 1.5 6.3 ns 1, 3 tPZH tPZL Output Enable Time Enable to Bus and DIR to An or Bn 2.0 15.0 1.5 14.0 1.5 9.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time G to Bus and DIR to Bus 2.0 11.0 1.5 9.0 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 2.0 10.0 1.5 9.0 1.5 6.3 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to A or B 2.0 12.0 1.5 11.0 1.5 7.7 ns 1, 5 tS Set-Up Time HIGH or LOW, Bus to Clock 4.5 4.0 2.0 ns 4 tH Hold Time HIGH or LOW, Bus to Clock 2.0 2.0 1.5 ns 4 tW Pulse Width, HIGH or LOW [8] 6.0 6.0 5.0 ns 5 FCT646CT Military Parameter Description Commercial Min. Max. Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Bus to Bus 1.5 6.0 1.5 5.4 ns 1, 3 tPZH tPZL Output Enable Time Enable to Bus and DIR to An or Bn 1.5 8.9 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time G to Bus and DIR toBus 1.5 7.7 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 6.3 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to A or B 1.5 7.0 1.5 6.2 ns 1, 5 tS Set-Up Time, HIGH or LOW, Bus to Clock 2.0 2.0 ns 4 tH Hold Time, HIGH or LOW, Bus to Clock 1.5 1.5 ns 4 5.0 5.0 ns 5 tW Pulse Width,[8] HIGH or LOW Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. See “Parameter Measurement Information” in the General Information Section. 5 CY54/74FCT646T Ordering Information Speed (ns) 5.4 Ordering Code Package Name Package Type CY74FCT646CTQCT Q13 24-Lead (150-Mil) QSOP Operating Range Commercial CY74FCT646CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC 6.0 CY54FCT646CTLMB L64 28-Square Leadless Chip Carrier Military 6.3 CY74FCT646ATQCT Q13 24-Lead (150-Mil) QSOP Commercial CY74FCT646ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT646TQCT Q13 24-Lead (150-Mil) QSOP CY74FCT646TSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY54FCT646TLMB L64 28-Square Leadless Chip Carrier 9.0 11.0 Document #: 38–00267–C Package Diagrams 28-Square Leadless Chip Carrier L64 MIL–STD–1835 C–4 6 Commercial Military CY54/74FCT646T Package Diagrams (continued) 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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