DAC ® DAC4813 481 3 QUAD 12-BIT DIGITAL-TO-ANALOG CONVERTER (12-bit port interface) FEATURES DESCRIPTION ● COMPLETE WITH REFERENCE AND OUTPUT AMPLIFIERS DAC4813 is a complete quad 12-bit digital-to-analog converter with bus interface logic. Each package includes a precision +10V voltage reference, doublebuffered bus interface including a RESET function and 12-bit D/A converters with voltage-output operational amplifiers. ● 12-BIT PORT INTERFACE ● ANALOG OUTPUT RANGE: ±10V ● MONOTONICITY GUARANTEED OVER TEMPERATURE ● INTEGRAL LINEARITY ERROR: ±1/2LSB max ● ±12V to ±15V SUPPLIES ● 28-PIN PLASTIC DIP PACKAGE The double-buffered interface consists of a 12-bit input latch and a D/A latch for each D/A converter. A RESET control allows the D/A outputs to be asynchronously reset to bipolar zero, a feature useful for power-up reset, system initialization and recalibration. DAC4813 D/A converters are committed to the ±10V output range only. Gain and offset are not externally adjustable. DAC4813 10V Reference D/A 1 D/A 2 DB0 LSB 12 DB11 MSB VREF OUT VOUT 1 DAC4813 is available with a integral linearity error of 1/2LSB and 12-bit monotonicity guaranteed over temperature. It is packaged in a 28-pin 0.6in. wide plastic DIP package and specified over –40oC to +85oC and 0°C to +70°C. VOUT 2 12-bit Latches D/A 3 D/A 4 VOUT 3 VOUT 4 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1992 Burr-Brown Corporation PDS-1148C 1 Printed in U.S.A. May, 1997 DAC4813 SPECIFICATIONS ELECTRICAL TA = +25oC, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. DAC4813AP, JP PARAMETER CONDITIONS INPUTS DIGITAL INPUTS MIN TYP MAX UNITS +5.5 +0.8 V V ±40 ±40 µA µA ±1/4 ±1/2 ±0.05 ±0.05 ±1/2 ±1 ±0.2 ±0.2 LSB LSB % %FSR(4) ±5 ±1 ±20 ±10 ppmFSR/%+VCC ppmFSR/%–VCC ±5 ±5 ±1/2 Guaranteed ±30 ±15 ±3/4 ppm/°C ppmFSR/°C LSB 4.5 6 µs µs V/µs LSB ±10 V mA Ω +10.05 V 0.2 ±5 Indefinite ±25 mA Ω ppm/°C +15 –15 +16.5 –16.5 V V 48 24 1080 60 28 1320 mA mA mW –3 +3 V –40 0 –60 +85 +70 +100 30 °C °C °C °C/W Over Temperature Input Code (1) Logic Levels (2) VIH (3) VIL Logic Input Currents DB0-DB11, WR, LDAC, RESET,ENX IIH IIL Range Bipolar Offset Binary +2 0 VI = +2.7V VI = +0.4V TRANSFER CHARACTERISTICS ACCURACY Linearity Error Differential Linearity Error Gain Error Bipolar Zero Error (5) Power Supply Sensitivity Of Full Scale +VCC –VCC DRIFT Over Specification Temperature Range Gain Bipolar Zero Drift Linearity Error over Temperature Monotonicity DYNAMIC CHARACTERISTICS SETTLING TIME (6) Full Scale Range Change 1LSB Output Step (7) At Major Carry Slew Rate Crosstalk (8) OUTPUT Output Voltage Range Output Current Output Impedance Short Circuit to ACOM Duration REFERENCE VOLTAGE Voltage Source Current Available for External Loads Impedance Temperature Coefficient Short Circuit to Common Duration POWER SUPPLY REQUIREMENTS Voltage: +VCC –VCC Current: To within ±0.012%FSR of Final Value 5kΩ || 500pF Load 20V Range 2 10 0.2 5kΩ Loads ±VCC ≥ ±11.4V ±5 0.2 Indefinite at DC +9.95 +10.00 2 at DC +11.4 –11.4 No Load ±VCC = ±15V +VCC –VCC Power Dissipation Potential at DCOM with Respect to ACOM (9) TEMPERATURE RANGES Specification: AP JP Storage Thermal Resistance, θJA,Plastic DIP NOTES: (1) For Two’s Complement Input Coding invert the MSB with an external logic inverter. (2) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) Error at input code 800HEX. (6) Maximum represents the 3σ limit. Not 100% tested for this parameter. (7) For the worst-case code change: 7FFHEX to 800HEX and 800HEX to 7FFHEX. (8) Crosstalk is defined as the change in any output as a result of any other output being driven from –10V to +10V at rated output current. (9) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications. ® DAC4813 2 TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS +VCC to ACOM ............................................................................ 0 to +18V –VCC to ACOM ............................................................................ 0 to –18V +VCC to –VCC ............................................................................... 0 to +36V ACOM to DCOM .................................................................................. ±4V Digital Inputs to DCOM ........................................................... –1V to +VCC External Voltage applied to BPO Resistor ......................................... ±18V VREF OUT .............................................................. Indefinite short to ACOM VOUT ............................................................................ Momentary to ±18V Lead Temperature, soldering 10s .................................................. +300oC Max Junction Temperature .............................................................. 165oC WRITE CYCLE #1 (Load first rank from Data Bus: LDAC = 1) > 50ns ENX > 50ns DB11–DB0 > 5ns NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. WR > 50ns PACKAGE/ORDERING INFORMATION WRITE CYCLE #2 (Load second rank from first rank: ENX = 1) PRODUCT > 50ns LDAC PACKAGE DAC4813AP 28-Pin Plastic DBL Wide DIP DAC4813JP 28-Pin Plastic DBL Wide DIP > 50ns PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE 215 215 –40°C to +85°C 0°C to +70°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. WR tSETTLING ELECTROSTATIC DISCHARGE SENSITIVITY ±1/2LSB V OUT Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. RESET COMMAND (Bipolar Mode) ENX, LDAC, WR = Don’t Care Reset > 50ns +10V tSETTLING VOUT 0V ±1/2LSB –10V TRUTH TABLE WR EN1 EN2 EN3 EN4 LDAC RESET X 1 X 0 0 0 0 0 0 X X 1 1 1 1 0 1 0 X X 1 1 1 0 1 1 0 X X 1 1 0 1 1 1 0 X X 1 0 1 1 1 1 0 X X 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 OPERATION Reset all D/A Latches No Operation No Operation Load Data into First Rank for D/A 4 Load Data into First Rank for D/A 3 Load Data into First Rank for D/A 2 Load Data into First Rank for D/A 1 Load Second Rank from First Rank, All D/As All Latches Transparent “X” = Don’t Care ® 3 DAC4813 PIN DESCRIPTIONS PIN NAME FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 WR EN1 EN2 EN3 EN4 LDAC DCOM –VCC ACOM +VCC VOUT 4 VOUT 3 VOUT 2 VOUT 1 VREF OUT DATA, MSB, positive true. DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA, LSB. Resets output of all D/As to bipolar-zero. The D/A remains in this state until overwritten by a LDAC-WR command. RESET does not reset the input latch. After power–up and reset, input latches will be in an indeterminant state. Write strobe. Must be low for data transfer to any latch (except RESET). Enable for 12-bit input data latch of D/A1. NOTE: This logic path is slower than the WR/ path. Enable for 12-bit input data latch of D/A2. NOTE: This logic path is slower than the WR/ path. Enable for 12-bit input data latch of D/A3. NOTE: This logic path is slower than the WR /path. Enable for 12-bit input data latch of D/A4. NOTE: This logic path is slower than the WR/ path. Load DAC enable. Must be low with WR for data transfer to the D/A latch and simultaneous update of all D/A converters. Digital common, logic currents return. Analog supply input, nominally –12V or –15V referred to ACOM. Analog common, +VCC, –VCC supply return. Analog supply input, nominally +12V or +15V referred to ACOM. D/A 4 analog output. D/A 3 analog output. D/A 2 analog output. D/A 1 analog output. +10V reference output. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC4813 4 BLOCK DIAGRAM MSB DB11 1 WR 14 EN1 15 LSB DB0 2 3 4 5 6 7 8 9 10 11 12 12 25kΩ 12-Bit Input Latch 25kΩ 12-Bit D/A Latch 0–800µA 12-Bit D/A Converter 50kΩ 27 VOUT 1 26 VOUT 2 25 VOUT 3 24 VOUT 4 12 25kΩ EN2 12-Bit Input Latch 16 25kΩ 12-Bit D/A Latch 0–800µA 12-Bit D/A Converter 50kΩ 12 25kΩ EN3 12-Bit Input Latch 17 25kΩ 12-Bit D/A Latch 0–800µA 12-Bit D/A Converter 50kΩ 12 25kΩ EN4 18 12-Bit Input Latch LDAC 19 12-Bit D/A Latch RESET 13 25kΩ 0–800µA 12-Bit D/A Converter 50kΩ +10V Reference 28 22 VREF OUT ACOM 20 23 21 DCOM +VCC –VCC NOTE: RESET does not reset input latches. ® 5 DAC4813 TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY DIGITAL INPUT CURRENT vs INPUT VOLTAGE 1k WR 12.0 9.6 +VCC 100 7.2 Input Current (µA) 10 –VCC RESET, LDAC 4.8 ENX 2.4 0 –2.4 –4.8 1 –7.2 DB0-DB11: DAC4813 –9.6 –12.0 0.1 10 100 1k 10k 100k 1M –2 0 2 CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE 0.8 0 Unipolar Offset Gain Error –0.5 –0.4 –1 Linearity Error (LSB) ∆ Gain Error (%) 0.4 0 0 –0.8 –20 20 60 Temperature (°C) 100 –0.5 000 140 400 800 C00 FFF Input Code (Hexidecimal) ± FULL SCALE OUTPUT SWING MAJOR CARRY GLITCH 15 250 VOUT 10 200 150 WR +5 0 0 100 VOUT (mV) 5 WR (V) VOUT (V) 8 0.5 ∆ Bipolar/Unipolar Offset (%) (For 10V FSR; Double for 20V FSR) Bipolar Offset –60 6 INTEGRAL LINEARITY ERROR 1 0.5 4 Input Voltage (V) Frequency (Hz) –5 50 0 Data = 7FFH Data = 800H WR (V) [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) TA = +25°C, V CC = ±15V unless otherwise noted. Data = 7FFH +10 0 –10 –15 0 5 10 15 Time (µs) 20 25 –2 2 4 6 Time (µs) ® DAC4813 0 6 8 10 12 14 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15V unless otherwise noted. SETTLING TIME, –10V TO +10V SETTLING TIME, +10V TO –10V 20 VOUT 20 1LSB = 4.88mV 1LSB = 4.88mV 0 WR –10 +5 0 –20 –2 0 2 4 6 8 10 0 VOUT –10 WR –20 –40 0 VOUT –2 12 +5 0 2 4 6 8 10 12 WR (V) VOUT VOUT Around +10V (mV) 10 WR (V) VOUT Around –10V (mV) 10 14 Time (µs) Time (µs) DISCUSSION OF SPECIFICATIONS SETTLING TIME Settling Time is the total time (including slew time) for the output to settle to within an error band around its final value after a change in input. Settling times are specified to ±0.01% of Full Scale Range (FSR) for two conditions: one for a FSR output change of 20V (25kΩ feedback) and one for a 1LSB change. The 1LSB change is measured at the Major Carry (7FFHEX to 800HEX, and 800HEX to 7FFHEX), the input code transition at which worst-case settling time occurs. LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points (digital inputs all “1s” and all “0s”). DAC4813 linearity error is ±1/2LSB max at +25oC. DIFFERENTIAL LINEARITY ERROR Differential Linearity Error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word If the DLE is more positive than –1LSB, the D/A is said to be monotonic. OPERATION INTERFACE LOGIC The bus interface logic of the DAC4813 consists of two independently addressable latches in two ranks for each D/A converter. The first rank consists of one 12-bit input latch which can be loaded directly from a 12- or 16-bit microprocessor/microcontroller bus. The input latch holds data temporarily before it is loaded into the second latch, the D/A latch. This double buffered organization permits simultaneous update of all D/As. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. DAC4813 is monotonic over their specification temperature range –40oC to +85oC. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/oC). All latches are level-triggered. Data present when the control signals are logic “0” will enter the latch. When the control signals return to logic “1”, the data is latched. CAUTION: DAC4813 was designed to use WR as the fast strobe. WR has a much faster logic path than ENX (or LDAC). Therefore, if one permanently wires WR to DCOM and uses only ENX to strobe data into the latches, the DATA HOLD time will be long, approximately 20ns to 30ns, and this time will vary considerably in this range from unit to unit. DATA HOLD time using WR is 5ns max. Bipolar Zero Drift is measured with a data input of 800HEX. The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/oC). ® 7 DAC4813 RESET FUNCTION The Reset function resets only the D/A latch. Therefore, after a RESET, good data must be written to all the input latches before an LDAC – WR command is issued. Otherwise, old data or unknown data is present in the input latches and will be transferred to the D/A latch producing an analog output value that may be unwanted. INTERNAL/EXTERNAL REFERENCE USE DAC4813 contains a +10V ±50mV voltage reference, VREF OUT. VREF OUT is available to drive external loads sourcing up to 2mA. The load current should be constant, otherwise the gain (and bipolar offset, if connected) of the D/A converters will vary. Because of the lack of additional pins required for external reference inputs, VREF OUT is connected internally to all 4 D/A converters. VREF OUT is available for external use on pin 28. LOGIC INPUT COMPATIBILITY DAC4813 digital inputs are TTL compatible (1.4V switching level) over the operating range of +VCC. Each input has low leakage and high input impedance. Thus the inputs are suitable for being driven by any type of 5V logic. An equivalent circuit of a digital input is shown in Figure 1. GAIN AND OFFSET ADJUSTMENTS DAC4813 has no Gain and Offset Adjustment option. Open DATA input lines will float to 7V or more. Although this will not harm the DAC4813, current spikes will occur in the input lines when a logic 0 is asserted and, in addition, the speed of the interface will be slower. A digital output driving a DATA input line of the DAC4813 must not drive, or let the DATA input float, above +5.5V. Unused DATA inputs should be connected to DCOM. INSTALLATION POWER SUPPLY CONNECTIONS Power supply decoupling capacitors should be added. Best settling time performance occurs using a 1 to 10µF tantalum capacitor at –VCC. Applications with less critical settling time may be ale to use 0.01µF at –VCC as well as at +VCC. The capacitors should be located close to the package. Unused control inputs should be connected to a voltage greater than +2V but not greater than +5.5V. If this voltage is not available, the control inputs can be connected to +VCC through a 100kΩ resistor to limit the input current. Digital Input DAC4813 features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. It is recommended that both DIGITAL COMMON (DCOM) and ANALOG COMMON (ACOM) be connected directly to a ground plane under the package. If a ground place is not used, connect the ACOM and DCOM pins together close to the package. Since the reference point for VOUT and VREF OUT is the ACOM pin, it is also important to connect the load directly to the ACOM pin. The change in current in the ACOM pin due to an input date word change from 000HEX to FFFHEX is only 1mA for each D/A converter. R 6.8V 10 to 20pF II DCOM DIGITAL INPUT Data, LDAC, WR, RESET ENX DAC4813 RΩ OUTPUT VOLTAGE SWING AND RANGE CONNECTIONS DAC4813 output amplifiers provide a ±10V output swing while operating on supplies as low as ±12V ±5%. 250 330 FIGURE 1. Equivalent Digital Input Circuit. DAC4813 is fully committed to ±10V output ranges. Optional ranges are not pin programmable. INPUT CODING DAC4813 accepts positive-true binary input codes. Input coding for bipolar analog outputs is Bipolar Offset Binary (BOB), where an input code of 000HEX gives a minus full-scale output, an input of FFFHEX gives an output 1LSB below positive full scale, and zero occurs for an input code of 800HEX. 12- AND 16-BIT BUS INTERFACES DAC4813 data is latched into the input latches of each D/A by asserting low each ENx individually and transferring the data from the bus to each input latch by asserting WR low. All D/A outputs in each package are then updated simultaneously by asserting LDAC and WR low. DAC4813 can be used with two's complement coding if a logic inverter is used ahead of the MSB input (DB11). Be sure to read the CAUTION statement in the LOGIC INPUT COMPATIBILITY section. ® DAC4813 8