DAC8544 www.ti.com SLAS420 – MAY 2004 QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE, DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • • • DESCRIPTION Single Supply: +2.7 V to +5.5 V Micropower Operation: 950 µA @ 5 V Rail-To-Rail Voltage Output Ultralow Crosstalk: –110 dB Settling Time: 10 µs To ±0.003% FSR 16-Bit Monotonic Offset Error: ±0.3 mV Gain Error: ±1 mV Total Error: ±3 mV Per-Channel VREF+, VREF–, VFB Pins Logic Compatible: +1.8 V to +5.5 V Readback Capability Double Buffered Inputs Simultaneous or Sequential Update Schmitt-Triggered Digital Inputs Hardware Reset 48-Lead TQFP Package The DAC8544 is a low-power, quad-channel, 16-bit, voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail voltage swing to be achieved at the output. The DAC8544 is 16-bit monotonic and offers exceptional absolute accuracy with ultralow crosstalk. The DAC8544 uses a 16-bit parallel interface and features additional power-down function pins as well as hardware-enabled, synchronous DAC updating and reset capability. The DAC8544 requires an external reference voltage to set the output range of the DAC. The device incorporates a power-on-reset circuit that ensures that the DAC outputs power up at zero volt and remains there until a valid write takes place. In addition, the DAC8544 contains a power-down feature, accessed via PD pin, that reduces the current consumption of the device to 400 nA at 5 V. The power consumption is typically under 5 mW at VDD = 5 V. The DAC8544 is available in a 48-lead TQFP package with an operating temperature range of –40°C to +105°C. APPLICATIONS • • • • • Process Control Data Acquisition Systems Closed-Loop Servo Control PC Peripherals Optical Networking VREFA+ VREFA− IOVDD IOGND VDD GND VREFB+ VREFB− Power-On Reset D15 Input Register D0 CS LDAC Interface Logic Input Register DAC8544 DAC Register DAC Register VFBA 16 Bit DAC Buffer 16 Bit DAC Buffer VOUTA VFBB VOUTB VFBC VOUTC VFBD VOUTD RST R/W Power-Down Logic A1 A0 VREFD− VREFD+ VREFC+ VREFC− PD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated DAC8544 www.ti.com SLAS420 – MAY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PRODUCT PACKAGE PACKAGE DRAWING NUMBER TA PACKAGE MARKING DAC8544 48 - TQFP PFB -40°C to 105°C DAC8544I ORDERING NUMBER TRANSPORT MEDIA DAC8544IPFB Tray DAC8544IPFBR Tape and Reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VDD to GND –0.3 V to 6 V IOVDD to IOGND –0.3 V to 6 V Digital input voltage to IOGND –0.3 V to IOVDD + 0.3 V VOUT to GND –0.3 V to VDD + 0.3 V Operating temperature range –40°C to 105°C Storage temperature range, Tstg –65°C to 150°C Junction temperature, TJ max +150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VDD = + 2.7 V to + 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted DAC8544 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 16 ±0.025 ±.098 ±0.25 ±1 Measured at code 485, 25°C 0.3 ±3 Measured at code 485, -40°C to 105°C 1.0 ±5.0 All zeroes loaded to DAC register -20 µV/°C 0.1 LSB -110 dB Relative Accuracy Differential Nonlinearity Zero-Code Offset Error Zero-Code Error Drift 16-Bit Monotonic DC Crosstalk AC Crosstalk Gain Error 1-kHz sine wave Measured at code 64714, 25°C 1.0 ±3.0 Measured at code 64714, -40°C to 105°C 2.0 ±5.0 Gain Error Drift Full-Scale Error Bits -5 %FSR LSB mV mV ppm of FSR/°C Measured at code 64714, 25°C 0.5 ±3.0 Measured at code 64714, -40°C to 105°C 1.0 ±5.0 mV VREF V OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate (1) (2) 2 0 RL = 2 kΩ; CL <200 pF 8 RL = 2 kΩ; CL <500 pF 12 RL = 2 kΩ; CL <200 pF 1 Linearity calculated using a reduced code range of 485 to 64714. Output unloaded. Assured by design and characterization, not production tested. 10 µs V/µs DAC8544 www.ti.com SLAS420 – MAY 2004 ELECTRICAL CHARACTERISTICS (continued) VDD = + 2.7 V to + 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted DAC8544 PARAMETER Capacitive Load Stability CONDITIONS MIN RL = ∞ TYP MAX 470 RL = 2 kΩ UNITS pF 1000 pF Digital-to-Analog Glitch Impulse 20 nV-s Digital Feedthrough 0.5 nV-s DC Output Impedance Short-Circuit Current Power-Up Time Ω 1 VDD = +5 V 50 VDD = +3 V 20 Coming out of power-down mode, VDD = +5 V 2.5 Coming out of power-down mode, VDD = +3 V 5 mA µs REFERENCE INPUT VREF+ Input Range 0 VREF– Input Range –0.1 Reference Input Impedance VDD 0.0 VDD/2 140 V V kΩ LOGIC INPUTS Input Current VINL, Input Low Voltage IOVDD = +1.8 V – +5.5 V VINH, Input High Voltage IOVDD = +1.8 V – +5.5 V ±1 µA 0.3 x IOVDD V 3 pF 0.7 x IOVDD V Pin Capacitance POWER REQUIREMENTS VDD 2.7 5.5 V IOVDD 1.8 5.5 V IDD (Normal Mode) DAC active and excluding load current VDD = +3.6 V to +5.5 V VIH = IOVDD and VIL = IOGND 1.0 1.6 VDD = +2.7 V to +3.6 V VIH = IOVDD and VIL = IOGND 0.96 1.52 mA IDD (All Power-Down Modes) VDD = +3.6 V to +5.5 V VIH = IOVDD and VIL = IOGND 0.2 1 VDD = +2.7 V to +3.6 V VIH = IOVDD and VIL = IOGND 0.05 1 µA POWER EFFICIENCY IOUT/IDD ILOAD = 2 mA, VDD = +5 V 93 % 3 DAC8544 www.ti.com SLAS420 – MAY 2004 TIMING CHARACTERISTICS IOVDD = 1.8 V to 5.5 V; VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 85°C (unless otherwise noted) MIN TYP MAX UNIT tw1 Pulse width: CS low for valid write 20 ns tsu1 Setup time: R/W low before CS falling 0 ns tsu2 Setup time: data in valid before CS falling 0 ns th1 Hold time: R/W low after CS rising 10 ns th2 Hold time: data in valid after CS rising 15 ns tw2 Pulse width: CS low for valid read 40 ns tsu3 Setup time: R/W high before CS falling 30 td1 Delay time: data out valid after CS falling th3 Hold time: R/W high after CS rising th4 Hold time: data out valid after CS rising 5 tsu4 Setup time: LDAC rising after CS falling 10 ns td2 Delay time: CS low after LDAC rising 50 ns tw3 Pulse width: LDAC low 40 ns tw4 Pulse width: LDAC high 40 ns tw5 Pulse width: CS high 80 ns tw6 Pulse width: RST low 40 ns tw7 Pulse width: RST high 40 tS VOUT Settling time (settling time for a full-scale code change) ns 60 80 10 ns 20 tW5 tW2 CS tsu1 th1 tsu2 th2 tsu3 th3 R/W Data I/O DB0−DB15 th4 td1 Data In Valid Data Out Valid tsu4 th2 LDAC tW3 tw4 ±0.003% of FSR Error Bands V(OUT) ts 4 ns ns 10 Data Read/Write Timing tW1 ns µs DAC8544 www.ti.com SLAS420 – MAY 2004 Reset Timing tW6 RST tW7 ts +FS VOUT DEVICE INFORMATION VOUTC VFBC VREFC+ VREFC− VFBB VOUTB VREFB+ VREFB− VOUTA VREFA− VREFA+ VFBA Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 VDD 1 36 VREFD− GND 2 35 VREFD+ IOGND 3 34 VFBD IOVDD 4 33 VOUTD D15 5 32 D14 6 31 D13 7 30 VDD GND PD D12 8 29 D11 9 28 RST GND D10 10 27 LDAC D9 11 26 R/W D8 12 25 CS DAC8544 24 A0 A1 IOGND D0 21 22 23 IOVDD D1 D3 D2 D5 D4 D6 D7 13 14 15 16 17 18 19 20 5 DAC8544 www.ti.com SLAS420 – MAY 2004 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS DAC8544 Pin 6 Mnemonic Function 1 VDD Analog supply voltage, +2.7 V to +5.5 V 2 GND Analog supply ground 3 IOGND Digital supply ground 4 IOVDD Digital supply +1.8 V to +5.5 V 5 D15 Digital input, MSB 6 D14 Digital input 7 D13 Digital input 8 D12 Digital input 9 D11 Digital input 10 D10 Digital input 11 D9 Digital input 12 D8 Digital input 13 D7 Digital input 14 D6 Digital input 15 D5 Digital input 16 D4 Digital input 17 D3 Digital input 18 D2 Digital input 19 D1 Digital input 20 D0 Digital input, LSB 21 IOVDD Digital supply +1.8 V to +5.5 V 22 IOGND Digital supply ground 23 A1 Address pin for selecting between DAC channels 24 A0 Address pin for selecting between DAC channels 25 CS Active-low chip select. Used with R/W_ to write/read data to/from device 26 R/W Read/Write select used to write data to input register or read data from DAC register 27 LDAC Load DACs, rising edge triggered loads all DAC registers 28 GND Analog ground 29 RST Asynchronously resets contents of all DAC Registers to zero-scale, but does not affect input register 30 PD Active-low power-down pin puts entire device into power-down mode with DAC outputs in 3-state condition 31 GND Analog supply ground 32 VDD Analog supply voltage, +2.7 V to +5.5 V 33 VOUTD Analog output voltage from DAC-D 34 VFBD Analog output sense for DAC-D 35 VREFD+ High reference voltage input for DAC-D 36 VREFD– Low reference voltage input for DAC-D, normally VREFD– = GND 37 VOUTC Analog output voltage from DAC-C 38 VFBC Analog output sense for DAC-C 39 VREFC+ High reference voltage input for DAC-C 40 VREFC– Low reference voltage input for DAC-C, normally VREFC– = GND 41 VOUTB Analog output voltage from DAC-B 42 VFBB Analog output sense for DAC-B 43 VREFB+ High reference voltage input for DAC-B 44 VREFB– Low reference voltage input for DAC-B, normally VREFB– = GND 45 VOUTA Analog output voltage from DAC-A DAC8544 www.ti.com SLAS420 – MAY 2004 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) DAC8544 Pin Mnemonic Function 46 VFBA Analog output sense for DAC-A 47 VREFA+ High reference voltage input for DAC-A 48 VREFA– Low reference voltage input for DAC-A, normally VREFA– = GND 7 DAC8544 www.ti.com SLAS420 – MAY 2004 TYPICAL CHARACTERISTICS This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) TOTAL UNADJUSTED ERROR vs DIGITAL INPUT CODE ERROR vs TEMPERATURE 3 0.005 VDD = 5.5 V 2 0.003 Gain Full-Scale 0.002 1 Error − mV Total Unadjusted Error − V 0.004 0.001 0 −0.001 0 −1 Zero-Scale −0.002 −0.003 −2 −0.004 −0.005 0 10000 20000 30000 40000 Digital Input Code 50000 −3 −40 60000 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 1. Figure 2. ERROR vs TEMPERATURE OFFSET ERROR DISTRIBUTION (ACROSS MANY SAMPLES) 3 100 40 TA = 25°C VDD = 3.6 V 35 2 30 Error − mV Percentage − % Gain Full-Scale 1 0 −1 25 20 15 10 Zero-Scale 5 −2 0 −3 −40 25 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 −5 −1 100 0 0.2 0.4 0.6 0.8 Figure 4. GAIN ERROR DISTRIBUTION (ACROSS MANY SAMPLES) FULL SCALE ERROR DISTRIBUTION (ACROSS MANY SAMPLES) 1 25 TA = 25°C TA = 25°C 20 Percentage − % Percentage − % −0.2 Figure 3. 15 10 5 15 10 5 −0.8 −0.6 −0.4 −0.2 0 0.2 Gain Error − mV Figure 5. 8 −0.6 −0.4 Offset Error − mV 20 0 −1 −0.8 0.4 0.6 0.8 1 0 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 Full Scale Error − mV Figure 6. 0.6 0.8 1 DAC8544 www.ti.com SLAS420 – MAY 2004 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 1 0.8 48 0.4 16 DLE − LSB Linearity Error − LSB 0.6 32 0 −16 0.2 0 −0.2 −0.4 −32 −0.6 −48 −0.8 −64 0 10000 20000 30000 40000 Digital Input Code 50000 −1 60000 0 20000 30000 40000 Digital Input Code 50000 Figure 7. Figure 8. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 64 60000 Differential Linearity Error − LSB 1 48 Linearity Error − LSB 10000 MAX Error 32 16 0 MIN Error −16 −32 −48 0.8 0.6 Max 0.4 0.2 0 Min −0.2 −0.4 −0.6 −0.8 −64 −40 0 40 80 TA − Free-Air Temperature − C −1 −40 110 0 40 TA − Free-Air Temperature − °C Figure 9. VREF = VDD −10 mV DAC Loaded With 0000 110 Figure 10. SINK CURRENT AT NEGATIVE RAIL 0.15 80 SOURCE CURRENT AT POSITIVE RAIL 5 VDD = 5 V VDD = 2.7 V 0.1 V O − Output Voltage − V V O − Output Voltage − V 0.125 VDD = 5 V 0.075 0.05 4.95 4.9 4.85 0.025 VREF = VDD −10 mV DAC Loaded With FFFFH 4.8 0 0 1 2 3 ISINK − Sink Current − mA Figure 11. 4 5 0 1 2 3 4 ISOURCE − Source Current − mA 5 Figure 12. 9 DAC8544 www.ti.com SLAS420 – MAY 2004 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs DIGITAL INPUT CODE SOURCE CURRENT AT POSITIVE RAIL 2.8 800 VDD = 2.7 V VDD = 5 V I DD − Supply Current − µ A V O − Output Voltage − V 700 2.7 2.6 2.5 VREF = VDD −10 mV DAC Loaded With FFFFH 400 300 200 IREF Included 0 0 1 VDD = 2.7 V 500 100 2.4 2 3 4 ISOURCE − Source Current − mA 5 0 50000 SUPPLY CURRENT vs SUPPLY VOLTAGE 60000 1600 I DD − Supply Current − µ A 1400 VDD = 5.5 V 1000 VDD = 2.7 V 600 400 IREF = VDD, IDD Measured at Power-Up, Reference Current Included, No Load 1200 1000 800 600 400 200 0 −40 −20 0 20 40 60 TA − Free-Air Temperature − C 80 0 2.7 100 3.1 3.5 3.9 4.7 5.1 5.5 Figure 16. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 0.8 4000 0.7 3500 IREF Included 3000 IDD = 5.5 V 0.6 4.3 V DD − Supply Voltage − V Figure 15. VDD = 2.7 V Device Counts I DD − Supply Current − µ A 40000 SUPPLY CURRENT vs TEMPERATURE 200 0.5 0.4 0.3 VIH = 2.7 V 0.2 0 2500 VDD = 5.5 V 2000 1500 1000 500 0.1 0 1 2 3 Logic Input Voltage − V Figure 17. 10 30000 Figure 14. 1400 800 20000 Figure 13. IREF Included, Midcode 1200 10000 Digital Input Code 1600 I DD − Supply Current − µ A 600 4 5 0 600 700 800 900 1000 1100 IDD − Supply Current − A Figure 18. 1200 1300 DAC8544 www.ti.com SLAS420 – MAY 2004 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) EXITING POWER-DOWN MODE OUTPUT GLITCH (MID-SCALE) 2.54 5.5 Code Change From 7FFFh to 8000h to 7FFFh 5 2.52 V O− Output Voltage − V V O − Output Voltage − V 4.5 4 3.5 3 2.5 2 1.5 1 2.5 2.48 2.46 0.5 2.44 0 −0.5 2.42 0 5 10 t − Time − 4 s/div Figure 19. VDD = VREF= 5 V, Output Loaded With 2 kΩ and 200 pF to GND. 35 Large Signal VDD = VREF= 5 V, Output Loaded With 2 kΩ and 200 pF to GND. 2.5 V O − Output Voltage − V V O − Output Voltage − V 30 HALF-SCALE SETTLING TIME 3 5 25 Figure 20. FULL-SCALE SETTLING TIME Large Signal 15 20 t − Time − s 4 3 2 1 2 1.5 1 0.5 0 0 t − Time − 12 s/div t − Time − 12 s/div Figure 21. Figure 22. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME 3.5 VDD = VREF = 2.7 V Output Loaded With 2 kΩ and 200 pF to GND V O − Output Voltage − V 2.5 2 1.5 1 1.50 VOUT − Output Voltage − V Large Signal 3 1.00 VDD = VREF = 2.7 V Output Loaded With 2 kΩ and 200 pF to GND 0.50 0.5 0 0.00 t − Time − 12 s/div Figure 23. t − Time − 12 s/div Figure 24. 11 DAC8544 www.ti.com SLAS420 – MAY 2004 TYPICAL CHARACTERISTICS (continued) This condition applies to all typical characteristics: VREF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted) SIGNAL-TO-NOISE vs OUTPUT FREQUENCY TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 0 96 THD − Total Harmonic Distortion − dB SNR − Signal-to-Noise Ratio − dB 98 VDD = 5 V 94 92 VDD = 2.7 V 90 88 VDD = VREF −1 dB FSR Digital Input, FS = 52 Ksps Measurement Bandwidth = 20 kHz 86 84 0 −20 −30 −40 1k 1.5 k 2 k 2.5 k 3k Output Frequency − Hz 3.5 k 4k THD −50 −60 −70 −80 3rd Harmonic 2nd Harmonic −90 −100 500 VDD = VREF = 5 V FS = 52 Ksps −1 dB FSR Digital Input Measurement Bandwidth = 20 kHz −10 4.5 k 0 500 1k 1.5 k 2k 2.5 k Output Frequency − Hz 3k 3.5 k Figure 25. Figure 26. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY FULL-SCALE SETTLING TIME (SMALL-SIGNAL POSITIVE-GOING STEP) VO − Output Voltage − 5 mV/div THD − Total Harmonic Distortion − dB 0 VDD = VREF = 2.7 V FS = 52 Ksps, −1 dB FSR Digital Input Measurement Bandwidth = 20 kHz −10 −20 −30 −40 THD −50 −60 −70 Small-Signal Settling Trigger Signal −80 2nd Harmonic −90 3rd Harmonic −100 0 500 1k 1.5 k 2k 2.5 k Output Frequency − Hz 3k 3.5 k t − Time − 2 s/div 4k Figure 27. Figure 28. V O − Output Voltage − 5 mV/div FULL-SCALE SETTLING TIME (SMALL-SIGNAL NEGATIVE-GOING STEP) Small-Signal Settling Trigger Signal t − Time − 2 s/div Figure 29. 12 4k DAC8544 www.ti.com SLAS420 – MAY 2004 THEORY OF OPERATION D/A SECTION The architecture of the DAC8544 consists of four string DACs followed by an output buffer amplifier. Figure 30 shows a block diagram of the DAC architecture. External Reference (+) R VFB R _ VREF + Resistor String VREF − DAC Register + VOUT External Reference (–) Figure 30. DAC8544 Architecture The input coding to the DAC8544 is unsigned binary, which gives the ideal output voltage as: V REF V REF D 65536 (1) where • D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. RESISTOR STRING The resistor string section is shown in Figure 31. It is simply a divide-by-two resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off, to be fed into the output amplifier, by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is assured monotonic. To Output Amplifier VREF+ VREF– R R R R Figure 31. Resistor String OUTPUT AMPLIFIER The output buffer is capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to VREF+. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a full-scale settling time of 10 µs with the output loaded. The feedback and gain setting resistors of the amplifier are in the order of 50 kΩ. Their absolute value can be off significantly, but they are matched to within 0.1%. The inverting input of the output amplifier is brought out to the VFB pin, through the feedback resistor. This allows for better accuracy in critical applications by tying the VFB point and the amplifier output together at the load. Other signal conditioning circuitry may also be connected between these points for specific applications including current sourcing. 13 DAC8544 www.ti.com SLAS420 – MAY 2004 THEORY OF OPERATION (continued) PARALLEL INTERFACE The DAC8544 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input register. (See the timing characteristics section for detailed information for a typical write or read operation.) In addition to the data, CS, and R/W inputs, the DAC8544's interface also provides power down, LDAC, and reset/reset-select control. Table 1 and Table 2 show the control signal actions and data format, respectively. These features are discussed in more detail in the remaining sections. Table 1. DAC8544 CONTROL SIGNAL SUMMARY (1) CS R/W LDAC RST PD H X X X X Device data I/O is disabled on the bus. (1) ACTION ↓ L X H,L H Write initiated, present input data to the bus. ↓ H X H,L H Read initiated, data from input register is presented to data bus. ↑ X X H,L H Input data is latched when writing to the device. X X ↑ H,L H Data from input register is transferred to DAC register and VOUT is updated. X X X ↑ H DAC register and VOUT reset to min-scale. (If DAC is powered down during reset, DAC register resets and VOUT settles to min-scale on power up.) X X X X L Power down device, VOUT impedance equals high impedance Only disables 16-bit data I/O interface. Other control lines remain active. LDAC FUNCTION The DAC8544 is designed using a double-buffered architecture. A write operation (rising edge of CS while R/W is low) transfers data from the data input pins into the input register. The data is held in the input register until a rising-edge is detected on the LDAC input. This rising-edge signal transfers the data from the input register to the DAC register. On issuance of the rising LDAC edge, the output of the DAC8544 begins settling to the newly written data value presented to the DAC register. Data in the input register is not changed when an LDAC rising edge occurs. UPDATE SEQUENCE For regular operation, R/W pin should be kept low while CS is kept high. Then, the 16-bit digital data should be applied to the input bus. The channel selection should then be asserted by setting the A0 and A1 pins. The falling edge of CS enables the device. Once the data is stable and the channels are selected, the first rising edge of the CS signal latches the data to the input register of the selected channel. After the data is latched to the input register, the rising edge of the LDAC signal updates all four channels simultaneously with existing data from their corresponding input register. READBACK For read-back operation, the user first releases the 16-bit bus, while CS is high. Then, the DAC channel should be selected using the A0 and A1 pins. R/W pin is then brought high to enable read-back operation. Following the falling edge of CS, the data from the selected channel (buffer data) is output on the bus. RST The RST input controls the reset of the DAC register and, consequently, the DAC output, but does not change the input register. The reset operation is edge-triggered by a low-to-high transition on the RST pin. Once a rising edge on RST is detected, the DAC output settles to the zero code. Application of a valid reset signal to the DAC does not overwrite existing data in the input register. 14 DAC8544 www.ti.com SLAS420 – MAY 2004 POWER-ON RESET The DAC8544 contains a power-on reset circuit that controls the output voltage after power up. On power up, the DAC register (and DAC output) is set to zero (plus a small offset error produced by the output buffer). It remains at zero until a valid write sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is important to know the state of the output of the DAC after power up. All digital inputs must be logic low until the digital and analog supplies are applied. Logic high voltages, applied to the input pins when power is not applied to IOVDD and VDD, may power the device through the ESD input structures causing undesired operation. POWER-DOWN MODES The DAC8544 uses two modes of operation. These modes are programmable via pin PD. Table 2 shows how the state of the pin correspond to the mode of operation of the DAC8544. Table 2. Modes of Operation for the DAC8544 PD OPERATING MODE High Normal operation Low Power down, high impedance When pin PD is high, the device works normally with its typical power consumption of 950 µA at VDD = 5 V. However, when PD pin is in low state, the device is in power-down mode, the supply current falls to 200 nA at VDD = 5 V (50 nA at VDD = 3 V), and the output is open circuit (high impedance). All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down mode. This allows the DAC output voltage to return to the previous level when power up resumes. The delay time required to exit power-down is typically 2.5 µs for VDD = 5 V, and 5 µs for VDD = 3 V. (See the typical characteristics section for additional information.) VOLTAGE REFERENCE INPUTS Two voltage inputs provide the reference set points for the DAC architecture. These are VREF+ and VREF–. For typical rail-to-rail operation, VREF+ should be equivalent to VDD and VREF– tied to GND. The output voltage is given by: V OUT 2 V REF V REFVREF D 65536 (2) The use of the VREF– input allows minor adjustments to be made to the offset of the DAC output by applying a small voltage to the VREF– input. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is not affected. ANALOG AND DIGITAL SUPPLIES The analog supply (VDD) powers the output buffer and DAC while the digital supply (IOVDD) powers the digital interface. VDD can operate from 2.7 V to 5.5 V while IOVDD can independently function from 1.8 V to 5.5 V. IOVDD determines the interface logic level. See the device specification table for details. EXTERNAL REFERENCE VOLTAGE To take advantage of the absolute accuracy of DAC8544, a high-performance reference voltage generator must be used. DAC8544 has a typical absolute accuracy error of 2 millivolts, and a typical voltage drift of 3 ppm/°C. This level of performance requires an accurate external reference voltage generator with good temperature drift characteristics. Accuracy, drift, supply voltage, power consumption, and cost are important factors in choosing a voltage reference. TI's REF02 is recommended. TI's REF3140 and REF3040 are small and low-cost alternatives. 15 DAC8544 www.ti.com SLAS420 – MAY 2004 FEEDBACK PINS For regular operation, the feedback pins (VFBA through VFBD) must be tied to their corresponding output pins (VOUTA through VOUTD) at the load. For higher current applications sensitive to gain error, the feedback pin should be routed to the target node, to sense the node voltage accurately (DAC8544 gain error is typically low, around 1 mV). HOST PROCESSOR INTERFACING DAC8544 to MSP430 Microcontroller Figure 32 shows a typical parallel interface connection between the DAC8544 and a MSP430 microcontroller. The setup for the interface shown uses ports 4 and 5 of the MSP430 to send or receive the 16-bit data while bits 0-7 of port 2 provides the control signals for the DAC. When data is to be transmitted to the DAC8544, the data is made available to the DAC via P4 and P5, and P2.1 is taken low. The MSP430 then toggles P2.0 from high-to-low and back to high, transferring the 16-bit data to the DAC. This data is loaded into the DAC register by applying a rising edge to P2.4. The remaining five I/O signals of P2 shown in the figure control the reset, power-down, and data format functions of the DAC. Depending on the specific requirements of a given application, these pins may be tied to IOGND or IOVDD, enabling the desired mode of operation. MSP430F149 DAC8544 8 Bits P4[0:7] 16 Bits D[15:0] P5[0:7] P2:0 P2:1 P2:2 P2:4 P2:5 P2:6 P2:7 VDD VDD 8 Bits 0.1 F 10 F 0.1 F 10 F CS R/W RST LDAC PD IOVDD IOVDD VFB VOUT VOUT A0 VREF − VREF + VREF IOGND GND A1 0.1 F 1 to 10 F (Other Pins Omitted for Clarity) Figure 32. DAC8544 to MSP430 Microcontroller DAC8544 to TMS320C5402 DSP Figure 33 shows the connections between the DAC8544 and the TMS320C5402 digital signal processor. Data is provided via the parallel data bus of the DSP while the DAC CS control input is derived from the decoded I/O strobe signal. The IOSTRB in addition to the R/W and XF(I/O) signals control the data transmission to and from the DAC as well as the LDAC control. With additional decoding, multiple DAC8544s can be connected to the same parallel data bus of the DSP. 16 DAC8544 www.ti.com SLAS420 – MAY 2004 TMS320C5402 DAC8544 16 Bits D[15:0] D[15:0] IOSTRB EN Address Decoder R/W 0.1 F 10 F 0.1 F 10 F CS IOVDD IOVDD R/W XF(I/O) VDD VDD A[23:0] VFB LDAC VOUT VOUT VREF + VREF VREF − 0.1 F IOGND 1 to 10 F GND (Other Pins Omitted for Clarity) Figure 33. DAC8544 to TMS320 DSP BIPOLAR OPERATION USING THE DAC8544 The DAC8544 has been designed for single-supply operation but a bipolar output range is also possible using the circuit shown in Figure 34. The circuit allows the DAC8544 to achieve an analog output range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. R2 = 10 kΩ 5V R1 = 10 kΩ 5V − VREF + 10 µF 0.1 µF VOUT DAC8544 VFB + ±5 V OPA703 −5V VREF − (Other Pins Omitted for Clarity) Figure 34. Bipolar Operation With the DAC8544 With VREF+ = 5 V, R1 = R2 = 10 kΩ: V OUT 10 D 5V 65536 (3) 17 DAC8544 SLAS420 – MAY 2004 www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The following measures should be taken to assure optimum performance of the DAC8544. The DAC8544 offers dual-supply operation, as it can often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more important it becomes to separate the analog and digital ground and supply planes at the DAC. Because the DAC8544 has both analog and digital ground pins, return currents can be better controlled and have less effect on the DAC output error. Ideally, GND would be connected directly to an analog ground plane and GND to the digital ground plane. The analog ground plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. The power applied to VDD and VREF+ (this also applies to VREF– if not tied to GND) should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to 10-µF and 0.1-µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially lowpass-filter the VDD supply, removing the high-frequency noise. 18 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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