EDI88128C HI-RELIABILITY PRODUCT 128Kx8 Monolithic SRAM, SMD 5962-89598 FEATURES ■ Access Times of 70, 85, 100ns The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. ■ Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130) The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. ■ 2V Data Retention (LP Versions) ■ CS and OE Functions for Bus Control The second chip select line (CS 2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. ■ TTL Compatible Inputs and Outputs ■ Fully Static, No Clocks ■ Organized as 128Kx8 The EDI88128C and the EDI88130C have eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. ■ Industrial, Military and Commercial Temperature Ranges ■ Thru-hole and Surface Mount Packages JEDEC Pinout • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) • 32 lead Ceramic ZIP (Package 100) • 32 lead Ceramic SOJ (Package 140) Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. ■ Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION PIN DESCRIPTION 32 DIP 32 SOJ TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 NC/CS2* WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 32 ZIP I/O0-7 Data Inputs/Outputs TOP VIEW A0-16 Address Inputs WE Write Enable 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 VCC A15 NC/CS2* WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 CS1, CS2 Chip Selects OE Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array AØ-16 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE CS1 CS2 OE * Pin 30 is NC for 88128 or CS 2 for 88130. July 1999 Rev. 13 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128C TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Unit OE CS1 CS2 WE Mode Output Power V X X X H L X H X X L L L X L L H H H X X X H H L Standby Standby Output Deselect Output Deselect Read Write High Z High Z High Z High Z Data Out Data In Icc 2 , Icc 3 Icc 2 , Icc 3 Icc 1 Icc 1 Icc 1 Icc 1 -0.5 to 7.0 Operating Temperature TA (Ambient) 0 to +70 °C -40 to +85 °C Military -55 to +125 °C Storage Temperature, Plastic -65 to +150 °C Commercial Industrial Power Dissipation 1 W Output Current 20 mA Junction Temperature, TJ 175 °C RECOMMENDED OPERATING CONDITIONS Parameter NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Typ Max Supply Voltage VCC 4.5 5.0 5.5 Unit V Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.5 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE (T A = +25°C) Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Input/Output Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = +25°C) Parameter Symbol Conditions Units Min Typ Max Input Leakage Current ILI VIN = 0V to VCC -5 — +5 µA Output Leakage Current ILO VI/O = 0V to VCC, CS1 ≥ VIH and/or CS2 ≤ VIL -10 — +10 µA Operating Power Supply Current I CC1 WE, CS 1 = VIL, II/O = 0mA, Min Cycle CS2 = VIH (70-85ns) — 120 mA (100ns) — 110 mA 10 mA I CC2 CS 1 ≥ VIH and/or CS2 ≤ VIL, VIN ≥ VIH or ≤ VIL I CC3 CS 1 ≥ VCC -0.2V and/or CS2 ≤ Vcc +0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V Output Low Voltage VOL IOL = 2.1mA Output High Voltage VOH IOH = -1.0mA Standby (TTL) Power Supply Current Full Standby Power Supply Current NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 — C — 1 5 mA LP — — 1 mA — — 0.4 V 2.4 — — V EDI88128C AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Parameter Symbol JEDEC Alt. Min 70ns 85ns Read Cycle Time tAVAV tRC 70 Address Access Time tAVQV tAA 70 85 100 ns Chip Select Access Time tELQV tSHQV tACS tACS 70 70 85 85 100 100 ns ns Chip Select to Output in Low Z (1) tELQX tSHQX tCLZ tCLZ 3 3 Chip Disable to Output in High Z (1) tEHQZ tSLQZ tCHZ tCHZ 0 0 Output Hold from Address Change tAVQX tOH 3 Output Enable to Output Valid tGLQV tOE Max Min 85 30 30 0 0 Output Enable to Output in Low Z (1) tGLQX tOLZ 0 tGHQZ tOHZ 0 30 30 0 0 0 ns ns 30 30 ns ns 50 ns 30 ns ns 0 30 0 Units ns 3 30 0 Max 3 3 3 30 Min 100 3 3 25 Output Disable to Output in High Z (1) 100ns Max ns 1. This parameter is guaranteed by design but not tested. AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q Q 255Ω 30pF 255Ω 5pF 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128C AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C) Parameter Symbol JEDEC Alt. Min 70ns Write Cycle Time tAVAV tWC 70 85 100 ns Chip Select to End of Write tELWH tELEH tSHWH tSHSL tCW tCW tCW tCW 60 60 60 60 75 75 75 75 85 85 85 85 ns ns ns ns Address Setup Time tAVWL tAVEL tAVSH tAS tAS tAS 0 0 0 0 0 0 0 0 0 ns ns ns Address Valid to End of Write tAVWH tAW 60 75 85 ns Write Pulse Width tWLWH tWLEH tWLSL tWP tWP tWP 35 35 35 70 70 70 80 80 80 ns ns ns Write Recovery Time tWHAX tEHAX tSLAX tWR tWR tWR 5 5 5 5 5 5 5 5 5 ns ns ns Data Hold Time tWHDX tEHDX tSLDX tDH tDH tDH 0 0 0 0 0 0 0 0 0 ns ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDVSL tDW tDW tDW 35 35 35 40 40 40 40 40 40 ns ns ns Output Active from End of Write (1) tWHQX tWLZ 5 5 5 ns 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 85ns Max 30 Min 0 100ns Max 35 Min 0 Max 40 Units ns EDI88128C tAVAV FIG. 2 ADDRESS TIMING WAVEFORM - READ CYCLE tAVQV CS1 tELQV tELQX tEHQZ tSHQV tSHQX tSLQZ tAVAV CS2 ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX DATA I/O OE DATA 1 tGLQV tGLQX DATA 2 tGHQZ DATA I/O READ CYCLE 2 (WE HIGH) READ CYCLE 1 (WE HIGH; OE, CS LOW) FIG. 3 tAVAV WRITE CYCLE 1 ADDRESS tAVWL tAVWH tWLWH tWHAX WE CS1 tELWH CS2 tSHWH tWHQX tWHDX tDVWH DATA IN DATA VALID tWLQZ HIGH Z DATA OUT WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED FIG. 4 WRITE CYCLE 3 WRITE CYCLE2 WS32K32-XHX tAVAV tAVEL tEHAX tWLEH tAVSH tSLAX tWLSL WE WE tSHSL tELEH CS1 CS1 CS2 CS2 tDVEH DATA IN tAVAV ADDRESS ADDRESS tDVSL tEHDX DATA IN DATA VALID tSLDX DATA VALID WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128C DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY) (TA = -55°C to +125°C) Characteristic Low Power Version only Data Retention Voltage Sym VDD Data Retention Quiescent Current ICCDR Chip Disable to Data Retention Time (1) TCDR VIN ≥ VDD -0.2V Operation Recovery Time (1) TR Conditions Min Typ VDD = 2.0V 2 – – V CS1 ≥ VDD -0.2V – – 400 µA or VIN ≤ 0.2V 0 – – ns – – ns * Read Cycle Time FIG. 5 DATA RETENTION - CS1 CONTROLLED Data Retention Mode 4.5V WS32K32-XHX 4.5V VDD tCDR tR CS1 ≥ VDD -0.2V CS1 DATA RETENTION, CS1 CONTROLLED FIG. 6 DATA RETENTION - CS2 CONTROLLED Data Retention Mode 4.5V Vcc WS32K32-XHX VDD 4.5V tCDR tR CS2 ≤ 0.2V CS2 DATA RETENTION, CS2 CONTROLLED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 Units TAVAV* NOTE: 1. Parameter guaranteed by design, but not tested. Vcc Max EDI88128C PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 0.175 0.125 0.061 0.017 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.100 TYP 0.020 0.016 0.155 0.115 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 100: 32 LEAD CERAMIC ZIP 1.65 MAX 0.125 MAX 0.500 MAX 0.040 0.020 0.155 0.125 0.100 NOM 0.040 MIN 0.050 31 x 0.050 = 1.550 ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ 0.108 0.088 0.840 0.820 0.040 0.030 0.440 0.430 0.379 REF 0.155 0.120 0.050 TYP ALL DIMENSIONS ARE IN INCHES 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128C ORDERING INFORMATION EDI 8 8 128 C X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 8 130 = Dual Chip Select TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140) Z = 32 lead Ceramic ZIP (Package 100) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8