ETC HCPL-J456#300

Intelligent Power Module
and Gate Drive Interface
Optocouplers
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
Technical Data
Features
• Performance Specified for
Common IPM Applications
over Industrial Temperature
Range: -40°C to 100°C
• Fast Maximum Propagation
Delays
tPHL = 480 ns
tPLH = 550 ns
• Minimized Pulse Width
Distortion
PWD = 450 ns
• 15 kV/µs Minimum Common
Mode Transient Immunity
at VCM = 1500 V
• CTR > 44% at IF = 10 mA
• Safety Approval
UL Recognized
-2500 V rms / 1 min. for
HCPL-4506/0466
-3750 V rms / 1 min. for
HCPL-J456
-5000 V rms / 1 min. for
HCPL-4506 Option 020
and HCNW4506
Applications
CSA Approved
BSI Certified (HCNW4506)
VDE0884 Approved
-VIORM = 560 Vpeak for
HCPL-0466 Option 060
-VIORM = 630 Vpeak for
HCPL-4506 Option 060
-VIORM = 891 Vpeak for
HCPL-J456
-VIORM = 1414 Vpeak for
HCNW4506
Functional Diagram
NC
1
• IPM Isolation
• Isolated IGBT/MOSFET Gate
Drive
• AC and Brushless DC Motor
Drives
• Industrial Inverters
Truth Table
8
VCC
LED
VO
ON
OFF
L
H
20 kΩ
ANODE
2
7
VL
CATHODE
3
6
VO
NC
4
5
GND
SHIELD
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
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2
Description
The HCPL-4506 and HCPL-0466
contain a GaAsP LED while the
HCPL-J456 and the HCNW4506
contain an AlGaAs LED. The LED
is optically coupled to an integrated high gain photo detector.
Minimized propagation delay
difference between devices makes
these optocouplers excellent
solutions for improving inverter
efficiency through reduced
switching dead time.
An on chip 20 kΩ output pull-up
resistor can be enabled by
shorting output pins 6 and 7, thus
eliminating the need for an
external pull-up resistor in
common IPM applications.
Specifications and performance
plots are given for typical IPM
applications.
Selection Guide
Package
Type
Part
Number
VDE0884
Approval
Standard
8-Pin DIP
(300 Mil)
White Mold
8-Pin DIP
(300 Mil)
Small Outline
SO8
Widebody
(400 Mil)
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
VIORM = 630 Vpeak VIORM = 891 Vpeak VIORM = 560 Vpeak VIORM = 1414 Vpeak
(Option 060)
(Option 060)
*Technical data for these products are on separate Agilent publications.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4506#XXX
020 = UL 5000 V rms/1 minute Option** for HCPL-4506 Only.
060 = VDE0884 Option** for HCPL-4506/0466.
300 = Gull Wing Lead Option for HCPL-4506/J456, HCNW4506.
500 = Tape and Reel Packaging Option
Option data sheets are available. Contact Agilent sales representative or authorized distributor
for information.
**Combination of Option 020 and Option 060 is not available.
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Hermetic*
HCPL-5300
HCPL-5301
—
3
Package Outline Drawings
HCPL-4506 and HCPL-J456 Outline Drawing
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW RU
1
2
3
UL
RECOGNITION
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS (HCPL-4506).
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
HCPL-4506 and HCPL-J456 Gull Wing Surface Mount Option 300 Outline Drawing
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.398 (0.370)
9.906 (0.390)
4
1.194 (0.047)
1.778 (0.070)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
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0.381 (0.015)
0.635 (0.025)
0.635 ± 0.25
(0.025 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
4
HCPL-0466 Outline Drawing (8-Pin Small Outline Package)
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
PIN ONE 1
2
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.270 BSG
(0.050)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
3.175 ± 0.127
(0.125 ± 0.005)
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
HCNW4506 Outline Drawing (8-Pin Widebody Package)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
9.00 ± 0.15
(0.354 ± 0.006)
5
TYPE NUMBER
A
HCNWXXXX
DATE CODE
YYWW
1
2
3
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
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0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
5
HCNW4506 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
PAD LOCATION (FOR REFERENCE ONLY)
5
6.15
(0.242)TYP.
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
1
2
3
4
1.3
(0.051)
0.9
(0.035)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
2.54
(0.100)
BSC
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
TEMPERATURE – °C
Solder Reflow Temperature Profile
260
240
220
200
180
160
140
120
100
80
60
40
20
0
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
0
1
2
3
4
5
6
7
8
9
10
11
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is recommended.
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12
6
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard
HCPL-4506
HCPL-J456
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Underwriters Laboratories (UL)
UL 1577
Recognized under UL 1577, Component
Recognized Program, Category FPQU2,
File E55361
Canadian Standards
Component
Association (CSA)
Acceptance
File CA88324
Notice #5
Verband Deutscher
DIN VDE 0884
Electrotechniker (VDE)
(June 1992)
Technischer
DIN VDE 0884
Uberwachungs-Verein
(June 1992)
Rheinland (TUV) Certificate R9650938
British
Certification according to
Standards
BS EN60065: 1994(BS415:1994),
Institute
BS EN 60950: 1992(BS7002:1992),
(BSI)
and IEC 65(1985).
HCPL-0466 HCNW4506
✔
✔
✔
Insulation and Safety Related Specifications
Parameter
Value
Symbol HCPL-4506 HCPL-J456 HCPL-0466 HCNW4506 Units
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
7.4
4.9
9.6
mm
Minimum External
Tracking (External
Creepage)
L(102)
7.4
8.0
4.8
10.0
mm
0.08
0.5
0.08
1.0
mm
NA
NA
NA
4.0
mm
≥ 175
≥ 175
≥ 175
≥ 200
Volts
IIIa
IIIa
IIIa
IIIa
Minimum Internal
Plastic Gap
(Internal Clearance)
Minimum Internal
Tracking (Internal
Creepage)
Tracking Resistance
(Comparative
Tracing Index)
Isolation Group
CTI
Conditions
Measured from input
terminals to output
terminals, shortest
distance through air.
Measured from input
terminals to output
terminals, shortest
distance path along body.
Through insulation
distance, conductor to
conductor, usually the
direct distance between
the photoemitter and
photodetector inside the
optocoupler cavity.
Measured from input
terminals to output
terminals, along internal
cavity.
DIN IEC 112/VDE 0303
Part 1
Material Group (DIN
VDE 0110, 1/89, Table 1)
All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be
met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a
printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage
and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and
insulation level.
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7
VDE 0884 Insulation Related Characteristics
HCPL-0466 HCPL-4506
Description
Symbol Option 060 Option 060 HCPL-J456 HCNW4506 Unit
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
I-IV
I-IV
I-IV
I-IV
for rated mains voltage ≤ 300 V rms
I-III
I-IV
I-IV
I-IV
for rated mains voltage ≤ 450 V rms
I-III
I-III
I-IV
for rated mains voltage ≤ 600 V rms
I-III
I-IV
for rated mains voltage ≤ 1000 V rms
I-III
Climatic Classification
55/100/21
55/100/21
55/100/21
55/100/21
Pollution Degree
2
2
2
2
(DIN VDE 0110/1.89)
Maximum Working
VIORM
560
630
891
1414
Vpeak
Insulation Voltage
Input to Output Test Voltage,
Method b* VIORM x 1.875 = VPR,
100% Production Test with tm =
VPR
1050
1181
1670
2652
Vpeak
1 sec, Partial Discharge < 5pC
Input to Output Test Voltage,
Method a* VIORM x 1.5 = VPR,
Type and Sample Test, tm = 60 sec,
VPR
840
945
1336
2121
Vpeak
Partial Discharge < 5pC
Highest Allowable Overvoltage*
VIOTM
4000
6000
6000
8000
Vpeak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values – maximum
values allowed in the event of a failure, also see Thermal Derating curve.
Case Temperature
TS
150
175
175
150
°C
Input Current
IS INPUT
150
230
400
400
mA
Output Power
PS OUTPUT
600
600
600
700
mW
9
9
9
9
Insulation Resistance at TS,
RS
≥ 10
≥ 10
≥ 10
≥ 10
Ω
VIO = 500 V
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (VDE 0884) for a detailed description of
Method a and Method b partial discharge test profiles.
Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data
shall be ensured by means of protective circuits.
Note: Insulation Characteristics are per DIN VDE 0884 (June 1992 revision).
Note: Surface mount classification is Class A in accordance with CECC 00802.
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Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current[1]
Peak Input
Current[2]
(50% duty cycle, ≤ 1 ms pulse width)
Peak Transient Input Current (<1 µs pulse width, 300 pps)
Reverse Input Voltage (Pin 3-2)
Symbol
TS
Min.
-55
Max.
125
Units
°C
TA
-40
IF(avg)
100
25
°C
mA
IF(peak)
50
mA
IF(tran)
1.0
A
VR
5
Volts
IO(avg)
3
15
mA
VCC
30
30
Volts
Volts
Volts
100
145
mW
mW
HCPL-4506, HCPL-0466
HCPL-J456, HCNW4506
Average Output Current (Pin 6)
Resistor Voltage (Pin 7)
Output Voltage (Pin 6-5)
Supply Voltage (Pin 8-5)
V7
VO
VCC
Output Power Dissipation[3]
Total Power Dissipation[4]
PO
PT
Lead Solder Temperature (HCPL-4506, HCPL-J456)
Lead Solder Temperature (HCNW4506)
260°C for 10 s, 1.6 mm below seating plane
260°C for 10 s
(up to seating plane)
See Package Outline Drawings Section
Infrared and Vapor Phase Reflow Temperature
(HCPL-0466 and Option 300)
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
Output Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
VCC
VO
4.5
0
10
-5
-40
30
30
20
0.8
100
Volts
Volts
mA
V
°C
IF(on)
VF(off) *
TA
*Recommended VF(OFF) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
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-0.5
-0.5
-0.5
9
Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Current Transfer Ratio
Symbol
CTR
Low Level Output Current
IOL
Low Level Output Voltage
VOL
Input Threshold Current
ITH
Device
Min. Typ.* Max. Units Test Conditions Fig. Note
44
90
%
IF = 10 mA,
5
VO = 0.6 V
4.4
9.0
mA
IF = 10 mA,
VO = 0.6 V
1, 2
0.3
0.6
V
IO = 2.4 mA
HCPL-4506
HCPL-0466
HCNW4506
1.5
5
mA
VO = 0.8 V,
IO = 0.75 mA
1
HCPL-J456
0.6
3
16
High Level Output Current
IOH
5
50
µA
VF = 0.8 V
High Level Supply Current
ICCH
0.6
1.3
mA
VF = 0.8 V,
VO = Open
16
Low Level Supply Current
ICCL
0.6
1.3
mA
IF = 10 mA,
VO = Open
16
1.5
1.8
V
IF = 10 mA
1.6
1.95
HCNW4506
1.6
1.85
∆VF/∆TA HCPL-4506
HCPL-0466
-1.6
Input Forward Voltage
VF
HCPL-4506
HCPL-0466
HCPL-J456
Temperature Coefficient
of Forward Voltage
1.2
HCPL-J456
HCNW4506
Input Reverse Breakdown
Voltage
Input Capacitance
BVR
CIN
Internal Pull-up Resistor
RL
Internal Pull-up Resistor
Temperature Coefficient
∆RL/∆TA
5
HCPL-J456
HCNW4506
3
mV/°C IF = 10 mA
V
60
HCPL-J456
HCNW4506
72
14
IR = 10 µA
IR = 100 µA
HCPL-4506
HCPL-0466
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5
-1.3
HCPL-4506
HCPL-0466
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
4
20
0.014
25
pF
f = 1 MHz,
VF = 0 V
kΩ
TA = 25°C
kΩ/°C
12, 13
10
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Propagation Delay
Time to Logic HCPL-J456
Low at Output
Propagation Delay
Time to High
Output Level
Pulse Width
Distortion
Propagation Delay
Difference Between
Any 2 Parts
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
Transient Immunity
Symbol Min. Typ.* Max. Units
Test Conditions
TPHL
30 200
400 ns
C L = 100 pF IF(on) = 10 mA,
480
VF(off) = 0.8 V,
100
C L = 10 pF VCC = 15.0 V,
TPLH 270 400
550 ns
C L = 100 pF VTHLH = 2.0 V,
VTHHL = 1.5 V
130
C L = 10 pF
PWD
200
450 ns
C L = 100 pF
tPLH-tPHL -150 200
450
Fig.
6, 8,
1013
20
ns
|CMH|
15
30
kV/µs IF = 0 mA,
VO > 3.0 V
|CML|
15
30
kV/µs IF = 10 mA
VO < 1.0 V
Note
11,
14,
16
17
VCC = 15.0 V,
C L = 100 pF,
VCM = 1500 Vp-p
TA = 25°C
7
18
19
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Propagation Delay
Time to Logic HCPL-J456
Low at Output
Propagation Delay Time
to High Output Level
Pulse Width
Distortion
Propagation Delay
Difference Between
Any 2 Parts
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
Transient Immunity
Power Supply
Rejection
Symbol Min. Typ.* Max. Units
Test Conditions
tPHL
20 200 400 ns IF(on) = 10 mA, VF(off) = 0.8 V,
485
VCC = 15.0 V, CL = 100 pF,
VTHLH = 2.0 V, VTHHL = 1.5 V
tPLH
220 450 650 ns
PWD
Fig. Note
6, 9 11-14,
16
250
500
ns
20
tPLH-tPHL -150 250
500
ns
17
|CMH|
30
|CML|
30
PSR
1.0
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
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kV/µs IF = 0 mA,
VO > 3.0 V
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 V p-p,
kV/µs IF = 16 mA, TA = 25°C
VO < 1.0 V
Vp-p Square Wave, tRISE, tFALL
> 5 ns, no bypass capacitors
7
18
19
16
11
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter
Sym.
Device
Input-Output Momentary VISO HCPL-4506
Withstand Voltage†
HCPL-0466
HCPL-J456
HCPL-4506
Option020
HCNW4506
Resistance
RI-O HCPL-4506
(Input-Output)
HCPL-J456
HCPL-0466
HCNW4506
Capacitance
CI-O HCPL-4506
(Input-Output)
HCPL-0466
HCPL-J456
HCNW4506
Min. Typ.* Max. Units
2500
V rms
3750
5000
Test Conditions Fig.
RH < 50%
t = 1 min.
TA = 25°C
5000
1012
1012
1013
0.6
Ω
pF
VI-O = 500 Vdc
f = 1 MHz
Note
6,7,10
6,8,10
6,9,
15
6,9,10
6
6
0.8
0.5
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.
Notes:
1. Derate linearly above 90°C free-air
temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air
temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air
temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air
temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in
percent is defined as the ratio of
output collector current (IO) to the
forward LED input current (IF) times
100.
6. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
7. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 V rms for 1 second (leakage
detection current limit, I I-O ≤ 5 µA).
8. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage ≥
4500 V rms for 1 second (leakage
detection current limit, I i-o ≤ 5 µA).
9. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage ≥
6000 V rms for 1 second (leakage
detection current limit, I I-O ≤ 5 µA).
10. This test is performed before the
100% Production test shown in the
VDE 0884 Insulation Related
Characteristics Table, if applicable.
11. Pulse: f = 20 kHz, Duty Cycle = 10%.
12. The internal 20 kΩ resistor can be
used by shorting pins 6 and 7
together.
13. Due to tolerance of the internal
resistor, and since propagation delay
is dependent on the load resistor
value, performance can be improved
by using an external 20 kΩ 1% load
resistor. For more information on
how propagation delay varies with
load resistance, see Figure 8.
14. The RL = 20 kΩ, C L = 100 pF load
represents a typical IPM (Intelligent
Power Module) load.
15. See Option 020 data sheet for more
information.
16. Use of a 0.1 µF bypass capacitor
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17.
18.
19.
20.
connected between pins 5 and 8 can
improve performance by filtering
power supply line noise.
The difference between tPLH and tPHL
between any two devices under the
same test condition. (See IPM Dead
Time and Propagation Delay
Specifications section.)
Common mode transient immunity in
a Logic High level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., VO > 3.0 V).
Common mode transient immunity in
a Logic Low level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state (i.e., VO < 1.0 V).
Pulse Width Distortion (PWD) is
defined as |tPHL - tPLH| for any given
device.
1.05
NORMALIZED OUTPUT CURRENT
IO – OUTPUT CURRENT – mA
10
8
6
4
VO = 0.6 V
2
0
100 °C
25 °C
-40 °C
0
5
10
15
1.00
0.95
0.90
IF = 10 mA
VO = 0.6 V
0.85
0.80
-40
20
-20
IF – FORWARD LED CURRENT – mA
IF – INPUT FORWARD CURRENT – mA
IF – FORWARD CURRENT – mA
TA = 25°C
IF
+
10
VF
–
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
80
100
1.50
1.60
15.0
4.5 V
30 V
10.0
5.0
0
-40
-20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 3. High Level Output
Current vs. Temperature.
TA = 25 °C
10
IF
+
VF
–
1
0.1
0.01
0.001
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VF – INPUT FORWARD VOLTAGE – V
Figure 4. HCPL-4506 and HCPL-0466
Input Current vs. Forward Voltage.
1
VF = 0.8 V
VCC = VO = 4.5 V OR 30 V
HCPL-J456/HCNW4506
100
VF – FORWARD VOLTAGE – VOLTS
Figure 5. HCPL-J456 and HCNW4506
Input Current vs. Forward Voltage.
8
2
20 kΩ
0.1 µF
20 kΩ
IF(ON) =10 mA
+
60
Figure 2. Normalized Output Current
vs. Temperature.
HCPL-4506/0466
100
40
20.0
TA – TEMPERATURE – °C
Figure 1. Typical Transfer
Characteristics.
1000
20
0
IOH – HIGH LEVEL OUTPUT CURRENT – µA
12
+
–
7
If
VCC = 15 V
5V
–
3
6
tf
VO
VOUT
tr
90%
90%
10%
10%
CL *
4
5
SHIELD
*TOTAL LOAD CAPACITANCE
Figure 6. Propagation Delay Test Circuit.
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VTHHL
VTHLH
tPHL
tPLH
100
13
1
VCM
8
0.1 µF
20 kΩ
IF
+
–
A
B
δV = VCM
δt
∆t
20 kΩ
7
2
3
6
OV
VCC = 15 V
∆t
VOUT
100 pF*
4
+
VO
5
VFF
VCC
SWITCH AT A: IF = 0 mA
SHIELD
*100 pF TOTAL
CAPACITANCE
–
VO
VOL
+
–
SWITCH AT B: IF = 10 mA
VCM = 1500 V
Figure 7. CMR Test Circuit. Typical CMR Waveform.
600
tP – PROPAGATION DELAY – ns
400
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
300
200
100
-40
-20
0
20
40
60
80
500
(INTERNAL)
tPLH
tPHL
400
300
200
100
-40
100
TA – TEMPERATURE – °C
800
1000
400
200
0
100
200
300
400
60
80
600
400
tPLH
tPHL
200
0
100
200
15
20
25
VCC – SUPPLY VOLTAGE – V
CL – LOAD CAPACITANCE – pF
Figure 11. Propagation Delay vs. Load
Capacitance.
400
10
Figure 12. Propagation Delay vs.
Supply Voltage.
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40
50
500
600
5
30
Figure 10. Propagation Delay vs. Load
Resistance.
800
0
500
20
10
RL – LOAD RESISTANCE – kΩ
IF = 10 mA
CL = 100 pF
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1200
600
0
40
Figure 9. Propagation Delay with
Internal 20 kΩ RL vs. Temperature.
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
1000
20
1400
IF = 10 mA
VCC = 15 V
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1200
0
-20
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 °C
TA – TEMPERATURE – °C
Figure 8. Propagation Delay with
External 20 kΩ RL vs. Temperature.
1400
800
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
tPLH
tPHL
tP – PROPAGATION DELAY – ns
500
30
tPLH
tPHL
400
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
TA = 25°C
300
200
100
0
5
10
15
20
IF – FORWARD LED CURRENT – mA
Figure 13. Propagation Delay vs. Input
Current.
HCPL-4506 OPTION 060/HCPL-J456
800
PS (mW)
IS (mA) FOR HCPL-4506
OPTION 060
IS (mA) FOR HCPL-J456
700
600
500
400
300
(230)
200
100
0
0
25
50
75 100 125 150 175 200
OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS
14
1000
HCPL-0466 OPTION 060/HCNW4506
PS (mW) FOR HCNW4506
IS (mA) FOR HCNW4506
PS (mW) FOR HCPL-0466
OPTION 060
IS (mA) FOR HCPL-0466
OPTION 060
900
800
700
600
500
400
300
200
(150)
100
0
0
25
50
75
100 125 150 175
TS – CASE TEMPERATURE – °C
TS – CASE TEMPERATURE – °C
Figure 14. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per VDE 0884.
1
310 Ω
2
7
3
6
8
20 kΩ
0.1 µF
20 kΩ
+5 V
1
8
2
7
3
VOUT
CMOS
6
CLEDN
100 pF
4
20 kΩ
CLEDP
+
– VCC = 15 V
4
5
5
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 15. Recommended LED Drive Circuit.
1
2
Figure 16. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
1
8
CLEDP
CLED02
310 Ω
6
CLEDN
4
0.1 µF
20 kΩ
7
CLED01
3
8
+5 V
20 kΩ
2
7
3
6
4
5
CMOS
5
20 kΩ
+
– VCC = 15 V
VOUT
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 17. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 18. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
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15
1
310 Ω
ICLEDP
2
IF
1
CLED02
CLEDP
7
2
CLEDP
CLED02
CLED01
3
310 Ω
VOUT
6
CLEDN
3
+ VR** –
5
CLEDN
VOUT
6
ICLEDN*
100 pF
4
20 kΩ
7
CLED01
ICLED01
SHIELD
100 pF
4
5
SHIELD
–
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
8
20
kΩ
20 kΩ
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
VCM
+
–
ITOTAL*
8
20
kΩ
VCM
Figure 19. AC Equivalent Circuit for Figure 18 During
Common Mode Transients.
Figure 20. AC Equivalent Circuit for Figure 15 During
Common Mode Transients.
1
1
2
8
+5 V
20 kΩ
7
CLEDP
CLED02
20 kΩ
7
CLED01
Q1
2
8
20
kΩ
3
CLEDN
6
VOUT
ICLEDN*
6
4
5
SHIELD
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
–
3
Q1
100 pF
4
VCM
Figure 21. Not Recommended Open
Collector LED Drive Circuit.
1
Figure 22. AC Equivalent Circuit for Figure 21 During
Common Mode Transients.
8
+5 V
20 kΩ
2
7
3
6
4
5
SHIELD
Figure 23. Recommended LED Drive
Circuit for Ultra High CMR.
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16
HCPL-4506
8
1
I
20 kΩ
LED1
2
+5 V
VCC1
0.1 µF
IPM
20 kΩ
7
+HV
310 Ω
3
6
4
5
VOUT1
CMOS
Q1
M
SHIELD
Q2
HCPL-4506
8
1
I
20 kΩ
LED2
2
+5 V
VCC2
0.1 µF
HCPL-4506
-HV
HCPL-4506
20 kΩ
7
HCPL-4506
310 Ω
3
6
4
5
VOUT2
CMOS
HCPL-4506
HCPL-4506
SHIELD
Figure 24. Typical Application Circuit.
ILED1
Q1 OFF
VOUT1
VOUT2
Q1 ON
Q2 OFF
Q2 ON
ILED1
ILED2
tPLH
Q1 OFF
VOUT1
VOUT2
MIN.
tPLH
MAX.
Q1 ON
Q2 OFF
Q2 ON
PDD*
MAX.
tPHL
MIN.
tPHL
MAX.
ILED2
MAX.
DEAD TIME
tPLH MAX.
tPHL
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
MIN.
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
PDD* MAX. =
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
Figure 25. Minimum LED Skew for Zero Dead Time.
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= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 26. Waveforms for Dead Time Calculation.
17
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive coupling from the input side of the
optocoupler, through the
package, to the detector IC
as shown in Figure 16. The
HCPL-4506 series improve
CMR performance by using a
detector IC with an optically
transparent Faraday shield, which
diverts the capacitively coupled
current away from the sensitive
IC circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and
the optocoupler output pins and
output ground as shown in Figure
17. This capacitive coupling
causes perturbations in the LED
current during common mode
transients and becomes the
major source of CMR failures
for a shielded optocoupler. The
main design objective of a high
CMR LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 15), can achieve
15 kV/µs CMR while minimizing
component complexity. Note that
a CMOS gate is recommended
in Figure 15 to keep the LED
off when the gate is in the high
state.
Another cause of CMR failure for
a shielded optocoupler is direct
coupling to the optocoupler
output pins through CLEDO1 and
CLEDO2 in Figure 17. Many factors
influence the effect and magnitude of the direct coupling
including: the use of an internal
or external output pull-up
resistor, the position of the LED
current setting resistor, the
connection of the unused input
package pins, and the value of the
capacitor at the optocoupler
output (CL).
Techniques to keep the LED in
the proper state and minimize the
effect of the direct coupling are
discussed in the next two
sections.
CMR with the LED On
(CMRL )
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. The recommended
minimum LED current of 10 mA
provides adequate margin over
the maximum I TH of 5.0 mA (see
Figure 1) to achieve 15 kV/µs
CMR. Capacitive coupling is
higher when the internal load
resistor is used (due to C LEDO2)
and an IF = 16 mA is required to
obtain 10 kV/µs CMR.
The placement of the LED current
setting resistor effects the ability
of the drive circuit to keep the
LED on during transients and
interacts with the direct coupling
to the optocoupler output. For
example, the LED resistor in
Figure 18 is connected to the
anode. Figure 19 shows the AC
equivalent circuit for Figure 18
during common mode transients.
During a +dVcm/dt in Figure 19,
the current available at the LED
anode (Itotal) is limited by the
series resistor. The LED current
(IF) is reduced from its DC value
by an amount equal to the current
that flows through CLEDP and
C LEDO1. The situation is made
worse because the current
through C LEDO1 has the effect of
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trying to pull the output high
(toward a CMR failure) at the
same time the LED current is
being reduced. For this reason,
the recommended LED drive
circuit (Figure 15) places the
current setting resistor in series
with the LED cathode. Figure 20
is the AC equivalent circuit for
Figure 15 during common mode
transients. In this case, the LED
current is not reduced during a
+dVcm/dt transient because the
current flowing through the
package capacitance is supplied
by the power supply. During a
-dVcm/dt transient, however, the
LED current is reduced by the
amount of current flowing
through CLEDN. But, better CMR
performance is achieved since the
current flowing in CLEDO1 during a
negative transient acts to keep the
output low.
Coupling to the LED and output
pins is also affected by the connection of pins 1 and 4. If CMR is
limited by perturbations in the
LED on current, as it is for the
recommended drive circuit
(Figure 15), pins 1 and 4 should
be connected to the input circuit
common. However, if CMR
performance is limited by direct
coupling to the output when the
LED is off, pins 1 and 4 should be
left unconnected.
CMR with the LED Off
(CMRH)
A high CMR LED drive circuit
must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a +dVcm/dt transient in
Figure 20, the current flowing
through CLEDN is supplied by the
parallel combination of the LED
and series resistor. As long as the
voltage developed across the
resistor is less than VF(OFF) the
18
LED will remain off and no
common mode failure will occur.
Even if the LED momentarily
turns on, the 100 pF capacitor
from pins 6-5 will keep the output
from dipping below the threshold.
The recommended LED drive
circuit (Figure 15) provides about
10 V of margin between the
lowest optocoupler output voltage
and a 3 V IPM threshold during
a 15 kV/µs transient with
VCM = 1500 V. Additional margin
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line connection in Figure 20, to clamp
the voltage across the LED
below VF(OFF).
Since the open collector drive
circuit, shown in Figure 21,
cannot keep the LED off during
a +dVcm/dt transient, it is
not desirable for applications
requiring ultra high CMRH
performance. Figure 22 is the AC
equivalent circuit for Figure 21
during common mode transients.
Essentially all the current flowing
through CLEDN during a +dVcm/dt
transient must be supplied by
the LED. CMRH failures can occur
at dV/dt rates where the current
through the LED and CLEDN
exceeds the input threshold.
Figure 23 is an alternative drive
circuit which does achieve ultra
high CMR performance by
shunting the LED in the off state.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-4506 series include
a Propagation Delay Difference
specification intended to help
designers minimize “dead time”
in their power inverter designs.
Dead time is the time period
during which both the high and
low side power transistors (Q1
and Q2 in Figure 24) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flowing through the power devices
between the high and low voltage
motor rails.
To minimize dead time the
designer must consider the propagation delay characteristics of the
optocoupler as well as the characteristics of the IPM IGBT gate
drive circuit. Considering only the
delay characteristics of the optocoupler (the characteristics of the
IPM IGBT gate drive circuit can
be analyzed in the same way) it is
important to know the minimum
and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay
specifications, preferably over the
desired operating temperature
range.
The limiting case of zero dead
time occurs when the input to Q1
turns off at the same time that the
input to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propagation delay waveforms, as shown in
Figure 25. A minimum dead time
of zero is achieved in Figure 25
when the signal to turn on LED2
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is delayed by (tPLH max - tPHL min)
from the LED1 turn off. Note that
the propagation delays used to
calculate PDD are taken at equal
temperatures since the optocouplers under consideration
are typically mounted in close
proximity to each other.
(Specifically, tPLH max and tPHL min
in the previous equation are not
the same as the tPLH max and
tPHL min, over the full operating
temperature range, specified in
the data sheet.) This delay is the
maximum value for the propagation delay difference specification
which is specified at 450 ns for
the HCPL-4506 series over an
operating temperature range of
-40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay difference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one optocoupler with the fastest tPLH and
another with the slowest tPHL
are in the same inverter leg. The
maximum dead time in this case
becomes the sum of the spread
in the tPLH and tPHL propagation
delays as shown in Figure 26.
The maximum dead time is also
equivalent to the difference
between the maximum and minimum propagation delay difference
specifications. The maximum
dead time (due to the optocouplers) for the HCPL-4506 series
is 600 ns (= 450 ns - (-150 ns) )
over an operating temperature
range of -40°C to 100°C.
19
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www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5965-6168E
5968-1089E (11/99)
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