HD74HC4518, HD74HC4520 Dual BCD Up Counters Dual Binary Up Counters REJ03D0653–0200 (Previous ADE-205-542) Rev.2.00 Mar 30, 2006 Description The HD74HC4518 dual BCD counter and the HD74HC4520 dual binary counter consist of two identical, independent, internally synchronous 4-stage counters. The counter stages are type D flip-flops, with interchangeable Clock and Enable lines for incrementing on either the positive-going or negative-going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the HD74HC4518 will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi-stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. Features • • • • • • High Speed Operation High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name HD74HC4518P HD74HC4520P HD74HC4518FPEL HD74HC4520FPEL Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Type DILP-16 pin PRSP0016DH-B (FP-16DAV) SOP-16 pin (JEITA) Package Abbreviation P — FP EL (2,000 pcs/reel) PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. HD74HC4520RPEL Taping Abbreviation (Quantity) SOP-16 pin (JEDEC) EL (2,000 pcs/reel) Function Table Clock Enable H L X X L H X Notes: 1. X: Don’t care Rev.2.00, Mar 30, 2006 page 1 of 8 X Reset L L L L L L H Operation Increment counter Increment counter No change No change No change No change Q0 to Q3 = L HD74HC4518, HD74HC4520 Pin Arrangement Clock A 1 16 VCC Enable A 2 15 Reset B Q0 A 3 C Q0 Q1 A 4 Q2 A R Q3 14 Q3 B Q1 Q2 13 Q2 B 5 Q2 Q1 12 Q1 B Q3 A 6 Q3 R Q0 C 11 Q0 B Reset A 7 10 Enable B GND 8 9 Clock B (Top view) Block Diagram HD74HC4518 Q1 Q0 D C R Reset Enable Clock Rev.2.00, Mar 30, 2006 page 2 of 8 Q D Q C R Q2 Q D Q C R Q3 Q D Q C Q Q R HD74HC4518, HD74HC4520 HD74HC4520 Q1 Q0 D C Q D Q C Q2 Q D Q C R R Q3 Q D Q C R Q Q R Reset Enable Clock Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 Clock Enable Reset 0 1 2 3 4 5 0 Q0 Q1 HD74HC4518 Q2 Q3 Q0 Q1 HD74HC4520 Q2 Q3 Rev.2.00, Mar 30, 2006 page 3 of 8 HD74HC4518, HD74HC4520 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Input current Quiescent supply current Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 VIL 4.5 6.0 VOH 2.0 4.5 6.0 4.5 6.0 2.0 VOL 4.5 6.0 4.5 6.0 Iin 6.0 6.0 ICC Rev.2.00, Mar 30, 2006 page 4 of 8 Min 1.5 3.15 4.2 — — — 1.9 4.4 5.9 4.18 5.68 — — — — — — — Ta = 25°C Typ Max — — — — — — — 0.5 — 1.35 — 1.8 2.0 — 4.5 — 6.0 — — — — — 0.0 0.1 0.0 0.1 0.0 0.1 — 0.26 — 0.26 — ±0.1 — 4.0 Ta = –40 to+85°C Min Max 1.5 — 3.15 — 4.2 — — 0.5 — 1.35 — 1.8 1.9 — 4.4 — 5.9 — 4.13 — 5.63 — — 0.1 — 0.1 — 0.1 — 0.33 — 0.33 — ±1.0 — 40 Unit V Test Conditions V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA IOL = 20 µA V Vin = VIH or VIL µA µA IOH = 4 mA IOH = 5.2 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA HD74HC4518, HD74HC4520 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) tPLH tPHL tPLH tPHL 6.0 2.0 4.5 — — — — — 22 32 200 40 — — — tPLH tPHL 6.0 2.0 4.5 — — — — — 17 34 190 38 6.0 2.0 4.5 6.0 2.0 — 80 16 14 0 — — 7 — — 4.5 6.0 0 0 tTLH tTHL 2.0 4.5 Cin 6.0 — fmax Propagation delay time tw Removal time trem Output rise/fall time Input capacitance Ta = –40 to +85°C Min Max — 4 — 21 — 25 — 240 — 48 2.0 4.5 6.0 2.0 4.5 Maximum clock frequency Pulse width Ta = 25°C Typ Max — 5 — 27 — 32 — 190 22 38 Min — — — — — Unit Test Conditions MHz ns Clock to Q 41 250 50 ns Reset to Q — — — 43 240 48 ns Enable to Q 32 — — — — — 100 20 17 0 41 — — — — –3 — — — 0 0 — — — — — — 75 15 — — 95 19 — — — 5 13 10 — — 16 10 ns ns Reset clock ns pF Test Circuit VCC VCC Input Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω See Function Table Output Clock Q0 Output Enable CL = 50 pF Q3 Reset CL = 50 pF Note : 1. CL includes probe and jig capacitance. Rev.2.00, Mar 30, 2006 page 5 of 8 HD74HC4518, HD74HC4520 Waveforms • Waveform – 1 tr tf 90% 50% Reset VCC 90% 50% 10% 10% tw 0V trem 90% 50% Clock VOH 90% 10% 10% tTHL tTLH tPHL VOH 90% 90% 50% 10% Qn VOL 10% tTHL VOL tTLH Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 2 tr tf VCC Clock 50% 50% 50% 0V tw tPLH tPHL 90% Qn VOH 90% 50% 10% 50% 10% VOL tTHL tTLH Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 3 tf Enable tr 90% 50% 90% 50% VCC 50% 10% 10% 0V tw tPLH tPHL 90% Qn 50% 10% tTLH VOH 90% 50% 10% tTHL Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00, Mar 30, 2006 page 6 of 8 VOL HD74HC4518, HD74HC4520 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 9 E 16 1 8 b3 0.89 A1 A Z L Reference Symbol θ bp e e1 D E A A1 bp b3 c θ e Z L c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV Dimension in Millimeters Min Nom Max 7.62 19.2 20.32 6.3 7.4 5.06 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.12 2.54 MASS[Typ.] 0.15g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c *2 Index mark HE E bp Terminal cross section ( Ni/Pd/Au plating ) 1 Z Reference Dimension in Millimeters Symbol 8 e *3 bp x M A L1 A1 θ L y Detail F Rev.2.00, Mar 30, 2006 page 7 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 9.90 10.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08 HD74HC4518, HD74HC4520 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.2.00, Mar 30, 2006 page 8 of 8 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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