IDT ICS8535AGI-31T

ICS8535I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO3.3V LVPECL FANOUT BUFFER
General Description
Features
The ICS8535I-31 is a low skew, high performance
1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
HiPerClockS™
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8535I-31 has selectable
single ended clock or crystal inputs. The single ended clock input
accepts LVCMOS or LVTTL input levels and translate them to 3.3V
LVPECL levels. The output enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
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ICS
Guaranteed output and part-to-part skew characteristics make the
ICS8535I-31 ideal for those applications demanding well defined
performance and repeatability.
Four differential 3.3V LVPECL outputs
Selectable LVCMOS/LVTTL CLK or crystal inputs
CLK can accept the following input levels: LVCMOS, LVTTL
Maximum output frequency: 266MHz
Output skew: 30ps (typical)
Part-to-part skew: 200ps (maximum)
Propagation delay: 1.75ns (maximum)
Additive phase jitter, RMS: 0.057ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Replaces the ICS8535I-11
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_EN
Pullup
Pin Assignment
D
Q
CLK
Pulldown
LE
0
VEE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
Q0
nQ0
XTAL_IN
OSC
1
XTAL_OUT
CLK_SEL
Pulldown
Q1
nQ1
Q2
nQ2
nc
nc
Q3
nQ3
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
nQ3
ICS8535I-31
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VEE
Power
2
CLK_EN
Input
Pullup
3
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects XTAL inputs
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
4
CLK
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 8, 9
nc
Unused
6,
7
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
10, 13, 18
VCC
Power
Positive supply pins.
11, 12
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
No connect.
14, 15
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
16, 17
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
Test Conditions
2
Minimum
Typical
Maximum
Units
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
nQ0:nQ3
0
0
CLK0
Disabled; Low
Disabled; High
0
1
CLK1
Disabled; Low
Disabled; High
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as
shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Enabled
Disabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK
Q0:Q3
nQ0:nQ3
0
LOW
HIGH
1
HIGH
LOW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73,2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
65
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
CLK, CLK_SEL
VCC = VIN = 3.465V
150
µA
CLK_EN
VCC = VIN = 3.465V
5
µA
CLK, CLK_SEL
VCC = 3.465V, VIN = 0V
-5
µA
CLK_EN
VCC = 3.465V, VIN = 0V
-150
µA
IDT™ / ICS™3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCC – 1.4
VCC – 0.9
V
VCC – 2.0
VCC – 1.7
V
0.6
1.0
V
Maximum
Units
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE 1: Outputs terminated with 50Ω to VCC – 2V
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
12
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = 3.3V ± 5%, TA = 0°C to 70°C
Parameter Symbol
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
1.4
155.52MHz, Integration Range:
12kHz – 20MHz
20% to 80%
Maximum
Units
266
MHz
1.75
ns
0.057
ps
30
ps
200
ps
300
600
ps
46
54
%
All parameters measured at ƒ ≤ 266MHz unless noted otherwise.
NOTE 1: Measured from VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crossing point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.057ps (typical)
-20
-30
-40
SSB Phase Noise dBc/Hz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
IDT™ / ICS™3.3V LVPECL FANOUT BUFFER
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
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Parameter Measurement Information
2V
,
,
,
VCC
Qx
SCOPE
VCC
CLK
2
nQ0:nQ3
LVPECL
Q0:Q3
nQx
tPD
VEE
1.3V ± 0.165V
Propagation Delay
3.3V Core/3.3V Output Load AC Test Circuit
nQx
nQ0:nQ3
Qx
Q0:Q3
t PW
t
nQy
Qy
odc =
tsk(o)
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Output Skew
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
Output Rise/Fall Time
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kW resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Crystal Input Interface
The ICS8535I-31 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
These same capacitor values will tune any 18pF parallel resonant
crystal over the frequency range and other parameters specified in
this data sheet. The optimum C1 and C2 values can be slightly
adjusted for different board layouts
.
XTAL_IN
C1
X1
18pF Parallel Crystal
XTAL_OUT
C2
Figure 2. Crystal Input Interface
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LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VCC
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
R1
Ro
0.1µf
50Ω
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
Figure 4A. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
FIN
50Ω
84Ω
Figure 4B. 3.3V LVPECL Output Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8535I-31.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8535I-31 is the sum of the core power plus the power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 65mA = 225.2mW
•
Power (outputs)MAX = 30mW/Loaded Output Pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 225.2mW + 120mW = 345.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per meter and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.345W * 66.6°C/W = 108°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™3.3V LVPECL FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V - (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Reliability Information
Table 8. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Linear Feet per minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8535I-31 is: 428
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 9. Package Dimensions 20 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 10. Ordering Information
Part/Order Number
ICS8535AGI-31
ICS8535AGI-31T
ICS8535AGI-31LF
ICS8535AGI-31LFT
Marking
ICS8535AGI31
ICS8535AGI31
ICS8535AI31L
ICS8535AI31L
Package
20 Lead TSSOP
20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Revision History Sheet
Rev
Table
Page
T10
8
9
13
A
Description of Change
Date
Added Recommendations for Unused Input and Output Pins.
Added LVCMOS-to-Crystal Interface section.
Ordering Information Table - added lead-free marking.
IDT™ / ICS™3.3V LVPECL FANOUT BUFFER
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