IS31AP4912 STEREO HEADPHONE DRIVER December 2011 GENERAL DESCRIPTION FEATURES The IS31AP4912 is stereo headphone drivers designed to allow the removal of the output DC-blocking capacitors for reduced component count and cost. The IS31AP4912 is ideal for small portable electronics where size and cost are critical design parameters. The IS31AP4912 integrates click-and-pop suppression circuitry and thermal protect circuit. The gain of the amplifier is adjusted via external resistors. IS31AP4912 is available in UTQFN-12 (2mm × 2mm) packages. It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C. No output DC-blocking capacitors Supply voltage from 2.7V ~ 5.5V Low output noise (7µV) High SNR (103dB) -95dB PSRR Thermal protect circuit Integrated click-and-pop suppression circuitry UTQFN-12 (2mm × 2mm) package APPLICATIONS Cellular handsets and PDAs Notebook PC MP3 Portable gaming TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Note: The SGND and PGND pins of the IS31AP4912 must be routed separately back to the decoupling capacitor in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 1 IS31AP4912 PIN CONFIGURATION Package Pin Configuration (Top View) UTQFN-12 CN 1 9 OUTR INR 2 8 VREF INL 3 7 VCC PIN DESCRIPTION No. Pin Description 1 CN Charge pump flying capacitor negative terminal. 2 INR Right channel audio input. 3 INL Left channel audio input. 4 OUTL Left channel audio output. 5 SDB Shutdown control terminal, active low. 6 SGND Signal Ground. 7 VCC Supply voltage. 8 VREF Internal produced supply voltage for charge pump and audio power amplifier. 9 OUTR Right channel audio output. 10 CP Charge pump flying capacitor positive terminal. 11 PGND Power ground. 12 VSS Output from charge pump. Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 2 IS31AP4912 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31AP4912-UTLS2-TR UTQFN-12, Lead-free 3000 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 3 IS31AP4912 ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA -0.3V ~ +6.0V -0.3V ~ VDD+0.3V 150°C -65°C ~ +150°C −40°C ~ +85°C Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VCC = 2.7V ~ 5.5V, TA = 25°C, unless otherwise noted. Typical value is TA = 25°C, VCC = 3.6V. Symbol Parameter Condition VCC Supply voltage ICC Quiescent current No load ISD Shutdown current VSDB = 0V Min. Typ. 2.7 FOSC Operating frequency |VOS| Output offset voltage VIH High-level input voltage VIL Low-level input voltage 3 V(IN) = 0V Max. Unit 5.5 V 5 mA 1 µA 250 kHz 1 mV 1.4 V 0.4 V Max. Unit ELECTRICAL CHARACTERISTICS (NOTE 1) TA = 25°C, VCC = 3.6V, unless otherwise noted. Symbol PO THD+N tWU Parameter Condition Output power THD+N = 1%，RL = 32Ω，f = 1kHz Total harmonic plus noise Wake-up shutdown distortion time VNO Output voltage noise SNR Signal-to-noise ratio Typ. 30 mW 0.024 % 39 ms VP-P = 200mV，RL = 32Ω，f = 217Hz -95 dB VP-P = 200mV，RL = 32Ω，f = 1kHz -93 dB 7 µV 103 dB PO = 20mW，RL = 32Ω，f = 1kHz from PSRR Power supply rejection ratio Min. PO = 30mW，THD+N = 0.1% Note 1: Guaranteed by design. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 4 IS31AP4912 TYPICAL PERFORMANCE CHARACTERISTIC 20 20 10 5 VCC = 3.0V RL = 32Ω 10 5 2 1 THD+N(%) THD+N(%) 2 f = 20Hz 0.5 0.2 1 0.5 f = 20Hz 0.2 0.1 0.1 0.05 0.05 f = 10kHz 0.02 0.01 1m VCC = 3.6V RL = 32Ω 0.02 f = 1kHz 2m 5m 10m 20m f = 10kHz 0.01 1m 100m 50m f = 1kHz 2m 5m THD+N vs. Output Power Figure 3 20 10 5 VCC = 4.2V RL = 32Ω 0.5 0.2 THD+N(%) THD+N(%) 1 0.5 0.2 f = 20Hz THD+N vs. Output Power VCC = 3.0V~4.2V RL = 32Ω PO = 20mW 0.1 0.05 0.02 0.01 0.1 0.005 f = 10kHz 0.05 0.002 0.02 f = 1kHz 2m 5m 10m 20m 0.001 20 100m 50m 50 100 200 Figure 4 500 1k 2k 5k 10k 20k 5k 10k Frequency(Hz) Output Power(W) THD+N vs. Output Power Figure 5 THD+N vs. Frequency +0 20u VCC = 3.0V~4.2V RL = 32Ω -20 10u VCC = 3.6V, 4.2V RL = 32Ω Input Grounded -40 7u PSRR(dB) Output Voltage(V) 100m 50m 1 2 0.01 1m 20m Output Power(W) Output Power(W) Figure 2 10m 5u 3u -60 -80 2u -100 1u 20 50 100 200 500 1k 2k 5k 10k 20k -120 20 50 100 Noise Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 500 1k 2k 20k Frequency(Hz) Frequency(Hz) Figure 6 200 Figure 7 PSRR vs. Frequency 5 IS31AP4912 APPLICATION INFORMATION CHARGE PUMP CONVERTER IS31AP4912 integrate a charge pump converter to change input supply voltage (VCC) into a negative voltage providing a 0V reference voltage for output. The charge pump converter only needs three external components: supply decoupling capacitor, output bypass capacitor and flying capacitor. Choose low ESR capacitors to ensure the best operating performance and place the capacitors as close as possible to the IS31AP4912. GAIN SETTING The input resistors (RIN) and feedback resistors (RF) set the gain of the amplifier according to Equation (1). R V Gain F R IN V (1) For example, in figure 1: RF = 20kΩ, RIN = 20kΩ, so, Gain 20 V 1 20 V Resistor matching is very important in the amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with 1% matching can be used with a tolerance greater than 1%. Place the input resistors very close to the IS31AP4912 to limit noise injection on the high-impedance nodes. The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. The capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. DESIGN NOTE COMPONENT SELECTION The value and ESR of the output capacitor for charge pump will affect output ripple and transient performance. A X7R or X5R ceramic capacitor in 2.2μF should be recommended. The flying capacitor should use a 2.2µF X7R or X5R ceramic capacitor. All the capacitors should support at least 10V. PCB LAYOUT The decoupling capacitors should be placed close to the VCC pin and the output capacitors should be placed close to the VSS pin. The flying capacitor should be placed close to the CN and CP pins. The input capacitors and input resistors should be placed close to the INR and INL pins and the traces must be parallel to prevent noise. The traces of OUTR and OUTL pins connected to the headphone should be as possible as short and wide. The recommended width is 0.5mm. Trace width should be at least 0.75mm for the power supply and the ground plane. The SGND and PGND pins of the IS31AP4912 must be routed separately back to the decoupling capacitor in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications. INPUT CAPACITOR (CIN) The input capacitors and input resistors form a high pass filter with the corner frequency, fC, determined in Equation (2). 1 f c 2R C IN IN (2) For example, in figure 1: RIN = 20kΩ, CIN = 0.47µF, so, 1 f 17 Hz c 2 20 k 0 .47 F Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 6 IS31AP4912 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature Figure 8 8 minutes max. Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 7 IS31AP4912 TAPE AND REEL INFORMATION Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 8 IS31AP4912 PACKAGING INFORMATION UTQFN-12 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 11/17/2011 9