TI ISO7420FCCDR

ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
Low-Power Dual Channel Digital Isolator
Check for Samples: ISO7420FCC
FEATURES
1
•
•
•
•
2
•
•
•
•
•
•
•
•
•
Signaling Rate: 50 Mbps (5V Supplies)
Output is Low in Default Mode
Integrated Noise Filter on the Input pins
Low Power Consumption: Typical ICC per
Channel
– 1.8 mA at 1 Mbps, 3.9 mA at 25 Mbps (5V
Supplies)
– 1.4 mA at 1 Mbps, 2.6 mA at 25 Mbps (3.3V
Supplies)
Low Propagation Delay: 20 ns Typical (5V
Supplies)
Channel-to-Channel Output Skew: 2ns
Maximum
3.3 V / 5 V Level Translation
Wide TA Range Specified: –40°C to 125°C
60 KV/μs Transient Immunity, Typical (5V
Supplies)
Low Emissions
Isolation Barrier Life: > 25 Years
Operates from 2.7V to 5.5V Supply Levels
Narrow Body SOIC-8 Package
APPLICATIONS
•
SAFETY AND REGULATORY
APPROVALS
•
•
•
•
•
3 KVRMS / 4242 VPK Isolation per DIN EN 607475-2 (VDE 0884 Part 2)
2.5 KVRMS Isolation for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 60950-1 and IEC 61010-1 End Equipment
Standards
All Agencies Approvals Pending
DESCRIPTION
ISO7420FCC provides galvanic isolation up to 2500
VRMS for 1 minute per UL and 4242 VPK per VDE.
This device has two isolated channels. Each channel
has a logic input and output buffer separated by a
silicon dioxide (SiO2) insulation barrier. Used in
conjunction with isolated power supplies,this device
prevents noise currents on a data bus or other circuit
from entering the local ground and interfering with or
damaging sensitive circuitry. The suffix F indicates
low-output option in fail-safe conditions (see Table 1).
This device has integrated noise filter for harsh
environments where short noise pulses may be
present at the device input pins.
These devices have TTL input thresholds and
operate from 2.7V to 5.5V supplies. All inputs are 5V
tolerant when supplied from a 2.7V or 3.3V supply.
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN DESCRIPTIONS
PIN
NAME
I/O
ISO7420FCC
DESCRIPTION
INA
2
I
Input, channel A
INB
3
I
Input, channel B
GND1
4
–
Ground connection for VCC1
GND2
5
–
Ground connection for VCC2
OUTA
7
O
Output, channel A
OUTB
6
O
Output, channel B
VCC1
1
–
Power supply, VCC1
VCC2
8
–
Power supply, VCC2
Table 1. FUNCTION TABLE
INPUT SIDE
VCC
OUTPUT SIDE
VCC
PU
(1)
PU
INPUT
INA, INB
OUTPUT
OUTA, OUTB
H
H
L
L
Open
L (1)
PD
PU
X
L (1)
X
PD
X
Undetermined
In fail-safe condition, output defaults to low level
AVAILABLE OPTIONS
PRODUCT
DATA
RATE
DEFAULT
OUTPUT
INTEGRATED
NOISE FILTER
RATED TA
CHANNEL
DIRECTION
MARKED
AS
ISO7420FCC
50 Mbps
Low
Yes
–40°C to
125°C
Same
7420FC
ORDERING
NUMBER
ISO7420FCCD (rail)
ISO7420FCCDR
(reel)
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
VCC1 ,
VCC2
Supply voltage (2)
–0.5 V to 6 V
VI
Voltage at INA, INB
–0.5 V to 6 V
VO
Voltage at OUTA, OUTB
IO
Output current
–0.5 V to VCC + 0.5 V
±15 mA
Human-body model
ESD
Electrostatic discharge
Field-induced charged-device
model
TJ(Max)
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
2
JEDEC Standard 22, Test Method
A114-C.01
JEDEC Standard 22, Test Method
C101
±4 kV
All
pins
±1.5 kV
150°C
-65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
RECOMMENDED OPERATING CONDITIONS
MIN
VCC1, VCC2
IOH
TYP
MAX
UNIT
Supply voltage
2.7
5.5
High-level output current (Vcc ≥ 3.0V)
–4
mA
V
High-level output current (Vcc < 3.0V)
-2
mA
IOL
Low-level output current
VIH
High-level input voltage
2
VCC
4
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration
1 / tui
Signaling rate
≥4.5V-Operation
20
<4.5V-Operation
25
≥4.5V-Operation
0
<4.5V-Operation
TJ
TA
(1)
(1)
mA
ns
50
Mbps
0
40
Junction temperature
–40
136
°C
Ambient temperature
-40
125
°C
25
To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
3
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 = 5V ± 10%, TA = -40°C to 125°C
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 1.
TEST CONDITIONS
VCC2 – 0.5
4.8
IOH = –20 μA; see Figure 1.
VCC2 – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC
IIL
Low-level input current
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 3.
MAX
V
IOL = 4 mA; see Figure 1.
0.2
0.4
IOL = 20 μA; see Figure 1.
0
0.1
450
V
mV
10
μA
μA
–10
25
UNIT
60
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
0.5
1.1
3
4.6
1
1.5
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15pF
50 Mbps
ICC2
4
6
1.7
2.5
6
8.5
2.7
4
8.5
12
mA
SWITCHING CHARACTERISTICS
VCC1 and VCC2 = 5V ± 10%, TA = -40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 1.
tf
Output signal fall time
tGS
Pulse width of glitches suppressed by the input filter
tfs
Fail-safe output delay time from input data or power loss
4
MAX
20
37
ns
2.5
5
ns
2
ns
12
ns
Part-to-part skew time
Output signal rise time
(3)
TYP
10
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 1.
See Figure 2.
UNIT
2.5
ns
2.5
ns
12
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 = 3.3 V ± 10%, TA = -40°C to 125°C
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 1.
TEST CONDITIONS
VCC2 – 0.5
3
IOH = –20 μA; see Figure 1.
VCC2 – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC
IIL
Low-level input curre
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 3.
MAX
UNIT
V
IOL = 4 mA; see Figure 1.
0.2
0.4
IOL = 20 μA; see Figure 1.
0
0.1
425
V
mV
10
μA
μA
-10
25
40
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15pF
40 Mbps
ICC2
0.3
0.8
2.4
3.3
0.6
1.2
3.1
4.5
1
2
4.2
6.1
1.3
2.3
5.3
7.5
mA
SWITCHING CHARACTERISTICS
VCC1 and VCC2 = 3.3 V ± 10%, TA = -40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 1.
MAX
22
40
ns
3
ns
2
ns
19
ns
Part-to-part skew time
Output signal rise time
tf
Output signal fall time
tGS
Pulse width of glithes suppressed by the input filter
tfs
Fail-safe output delay time from input power loss
(3)
TYP
10
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 1.
See Figure 2.
UNIT
3
ns
3
ns
12.5
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
5
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 = 2.7 V, TA = -40°C to 125°C
PARAMETER
MIN
TYP
IOH = –2 mA; see Figure 1.
TEST CONDITIONS
VCC2 – 0.3
2.5
IOH = –20 μA; see Figure 1.
VCC2 – 0.1
2.7
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC
IIL
Low-level input current
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 3.
MAX
UNIT
V
IOL = 4 mA; see Figure 1.
0.2
0.4
IOL = 20 μA; see Figure 1.
0
0.1
350
V
mV
10
μA
μA
–10
25
35
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15pF
40 Mbps
ICC2
0.15
0.4
2.1
3.1
0.4
0.7
2.7
4
0.7
1.2
3.6
5
1
1.7
4.4
6.3
mA
SWITCHING CHARACTERISTICS
VCC1 and VCC2 = 2.7 V, TA = -40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 1.
tf
Output signal fall time
tGS
Pulse width of glitches suppressed by the input filter
tfs
Fail-safe output delay time from input power loss
6
MAX
26
45
ns
3
ns
2
ns
22
ns
Part-to-part skew time
Output signal rise time
(3)
TYP
15
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 1.
See Figure 2.
UNIT
3
ns
3
ns
13.5
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
Isolation Barrier
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
(1)
VI
50 W
VCC1
VI
OUT
VO
1.4 V
1.4 V
0V
CL
tPLH
(2)
tPHL
90%
10%
VCC/2
VO
VCC/2
VOH
VOL
tr
tf
S0412-01
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC
ISOLATION BARRIER
VCC
IN = VCC
A.
2.7 V
VI
0V
OUT
t fs
VO
CL
NOTE A
VOH
50%
VO
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
C = 0.1 μ F ±1%
Isolation Barrier
VCC1
IN
GND1
VCC2
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
(1)
CL
GND2
VOH or VOL
–
+ VCM –
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
7
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
DEVICE INFORMATION
IEC Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN IEC 60112 / VDE 0303 Part 1
>400
V
Minimum internal gap (internal
clearance)
Distance through the insulation
0.014
mm
RIO
Isolation resistance, input to
output (1)
CIO
Barrier capacitance, input to
output (1)
CI
Input capacitance (2)
(1)
(2)
>1012
Ω
11
Ω
VIO = 0.4 sin (2πft), f = 1 MHz
1
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1
pF
VIO = 500 V, TA < 100°C
VIO = 500 V, 100°C ≤ TA ≤ max
>10
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
INSULATION CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
VIORM
TEST CONDITIONS
Maximum working insulation voltage
Input-to-output test voltage per DIN EN
60747-5-2
VPR
VIOTM
Transient overvoltage per DIN EN 607475-2
VISO
Isolation voltage per UL 1577
RS
Insulation resistance
8
UNIT
566
VPEAK
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VTEST = VISO, t = 60 sec (qualification)
2500
VTEST = 1.2 x VISO, t = 1 sec (100% production)
3000
VIO = 500 V at TS
>109
Pollution degree
(1)
SPECIFICATION
VPEAK
VPEAK
VRMS
Ω
2
Climatic Classification 40/125/21
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
Table 2. IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
Rated mains voltage ≤ 400 VRMS
I–II
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2)
Approved under CSA Component Acceptance Notice
#5A
Recognized under UL 1577
Component Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4242 VPK
Maximum Working Voltage, 566 VPK
Basic and Reinforced Insulation per CSA 60950-1 and
IEC 60950-1
Reinforced Insulation per CSA 61010-1 and IEC
61010-1
Single / Basic Isolation Voltage,
2500 VRMS (1)
File number: 40016131 (Approval pending)
File number: 220991 (Approval pending)
File number: E181974 (Approval
pending)
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
9
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Maximum case temperature
MIN
TYP
MAX
θJA = 115.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
197
θJA = 115.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
302
θJA = 115.1°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C
402
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
PACKAGE THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
ISO7420
THERMAL METRIC (1)
D PACKAGE
UNITS
(8) PINS
θJA
Junction-to-ambient thermal resistance
115.1
θJCtop
Junction-to-case (top) thermal resistance
60.1
θJB
Junction-to-board thermal resistance
56.4
ψJT
Junction-to-top characterization parameter
17.2
ψJB
Junction-to-board characterization parameter
55.8
θJCbot
Junction-to-case (bottom) thermal resistance
PD
(1)
N/A
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-Mbps 50% duty-cycle square wave
Device power dissipation
°C/W
120
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
450
Safety Limiting Current (mA)
400
VCC1 = VCC2 = 2.7 V
350
300
VCC1 = VCC2 = 3.6 V
250
200
VCC1 = VCC2 = 5.5 V
150
100
50
0
0
50
100
150
Case Temparature (ƒC)
200
C000
Figure 4. θJC Thermal Derating Curve per DIN EN 60747-5-2
10
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
APPLICATION INFORMATION
Figure 5. Typical ISO7420FCC Application Circuit
Note: For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
SUPPLY CURRENT EQUATIONS
Maximum Supply Current Equations
(Calculated over recommended operating temperature range and Silicon process variation)
At VCC1 = VCC2 = 5V ±10%
ICC1(max) = 1.1 + 5.80E-02 × f
ICC2(max) = 4.6 + 6.55E-02 × f + 5.5E-03 × f × CL
At VCC1 = VCC2 = 3.3V ± 10%
ICC1(max) = 0.8 + 3.40E-02 × f
ICC2(max) = 3.3 + 4.60E-02 × f + 3.6E-03 × f × CL
At VCC1 = VCC2 = 2.7V
ICC1(max) = 0.4 + 3.20E-02 × f
ICC2(max) = 3.1 + 3.75E-02 × f + 2.7E-03 × f × CL
f is data rate of each channel measured in Mbps; CL is the capacitive load of each channel measured in pF;
ICC1(max) and ICC2(max) are measured in mA.
Typical Supply Current Equations
(Calculated for TA = 25°C and nominal Silicon process material)
At VCC1 = VCC2 = 5V
ICC1(typ) = 0.5 + 4.40E-02 × f
ICC2(typ) = 3 + 3.50E-02 × f + 5.0E-03 × f × CL
At VCC1 = VCC2 = 3.3V
ICC1(typ) = 0.3 + 2.60E-02 × f
ICC2(typ) = 2.4 + 2.25E-02 × f + 3.3E-03 × f × CL
At VCC1 = VCC2 = 2.7V
ICC1(typ) = 0.15 + 2.10E-02 × f
ICC2(typ) = 2.1 + 1.75E-02 × f + 2.7E-03 × f × CL
f is Data Rate of each channel measured in Mbps; CL is the Capacitive Load of each channel measured in pF;
ICC1(typ) and ICC2(typ) are measured in mA.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
11
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
ISO7420FCC Input
Output
VCC2
VCC1
VCC1
8Q
500Q
OUT
IN
13Q
7.5 uA
Figure 6. Device I/O Schematics
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
TYPICAL CHARACTERISTICS
SUPPLY CURRENT PER CHANNEL
vs
DATA RATE
5
ICC1
3.3VV
ICC1 atat3.3
ICC2
3.3VV
ICC2 atat3.3
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
Supply Current (mA)
4
3.5
10
TA = 25 °C
CL = 15 pF
ICC1
3.3VV
ICC1 atat3.3
ICC2
3.3VV
ICC2 atat3.3
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
8
Supply Current (mA)
4.5
SUPPLY CURRENT FOR BOTH CHANNELS
vs
DATA RATE
3
2.5
2
1.5
TA = 25 °C
CL = 15 pF
6
4
1
2
0.5
0
0
0
10
20
30
40
50
Data Rate (Mbps)
0
40
Figure 8.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25 °C
VCC
3.3VV
V
CC atat3.3
5
4
3
2
VCC
3.3VV
VCC atat3.3
1
50
C002
Figure 7.
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
30
1
V
VCC
CC atat55VV
0.8
0.6
0.4
0.2
VCC atat55VV
VCC
TA = 25 °C
–15
0
–10
0
0
–5
High-Level Output Current (mA)
5
10
15
Low-Level Output Current (mA)
C003
C004
Figure 9.
Figure 10.
VCC1 and VCC2 UNDER-VOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
27
2.5
VCC
Rising
V
CC Rising
2.48
VCC
Falling
V
CC Falling
Propagation Delay Time (ns)
Power Supply Under Voltage Threshold (V)
20
Data Rate (Mbps)
6
0
10
C001
2.46
2.44
2.42
2.4
2.38
2.36
25
23
21
19
17
ttpLH
3.3
3.3VV
pLH atat
ttpHL
3.3
3.3VV
pHL atat
ttpLH
5 5VV
pLH atat
ttpHL
5 5VV
pHL atat
15
13
2.34
±50
0
50
100
Free-Air Temperature (ƒC)
150
±40
C005
Figure 11.
±5
30
65
100
Free-Air Temperature (ƒC)
135
C006
Figure 12.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
13
ISO7420FCC
SLLSED3A – JUNE 2013 – REVISED JULY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT JITTER
vs
DATA RATE
INPUT GLITCH SUPPRESSION TIME
vs
FREE-AIR TEMPERATURE
1.2
Input Glitch Rejection Time (ns)
18
Pk-Pk Output Jitter (ns)
1
0.8
0.6
0.4
0.2
Output Jitter at 3.3 V
Output Jitter at 5 V
TA = 25 °C
0
0
20
40
14
12
10
8
6
4
2.7VV
ttGR
GS atat2.7
ttGR
3.3VV
GS atat3.3
ttGR
GS atat5 5VV
2
0
60
Data Rate (Mbps)
16
±40
±15
10
35
60
85
110
Free-Air Temperature (ƒC)
C007
Figure 13.
Figure 14.
Figure 15. Eye Diagram at 50 Mbps, 5V at 25°C
Figure 16. Eye Diagram at 40 Mbps, 3.3V at 25°C
135
C008
Figure 17. Eye Diagram at 40 Mbps, 2.7V at 25°C
14
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
ISO7420FCC
www.ti.com
SLLSED3A – JUNE 2013 – REVISED JULY 2013
REVISION HISTORY
Changes from Original (June 2013) to Revision A
Page
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 ................................................................................... 4
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 and removed Note 1 .................................................. 5
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 and removed Note 1 .................................................. 6
•
Changed Figure 9 X axis values ......................................................................................................................................... 13
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :ISO7420FCC
15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ISO7420FCCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7420FC
ISO7420FCCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7420FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7420FCCDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7420FCCDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated