Ordering number : EN7637 Monolithic Linear IC LA75695VA For Use in TV/VTR Applications IF Signal Processing (VIF+SIF+SIF converter) Overview The LA75695VA is a NTSC Support VIF/SIF signal-processing IC that makes the minimum number of adjustments possible. The system is designed so that VCO adjustment makes AFT adjustment unnecessary, thus simplifying the adjustment steps in endproduct manufacturing. PLL detection is adopted in the FM detector, allowing the LA75695VA to support multichannel detection for the audio signal. In addition, it also incorporates a buzz canceller that suppresses Nyquist buzz for improved audio quality. Functions • VIF Block: VIF Amplifier, Buzz Canceller, PLL Detector, IF AGC, RF AGC, AFT, Equalizer Amplifier • 1st SIF Block: 1st SIF Amplifier, 1st SIF Detector • SIF Block: Limiter Amplifier, PLL-FM Detector Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Circuit voltage Circuit current Allowable power dissipation Symbol Conditions Ratings Unit VCC1 max 6 V VCC2 max 12 V VCC V V13, V17 I6 -3 mA I10 -10 mA I24 -2 mA 600 mW Pd max Ta ≤ 70°C, Mounted on a board. * Operating temperature Topr -20 to +75 °C Storage temperature Tstg -55 to +150 °C ∗ When mounted on a 114.3×76.1×1.6mm3, glass epoxy circuit board. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / 42606 MS OT B8-8172 No.7637-1/13 LA75695VA Recommended Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Operating voltage Symbol Conditions Ratings Unit VCC1 5 V VCC2 9 V VCC1 op 4.5 to 5.5 V VCC2 op 4.5 to 9.5 V Electrical Characteristics at Ta = 25°C, VCC1 = 5V, VCC2 = 9V, fp = 45.75MHz VIF Block Ratings Parameter Symbol Conditions min typ Unit max Circuit current 1 I5 35.7 42 48.3 mA Circuit current 2 I4 6.7 7.9 9.1 mA VCC2-0.5 VCC2 0 0.5 V 36 42 dBµV Maximum RF AGC voltage V14H Minimum RF AGC voltage V14L Input sensitivity AGC range Maximum allowable input No-signal video output voltage Sync. signal tip voltage Vi S1 = OFF 30 V GR 50 56 dB Vi max 95 100 dBµV V6 3.1 3.4 3.7 V V6 tip 0.8 1.1 1.3 V VO 1.7 2.0 2.3 Vp-p Black noise threshold voltage VBTH 0.5 0.8 1.1 V Black noise clamp voltage 2.4 Video output level VBCL 1.7 2.1 Video S/N S/N 48 52 dB C-S best IC-S 38 43 dB -3 -1.5 dB Frequency characteristics fC Differential gain DG 3 6.5 % Differential phase DP 3 5 °C No-signal AFT voltage V13 2.0 2.5 3.0 V Maximum AFT voltage V13H VCC2-1.0 VCC2-0.5 VCC2 V Minimum AFT voltage V13L 0 0.18 1.0 V Sf 17 25 34 mV/kHz AFT detection sensitivity 6MHz V VIF input resistance Ri 45.75MHz 1.5 VIF input capacitance Ci 45.75MHz 3 APC pull-in range (U) fpu APC pull-in range (L) AFT tolerance frequency 1 0.7 fpl ∆Fa1 kΩ pF 1.5 MHz -1.5 -0.9 -150 0 150 1.0 1.5 MHz kHz VCO1 maximum variable range (U) dfu VCO1 maximum variable range (L) dfl -1.5 -1 MHz VCO control sensitivity β 1.2 3.2 5.0 kHz/mV VS 25.0 28.5 31.5 % Synchronization ratio MHz 1st SIF Block Ratings Parameter Conversion gain 4.5MHz output level Symbol Conditions min typ Unit max VG 22 28 32 dB 160 mVrms SO 80 120 1st SIF maximum input Si max 50 100 1st SIF input resistance Ri (SIF) 41.25MHz 2 kΩ 1st SIF input capacitance Ci (SIF) 41.25MHz 3 pF mVrms No.7637-2/13 LA75695VA SIF Block Ratings Parameter Symbol Limiting sensitivity Conditions min Vi (lim) FM detector output voltage VO (FM) AM rejection ratio AMR Distortion THD SIF S/N 4.5MHz±25kHz * typ Unit max 48 52 58 dBµV 420 500 620 mVrms 50 60 0.3 S/N (FM) 63 dB 0.8 69 % dB * IF the dynamic range of the FM detection output needs to be widened, connect a resistor and a capacitor in series between pin 23 and GND for level adjustment. SIF Converter Ratings Parameter Symbol Maximum output level V max Conditions min 110 typ 116 max 122 Unit dBµV Package Dimensions unit : mm 3287 6.5 24 0.5 6.4 4.4 13 12 1 0.5 0.15 0.22 0.1 (1.3) 1.5max (0.5) SANYO : SSOP24(225mil) No.7637-3/13 LA75695VA Pin Assignment No.7637-4/13 LA75695VA Block Diagram and AC Characteristics Test Circuit No.7637-5/13 LA75695VA Input Impedance Test Circuit Test Conditions V1. Circuit current [I5] (1) Internal AGC (2) Input a 45.75MHz 10mVrms continuous wave to the VIF input pin. (3) RF AGC Vr MAX (4) Connect an ammeter to the VCC1 and measure the incoming current. V2. Circuit current [I4] (1) Internal AGC (2) Input a 45.75MHz 10mVrms continuous wave to the VIF input pin. (3) RF AGC Vr MAX (4) Connect an ammeter to the VCC2 and measure the incoming current. V3. V4. Maximum RF AGC voltage, Minimum RF AGC voltage [V14H, V14L] (1) Internal AGC (2) Input a 45.75MHz 10mVrms continuous wave to the VIF input pin. (3) Adjust the RF AGC Vr (resistor value max.) and measure the maximum RF AGC voltage. ····· F (4) Adjust the RF AGC Vr (resistor value min.) and measure the minimum RF AGC voltage. ····· F V5. Input sensitivity [Vi] (1) Internal AGC (2) fp = 45.75MHz 15kHz 78% AM (VIF input) (3) Turn off the S1 and put 100kΩ through. (4) VIF input level at which the 15kHz detection output level at test point A becomes VO -3dB. No.7637-6/13 LA75695VA V6. AGC range [GR] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) In the same manner as for the V5 (input sensitivity), measure the VIF input level at which the detection output level becomes Vo -3dB. ····· Vil (3) GR = Vil–Vi V7. Maximum allowable input [Vi max] (1) Internal AGC (2) fp = 45.75MHz 15kHz 78% AM (VIF input) (3) VIF input level at which the detection output level at test point A is video output (VO) ±1dB. V8. No-signal video output voltage [V6] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) Measure the DC voltage of VIDEO output (A). V9. Sync. signal tip voltage [V6tip] (1) Internal AGC (2) Input a 45.75MHz 10mVrms continuous wave to the VIF input pin. (3) Measure the DC voltage of VIDEO output (A). V10. Video output level [VO] (1) Internal AGC (2) fp = 45.75MHz 15kHz 78% AM Vi = 10mVrms (VIF input) (3) Measure the peak value of the detection output level at test point A. (Vp-p) V11.V12. Black noise threshold level and clamp voltage [VBTH, VBCL] (1) Apply DC voltage to the external AGC, IF AGC (pin 17) and adjust the voltage. (2) fp = 45.75MHz 400Hz 40% AM 10mVrms (VIF input) (3) Adjust the IF AGC (pin 17) voltage to operate the noise canceller. Measure the VBTH, VBCL at test point A. V13. Video S/N [S/N] (1) Internal AGC (2) fp = 45.75MHz CW = 10mVrms (VIF input) (3) Measure the noise voltage at test point A in RMS volts through a 10kHz to 4MHz band-pass filter. ····· Noise voltage (N) 1.12Vp-p Video portion (Vp-p) (4) S/N = 20log Noise voltage (Vrms) = 20log Noise voltage (Vrms) (dB) No.7637-7/13 LA75695VA V14. C/S beat [IC-S] (1) Apply DC voltage to the external AGC IF AGC (pin 17) and adjust the voltage. (2) fp = 45.75MHz CW; 10mVrms fc = 42.17MHz CW; 10mVrms – 10dB fs = 41.25MHz CW; 10mVrms – 10dB (3) Adjust the IF AGC (pin 17) voltage so that the output DC level at test point A becomes 2.4V. (4) Measure the difference between the levels for 3.58MHz and 0.92MHz components at test point A. V15. Frequency characteristics [fc] (1) Apply DC voltage to the external AGC IF AGC (pin 17) and adjust the voltage. (2) SG1 : 45.75MHz continuous wave 10mVrms SG2 : 45.65MHz to 39.75MHz continuous wave 2mVrms Add the SG1 and SG2 signals using a T pat and adjust each SG signal level so that the above-mentioned levels are reached and input the added signals to the VIF IN. (3) First set the SG2 frequency to 45.65MHz, and then adjust the IF AGC voltage (V17) so that the output level at test point A becomes 0.5Vp-p. ····· V1 (4) Set the SG2 frequency to 39.75MHz and measure the output level. ····· V2 (5) Calculate as follows : fc = 20log V2 (dB) V1 V16.V17. Differential gain, differential phase [DG, DP] (1) Internal AGC (2) fp = 45.75MHz APL50% 87.5% modulation video signal Vi = 10mVrms (3) Measure the DG and DP at test point A. V18. No-signal AFT voltage [V13] (1) Internal AGC (2) Measure the DC voltage at the AFT output (B). No.7637-8/13 LA75695VA V19.V20.V21. Maximum, minimum AFT output voltage, AFT detection sensitivity [V13H, V13L, Sf] (1) Internal AGC (2) fp = 45.75MHz ±1.5MHz Sweep = 10mVrms (VIF input) (3) Maximum voltage : V13H, minimum voltage : V13L. (4) Measure the frequency deviation at which the voltage at test point B changes from V1 to V2. ····· ∆f V22.V23. VIF input resistance, Input capacitance [Ri, Ci] (1) Referring to the Input Impedance Test Circuit, measure Ri and Ci with an impedance analyzer. V24.V25. APC pull-in range [fpu, fpl] (1) Internal AGC (2) fp = 39MHz to 51MHz continuous wave; 10mVrms (3) Adjust the SG signal frequency to be higher than fp = 45.75MHz to bring the PLL to unlocked state. Note : The PLL is assumed to be in unlocked state when a beat signal appears at test point A. (4) When the SG signal frequency is lowered, the PLL is brought to locked state again. ····· f1 (5) Lower the SG signal frequency to bring the PLL to unlock state. (6) When the SG signal frequency is raised, the PLL is brought to locked state again. ····· f2 (7) Calculate as follows : fpu = f1–45.75MHz fpl = f2–45.75MHz V26. AFT tolerance frequency 1 [dfa1] (1) Internal AGC (2) SG1 : 43.75MHz to 47.75MHz variable continuous wave 10mVrmns (3) Adjust the SG1 signal frequency so that the AFT output DC voltage (test point B) becomes 2.5V; that SG1 signal frequency is f1. (4) External AGC (Adjust the V17.) (5) Apply 5V to the IF AGC (pin 17) and then pick up the VCO oscillation frequency from GND, etc.; and measure the frequency ····· f2 (6) Calculate as follows : AFT tolerance frequency : dfa1 = f2–f1 (kHz) V27.V28. VCO maximum variable range (U, L) [dfu, dfl] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) Pick up the VCO oscillation frequency from the VIDEO output (A), GND, etc. and adjust the VCO coil so that the frequency becomes 45.75MHz. (3) fl is taken as the frequency when 1V is applied to the APC pin (pin 9). In the same manner, fu is taken as the frequency when 5V is applied to the APC pin (pin 9). dfu = fL–45.75MHz dfl = fL–45.75MHz No.7637-9/13 LA75695VA V29. VCO control sensitivity [β] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) Pick up the VCO oscillation frequency from the VIDEO output (A), GND, etc. and adjust the VCO coil so that the frequency becomes 45.75MHz. (4) f1 is taken as the frequency when 3.0V is applied to the APC pin (pin 9). In the same manner, f2 is taken as the frequency when 3.4V is applied to the APC pin (pin 9). β= f2–f1 400 (kHz/mV) V30. Synchronization ratio [VS] (1) Internal AGC (2) fp = 45.75MHz 87.5% 10STEP B/W Vi = 10mVrms (3) Measure the output amplitude at the measuring point A. ····· Vvideo (4) Measure the pedestal voltage (DC) at the measuring point A. ····· Vped VS = (Vped–V6tip) / Vvideo×100 (%) F1. 1st SIF conversion gain [VG] (1) Internal AGC (2) fp = 45.75MHz CW; 10mV (VIF input) fs = 41.25MHz CW; 500µV (1st SIF input) ····· V1 (3) Detection output level at test point C (Vrms) ····· V2 (4.5MHz) (4) VG = 20log V2 dB V1 F2. 4.5MHz output level [SO] (1) Internal AGC (2) fp = 45.75MHz CW; 10mV (VIF input) fs = 41.25MHz CW; 10mV (1st SIF input) ····· V1 (3) Detection output level at test point C (4.5MHz) ····· SO (mVrms) F3. 1st SIF maximum input [Si max] (1) Internal AGC (2) fp = 45.75MHz CW; 10mV (VIF input) fs = 41.25MHz CW; variable (1st SIF input) (3) Input level at which the detection output at test point C (4.5MHz) becomes SO ±2dB. ····· Si max F4.F5. 1st SIF input resistance, Input capacitance [Ri (SIF1), Ci (SIF1)] (1) Using an input analyzer, measure Ri and Ci in the input impedance measuring circuit. S1. SIF limiting sensitivity [Vi (lim)] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) fs = 4.5MHz fm = 400Hz ∆F = ±25kHz (SIF input) (3) Set the SIF input level to 100mVrms and then measure the level at test point D. ····· V1 (4) Lower the SIF input level until V1 -3dB occurs. Measure the input level at that moment. S2.S4. FM detection output voltage, distortion factor [VO (FM), THD] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) fs = 4.5MHz fm = 400Hz ∆F = ±25kHz (SIF input Vi = 100mVrms) (3) Assign the level at test point D to the FM detection output voltage and measure the distortion factor. S3. AM rejection ratio [AMR] (1) Apply the VCC voltage to the external AGC, IF AGC (pin 17). (2) fs = 4.5MHz fm = 400Hz AM = 30% (SIF input Vi = 100mVrms) (3) Measure the output level at test point D. ····· VAM (4) AMR = 20log VO (FM) dB VAM No.7637-10/13 LA75695VA S5. SIF S/N [S/N (FM)] (1) External AGC (V17 = VCC) (2) fs = 4.5MHz NO MOD Vi = 100mVrms (3) Measure the output level at test point D. ····· Vn (4) S/N (FM) = 20log VO (FM) dB Vn C2. SIF converter maximum output level [V max] (1) Internal AGC (2) fp = 45.75MHz CW; 10mV (VIF input) fs = 41.25MHz CW; 10mV (1st SIF input) (3) Measure the 4.5MHz component at test point E (MIX output). ····· V max (dBµV) Note 1) Unless otherwise specified for VIF test, apply the VCC voltage to the IF AGC and adjust the VCO coil so that oscillation occurs at 45.75MHz. 2) Unless otherwise specified, the SW1 must be ON. Sample Application Circuit * When using a 5V common power supply for VCC1 and VCC2, connect an L (= 10µH) across pins 4 to 5, and disconnect C (100µF and 0.01µF) from pin 4. No.7637-11/13 LA75695VA Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. 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Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2006. Specifications and information herein are subject to change without notice. PS No.7637-12/12