SANYO LC88F40F0PA

Ordering number : ENA1853A
LC88F40H0PA/PAU
LC88F40F0PA/PAU
LC88F40D0PA/PAU
CMOS LSI
For Car Audio Systems
16-bit ETR Microcontroller
(ALL FLASH)
Overview
The LC88F40H0PA/PAU, LC88F40F0PA/PAU and LC88F40D0PA/PAU are 16-bit microcontrollers which are
ideally suited as a system controller in car audio applications for the control of “MP3 and WMA and other compression
decoders through CD/USB,” “CD mechanisms and CD DSPs,” “displays,” and “DSP tuners.” They are configured
around a CPU that operates at a high speed, and incorporate an internal flash ROM (All Flash, onboard programmable)
and RAM. These 16-bit microcontrollers integrate on a single chip such principal functions as on-chip debugging,
16-bit timer/counter (may be divided into 8-bit timers/counters), synchronous SIO (also used as the I2C bus interface),
UART (full duplex), 12-bit PWM, 12-bit resolution (8-bit resolution selectable) × 13-channel A/D converter, and 16
vector interrupts.
Microcontroller model line-up (list of ROM and RAM sizes)
Type No.
Flash ROM (byte)
RAM (byte)
LC88F40H0PA/PAU
512K
30K
LC88F40F0PA/PAU
384K
20K
LC88F40D0PA/PAU
256K
12K
Features
■Power supply voltage
• Main power supply voltage (VDDCPU)
• I/O power supply (VDDPORT)
3.3V±0.3V
VDDCPU to 5.5V
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.1.23
D1510HKPC 20101005-S00001, S00002, S00003, S00004, S00005, S00006 No.A1853-1/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Flash ROM (ALL FLASH)
• Single 3.3V power supply, on-board writeable
• Block erase in 512 byte units
■Minimum instruction cycle time (Tcyc)
• 83.3ns
■Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units : 86 (P0n, P1n, P2n, P3n, P4n, P5n, P6n, P7n
PAn, PB0 to PB6, PC0, PD0 to PD5)
• Dedicated pin for low-pass filter connection
: 1 (LPFO)
• Regulator pins
: 1 (VREG)
• Reset pins
: 1 (RESB)
• TEST pins
: 1 (TEST)
• Dedicated pins for crystal oscillator
: 2 (XT1, XT2)
• Power pins
: 2 (VDDCPU, VSS1: Main power, I/O power supply)
: 4 (VDDPORT1 to 2, VSS2 to 3: I/O power supply)
: 2 (VDDPLL, VSS4: PLLVCO power)
■SIO: 6 channels (4 channels are also used as I2C bus.)
• SIO0: 8 bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle)
3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes)
• SIO1: 8 bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle)
3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes)
• SMIIC0: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC1: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC2: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC3: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
■UART: 4 channels
1) Data length
: 8 bits (LSB first)
2) Stop bits
: 1 bit
3) Parity bits
: None/even parity/odd parity
4) Transfer rate
: 8 to 4096 cycle
5) Baudrate source clock : System clock/XT clock/VCO clock
5) Wakeup function
6) Full duplex communication
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LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs
1) 5-bit prescaler
2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator
• Timer 1: 16-bit timer with capture registers
1) 5-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator
• Timer 2: 16-bit timer with capture registers
1) 4-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, XT clock, VCO clock, and external events
• Timer 3: 16-bit timer that supports PWM/toggle outputs
1) 8-bit prescaler
2) 8-bit PWM × 2ch or 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, XT clock, VCO clock, and external events
• Timer 4: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 6: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 1
• Timer 7: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 1
* Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from XT clock or VCO clock.
• Timer 8
1) Clock source may be selected from XT clock (32.768kHz) and frequency-divided output of clock.
2) Interrupts can be generated in 8 timing schemes.
• Watch timer
1) Clock may be selected from XT clock (32.768kHz)
2) Interrupts can be generated in 4 timing schemes.
■Day, minute and second counters
1) Count-up of clocks output from watch timer
2) Configured with day counter, minute counter, second counter
3) Continues operation when in HOLDX mode.
■AD converter
1) 12/8 bits resolution selectable
2) Analog input: 13 channels
3) Comparator mode
4) Automatic reference voltage generation
No.A1853-3/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■PWM: Multifrequency 12-bit PWM × 4 channels
• PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B)
• PWM1: Multifrequency 12-bit PWM × 2 channels (PWM1A and PWM1B)
1) 2-channel pairs controlled independently of one another
2) Clock source selectable from system clock or VCO clock
3) 8-bit prescaler: TPWMR0 = (prescaler value + 1) × clock period
4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
5) Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
6) Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWR0 to 256 TPWR0
Overall period
: Fundamental wave period × 16
High pulse width
: 0 to (Overall period - TPWR0)
■Watchdog Timer: 1 channel
• Driven by the timer 8 + internal watchdog timer dedicated counter
• Interrupt or reset mode selectable
■Interrupts
• 63 sources, 16 vector addresses
1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the
current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
1
08000H
WDT (1)
Interrupt Source
2
08004H
Timer 8 (2)/Watch timer (1)
3
08008H
Timer 0 (2)
4
0800CH
INT0 (1)
5
08010H
6
08014H
INT1 (1)
7
08018H
INT2 (1)/timer 1 (2)/UART 2 (3)
8
0801CH
INT3 (1)/timer 2 (3)/SMIIC0 (1)
9
08020H
INT4 (1)/timer 3 (2)/SMIIC1 (1)/IR Remote control receive (4)
10
08024H
INT5 (1)/timer 4 (1)/SIO1 (2)
11
08028H
12
0802CH
PWM0 (1)/PWM1 (1)/SMIIC2 (1)
13
08030H
ADC (1)/timer 5 (1)/SMIIC3 (1)
14
08034H
INT6 (1)/timer 6 (1)/UART 3 (3)
15
08038H
INT7 (1)/timer 7 (1)/SIO0 (2)/UART 4 (3)
16
0803CH
Port 0 (3)/Port 5 (8)/UART 5 (3)
• 3 priority levels selectable.
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• A number enclosed in parentheses denotes the number of sources.
■Subroutine Stack: Entire maximum RAM space (The stack is allocated in RAM.)
• Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
• Subroutine calls that do not automatically save PSW: 4 bytes
■High-speed Multiplication/division instructions
• 16 bits × 16 bits
• 16 bits ÷ 16 bits
• 32 bits ÷ 16 bits
No.A1853-4/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Infrared remote controller receive functions
1) Noise rejection function
2) PPM(Pulse Position Modulation), compatible with Manchester and other data encoding systems.
3) HOLDX mode release function
■Oscillation circuits
• RC oscillator circuit (internal):
For system clock
• XT oscillator circuit:
For system clock
• VCO oscillator circuit (internal): For system clock
■Low power consumption
• HALT mode:
Halts instruction execution while allowing the peripheral circuits to continue operation.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
• HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run
on the XT clock.
■System clock divider function
• Can run on low current.
• 1/1 to 1/128 of the system clock frequency can be set.
No.A1853-5/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Both the XT oscillator and internal RC oscillator retain the state established when the standby mode is entered.
2) Both the XT and VCO clocks retain the state established when the standby mode is entered.
3) There are the two ways of releasing the HALT mode.
(1) Generating a reset condition
(2) Generating an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) Both the XT oscillator and internal RC oscillator automatically stop operation.
2) XT clock and VCO clock oscillators automatically stop.
3) There are the six ways of releasing the HOLD mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
• HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run
on the XT clock.
1) The internal RC oscillator automatically stops operation.
2) The XT clock retains the state established when the HOLDX mode is entered and the VCO clock automatically
stops.
3) There are nine ways of resetting the HOLDX mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
(7) Having an interrupt source established in the timer 8 circuit
(8) Having an interrupt source established in the infrared remote controller receive circuit
(9) Having an interrupt source established in the clock timer circuit
■Reset
• External reset
• Voltage drop detection type of reset circuit (VDET circuit) incorporated
1) Normal mode detection voltage: 2.85V ±0.15V
2) HOLD mode detection voltage: 1.42V ±0.15V
■On-chip debugger function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting and real time monitor.
• Single-wire communication
■Shipping Form
• QIP100E (Lead free product)
No.A1853-6/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.A1853-7/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
P43/SO1
P42
P41
P40/INT6
P00/P0INT
P01/P0INT
P02/P0INT
P03/P0INT
P04/P04INT
P05/P05INT
P06/T0PWML
P07/T0PWMH
P10/SO0
P11/SIO0
P12/SCK0
P13
P14/T3OUTL
P15/T3OUTH
P16/U2RX
P17/U2TX
P30/INT0
P31/INT1
P32/INT2
P33/INT3
P34/U3RX
P35/U3TX
P36/T6O
P37/T7O
VDDPORT2
VSS3
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PA0/SM1CK
81
50
P44/SIO1
PA1/SM1DA
82
49
P45/SCK1
PA2/SM1DO
83
48
P46/PWM00
PA3/SM2CK
84
47
P47/PWM01
PA4/SM2DA
85
46
VSS2
PA5/SM2DO
86
45
VDDPORT1
PA6/U5RX
87
44
P27/RMIN
PA7/U5TX
88
43
P26/T5O
PB0/PWM10
89
42
P25/T4O
PB1/PWM11
90
41
P24/SM0DO
PB2
91
40
P23/SM0DA
PB3
92
39
P22/SM0CK
PB4
93
38
P21/INT5
PB5/INT7
94
37
P20/INT4
PB6
95
36
PD5
VDDPLL
96
35
PD4
VSS4
97
34
PD3
LPFO
98
33
PD2
P50/P5INT0
99
32
PD1/U4TX
P51/P5INT1
100
31
PD0/U4RX
P77/SM3DO
P76/SM3DA
VREG
P75/SM3CK
PC0
P74/AN12
RESB
P73/AN11
TEST
P72/AN10
P57/P5INT7
P71/AN9
P56/P5INT6
P70/AN8
P55/P5INT5
P67/AN7
P54/P5INT4
P66/AN6
P53/P5INT3
P65/AN5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P64/AN4
9
P63/AN3
8
P62/AN2
7
P61/AN1
6
P60/AN0
5
VDDCPU
4
XT2
3
XT1
2
VSS1
1
P52/P5INT2
LC88F40H0PA/PAU
LC88F40F0PA/PAU
LC88F40D0PA/PAU
Top view
No.A1853-8/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
RC
Timer 8
X’tal
Clock generator
System Block Diagram
Watchdog timer
CPU
FLASH ROM
Watch timer
RAM
Day, minute and
second counter
On-chip debugger
Timer 0
Port 0
Timer 1
Port 1
Timer 2
Port 2
Timer 3
Port 3
Timer 4
Port 4
Timer 5
Port 5
Timer 6
Port 6
Timer 7
Port 7
SIO0
Port A
SIO1
Port B
Port C
SMIIC0
Port D
SMIIC1
SMIIC2
PWM0
SMIIC3
PWM1
UART2
ADC
UART3
UART4
UART5
Infrared remote
controller receive
INT0 to INT7
No.A1853-9/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Pin Description
Name
I/O
Description
VDDCPU
-
+ Power sources 3.3V power supply (3.0 to 3.6V)
VDDPORT1
-
+ Power sources I/O power supply (VDDCPU to 5.5V)
VDDPORT2
-
+ Power sources I/O power supply (VDDCPU to 5.5V)
VDDPLL
-
+ Power sources PLLVCO power supply (3.0 to 3.6V)
VSS1
-
- Power sources
VSS2
-
- Power sources
VSS3
-
- Power sources
VSS4
-
Port 0
I/O
P00 to P07
- Power sources
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT1 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Port 0 interrupt input (P00 to P05)
• HOLD release input (P00 to P05)
• Pin functions
P06: Timer 0L output
P07: Timer 0H output
Port 1
I/O
P10 to P17
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT2 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/output
P12: SIO0 clock input/output
P14: Timer 3L output
P15: Timer 3H output
P16: UART2 receive
P17: UART2 transmit
Port 2
I/O
P20 to P27
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT1 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/
timer 2H capture input
P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/
timer 2H capture input
P22: SMIIC0 clock input/output
P23: SMIIC0 data bus input/output
P24: SMIIC0 data (used in 3-wire SIO mode)
P25: Timer 4 output
P26: Timer 5 output
P27: Remote control receive
• Interrupt acknowledge type
INT4, INT5: H level, L level, H edge, L edge, both edges
Port 3
P30 to P37
I/O
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT2 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P30: INT0 input/HOLD release input/timer 2L capture input
P31: INT1 input/HOLD release input/timer 2H capture input
P32: INT2 input/HOLD release input/timer 2 event input/timer 2L capture input
P33: INT3 input/HOLD release input/timer 2 event input/timer 2H capture input
P34: UART3 receive
P35: UART3 transmit
P36: Timer 6 output
P37: Timer 7 output
• Interrupt acknowledge type
INT0 to INT3: H level, L level, H edge, L edge, both edges
Continued on next page.
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LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Name
Port 4
I/O
I/O
P40 to P47
Description
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT1 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P40: INT6 input/HOLD release input
P43: SIO1 data output
P44: SIO1 data input/output
P45: SIO1 clock input/output
P46: PWM00 output
P47: PWM01 output
• Interrupt acknowledge type
INT6: H level, L level, H edge, L edge, both edges
Port 5
I/O
P50 to P57
• 8-bit I/O port
Supply voltage from VDDCPU
• I/O specifiable in 1-bit units
used
• Pull-up resistors can be turned on and off in 1 bit units
(3.0 to 3.6V)
• Pin functions
• Port 5 interrupt function
• HOLD release input
Port 6
I/O
P60 to P67
• 8-bit I/O port
Supply voltage from VDDCPU
• I/O specifiable in 1-bit units
used
• Pull-up resistors can be turned on and off in 1 bit units
(3.0 to 3.6V)
• Pin functions
AN0 (P60) to AN7 (P67): AD converter input port
Port 7
I/O
P70 to P77
• 8-bit I/O port
Supply voltage from VDDCPU
• I/O specifiable in 1-bit units
used
• Pull-up resistors can be turned on and off in 1 bit units
(3.0 to 3.6V)
• Pin functions
AN8 (P70) to AN12 (P74): AD converter input port
P75: SMIIC3 clock input/output
Supply voltage from
P76: SMIIC3 data bus input/output
VDDPORT1 used
(VDDCPU to 5.5V)
Supply voltage from
P77: SMIIC3 data (used in 3-wire SIO mode)
Port A
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
PA0 to PA7
• Pull-up resistors can be turned on and off in 1 bit units
VDDPORT2 used
(VDDCPU to 5.5V)
• Pin functions
PA0: SMIIC1 clock input/output
PA1: SMIIC1 data bus input/output
PA2: SMIIC1 data (used in 3-wire SIO mode)
PA3: SMIIC2 clock input/output
PA4: SMIIC2 data bus input/output
PA5: SMIIC2 data (used in 3-wire SIO mode)
PA6: UART5 receive
PA7: UART5 transmit
Port B
I/O
PB0 to PB6
• 7-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT2 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
PB0: PWM10 output
PB1: PWM11 output
PB5: INT7 input/HOLD release input
• Interrupt acknowledge type
INT7: H level, L level, H edge, L edge, both edges
Port C
I/O
PC0
Port D
PD0 to PD5
I/O
• 1-bit I/O port
Supply voltage from VDDCPU
• I/O specifiable in 1-bit units
used
• Pull-up resistors can be turned on and off in 1 bit units
(3.0 to 3.6V)
• 6-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
VDDPORT1 used
(VDDCPU to 5.5V)
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
PD0: UART4 receive
PD1: UART4 transmit
Continued on next page.
No.A1853-11/32
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Continued from preceding page.
Name
I/O
Description
XT1
I
• Input terminal for 32.768kHz X'tal oscillation
XT2
O
• Output terminal for 32.768kHz X'tal oscillation
RESB
I
• Reset pin
TEST
I/O
• TEST pin
• This must be set to low for 50μs or longer when the power is turned on and when a reset is required.
• Used to communicate with on-chip debugger
• 100kΩ pull-down
LPFO
O
• LPF connection pin for PLLVCO
VREG
O
• Regulator output pin
Connect a bypass capacitor to this pin
No.A1853-12/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Port Output Types
The port output type and pull-up resistance must be set using the registers.
The pin data can be read regardless of the I/O setting of the port.
The port output type (CMOS output or N-channel open drain output) and use/disuse of the pull-up resistor can be
configured separately for each port.
* Make the following connection to minimize the noise input to the VDDCPU pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the
backup capacitors. (VDDCPU = VDDPORT1 = VDDPORT2 = VDDPLL)
LSI
Power
supply
VDDCPU
For
buckup
LPFO
VDDPORT1
VDDPORT2
VDDPLL
VREG
VSS1 VSS2 VSS3 VSS4
Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is
unpredictable. (VDDCPU = VDDPORT1 = VDDPORT2 = VDDPLL)
LSI
Power
supply
VDDCPU
For
buckup
LPFO
VDDPORT1
VDDPORT2
VDDPLL
VREG
VSS1 VSS2 VSS3 VSS4
No.A1853-13/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Maximum Supply
Symbol
Applicable Pin
/Remarks
min
VDD max(1)
VDDCPU
VDDPLL
VDDCPU=VDDPORT1
=VDDPORT2=VDDPLL
VDD max(2)
VDDPORT1
VDDPORT2
VDDPORT1=VDDPORT2
Input voltage
VI(1)
RESB, XT1
Input/Output
VIO(1)
voltage
voltage
Specification
Conditions
typ
max
-0.3
+4.6
-0.3
+6.5
-0.3
VDD(1)+0.3
-0.3
VDD(1)+0.3
-0.3
VDD(2)+0.3
Ports 5, 6
unit
V
P70 to 74
Ports C
XT2
VIO(2)
Ports 0, 1, 2, 3, 4
P75 to P77
Ports A, B, D
Peak output
IOPH(1)
current
Ports 0, 1, 2, 3, 5
CMOS output selected
Ports 6, 7, A, C, D
Per 1 application pin
P40 to P45
-10
PB2 to PB6
IOPH(2)
P46, P47
Per 1 application pin
PB0, PB1
Average
Ports 0, 1, 2, 3, 5
CMOS output selected
output current
IOMH(1)
Ports 6, 7, A, C, D
Per 1 application pin
(Note 1-1)
P40 to P45
-20
-7.5
High level output current
PB2 to PB6
IOMH(2)
P46, P47
Per 1 application pin
PB0, PB1
Total output
ΣIOAH(1)
current
Ports 5
Total of all applicable pins
Ports C
ΣIOAH(2)
Ports 6
Ports 5, 6
-15
mA
Total of all applicable pins
P70 to P74
ΣIOAH(3)
-10
-15
Total of all applicable pins
-20
P70 to P74
Ports C
ΣIOAH(4)
Ports 2, D
Total of all applicable pins
P75 to P77
ΣIOAH(5)
Ports 0, 4
Total of all applicable pins
ΣIOAH(6)
Ports 0, 2, 4, D
Total of all applicable pins
P75 to P77
-25
-25
-45
ΣIOAH(7)
Ports 1, 3
Total of all applicable pins
-25
ΣIOAH(8)
Ports A, B
Total of all applicable pins
-25
ΣIOAH(9)
Ports 1, 3, A, B
Total of all applicable pins
-45
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A1853-14/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Parameter
Peak output
Symbol
IOPL(1)
current
Applicable Pin
/Remarks
Ports 0, 1, 3
Specification
Conditions
min
typ
max
unit
Per 1 application pin.
Ports 4, 5, 6
Ports B, C, D
P20, P21
20
P24 to P27
P70 to P74, P77
PA2, PA5 to PA7
IOPL(2)
P22, P23
Per 1 application pin.
P75, P76
25
PA0, PA1
PA3, PA4
Average
IOML(1)
Ports 0, 1, 3
output current
Ports 4, 5, 6
(Note 1-1)
Ports B, C, D
Per 1 application pin.
P20, P21
10
Low level output current
P24 to P27
P70 to P74, P77
PA2, PA5 to PA7
IOML(2)
P22, P23
Per 1 application pin.
mA
P75, P76
15
PA0, PA1
PA3, PA4
Total output
ΣIOAL(1)
current
Ports 5
Total of all applicable pins
15
Ports C
ΣIOAL(2)
Ports 6
Total of all applicable pins
15
P70 to P74
ΣIOAL(3)
Ports 5, 6
Total of all applicable pins
P70 to P74
20
Ports C
ΣIOAL(4)
Ports 2, D
Total of all applicable pins
25
P75 to P77
ΣIOAL(5)
Ports 0, 4
Total of all applicable pins
ΣIOAL(6)
Ports 0, 2, 4, D
Total of all applicable pins
25
45
P75 to P77
ΣIOAL(7)
Allowable power
Ports 1, 3
Total of all applicable pins
25
ΣIOAL(8)
Ports A, B
Total of all applicable pins
25
ΣIOAL(9)
Ports 1, 3, A, B
Total of all applicable pins
45
Pd max
QIP100E
Ta = -40 to +85°C
400
mW
-40
+85
°C
-45
+125
°C
dissipation
Operating
Topr
temperature range
Storage
Tstg
temperature range
Note 1-1: Average output current is average of current in 100ms interval.
No.A1853-15/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Symbol
Applicable Pin
/Remarks
min
Operating
VDD(1)
VDDCPU=VDDPLL
supply voltage
VDD(2)
VDDPORT1
VDDPORT2
VHD
VDDCPU=VDDPORT1
RAM and register contents
in HOLD mode.
VIH(1)
=VDDPORT2=VDDPLL
Ports 0, 1, 2, 3, 4
Memory sustaining
supply voltage
High level input
voltage
VDDPORT=VDD(2)
max
unit
3.0
3.6
VDD(1)
5.5
1.2
VDD(2)
VDDCPU=VDD(1)
0.3×VDD(1)
+0.7
VDD(1)
0.75×VDD(1)
VDD(1)
0.7×VDD(2)
VDD(2)
VSS
0.1×VDD(2)
+0.4
VSS
0.1×VDD(1)
+0.4
VSS
0.25×VDD(1)
VSS
0.3×VDD(2)
Ports A, B, D
Ports 5, 6, C
typ
0.3×VDD(2)
+0.7
P75 to P77
VIH(2)
Specification
Conditions
P70 to P74
VIH(3)
RESB
VDDCPU=VDD(1)
VIH(4)
P22, P23, P75, P76
VDDPORT=VDD(2)
PA0, PA1, PA3, PA4
V
I2C side
Low level input
VIL(1)
voltage
Ports 0, 1, 2, 3, 4
VDDPORT=VDD(2)
P75 to P77
Ports A, B, D
VIL(2)
Ports 5, 6, C
VDDCPU=VDD(1)
P70 to P74
VIL(3)
RESB
VDDCPU=VDD(1)
VIL(4)
P22, P23, P75, P76
VDDPORT=VDD(2)
PA0, PA1, PA3, PA4
I2C side
Instruction cycle
tCYC
VDDCPU=VDD(1)
time
Supply voltage rise
Tpup
VDDCPU
1
time
Oscillation
FmRC
frequency range
FmX’tal
Internal RC oscillation
XT1, XT2
μs
83.3
32.768kHz crystal
oscillation.
0.5
1.0
32.768
100
ms
2.0
MHz
kHz
No.A1853-16/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
High level input
Symbol
Applicable Pin
VDD[V]
Ports 0, 1, 2, 3, 4
Output disable
P75 to P77
Pull-up resistor OFF
Ports A, B, D
VIN=VDD(2)
(including the off-leak current of
Ports 5, 6, C
Output disable
P70 to P74
Pull-up resistor OFF
RESB
VIN=VDD(1)
(including the off-leak current of
IIH(3)
XT1
VIN=VDD(1)
IIL(1)
Ports 0, 1, 2, 3, 4
Output disable
P75 to P77
Pull-up resistor OFF
Ports A, B, D
VIN=VSS
(including the off-leak current of
Ports 5, 6, C
Output disable
P70 to P74
Pull-up resistor OFF
RESB
VIN=VSS
(including the off-leak current of
IIH(1)
current
Specification
Conditions
/Remarks
min
typ
max
unit
VDDPORT=
VDD(1) to 5.5
1
VDDCPU=
3.0 to 3.6
1
the output Tr.)
IIH(2)
the output Tr.)
Low level input
current
VDDCPU=
3.0 to 3.6
0.18
μA
VDDPORT=
VDD(1) to 5.5
-1
VDDCPU=
3.0 to 3.6
-1
the output Tr.)
IIL(2)
the output Tr.)
High level output
IIL(3)
XT1
VIN=VSS
VOH(1)
Ports 0, 1, 2, 3
IOH=-1.0mA, VDD(2)
voltage
P75 to P77
VDD(2)
-1.0
VDDPORT=
VDD(1) to 5.5
VDD(2)
-0.4
IOH=-1.0mA, VDD(1)
VDDCPU=
3.0 to 3.6
VDD(1)
-1.0
IOH=-0.4mA, VDD(1)
VDDCPU=
3.0 to 3.6
VDD(1)
-0.4
IOH=-10mA, VDD(2)
VDDPORT=
4.5 to 5.5
VDD(2)
-1.5
IOH=-1.6mA, VDD(2)
VDDPORT=
VDD(1) to 5.5
VDDPORT=
VDD(2)
-0.4
IOH=-0.4mA, VDD(2)
Ports A, D
PB2 to PB6
VOH(3)
Ports 5, 6, C
P70 to P74
VOH(4)
VOH(5)
P46, P47
PB0, PB1
VOH(6)
Low level output
VOL(1)
voltage
Ports 0, 1, 3, 4
IOL=10mA
P24 to P27,
V
1.5
4.5 to 5.5
P20, P21
VOL(2)
-0.18
VDDPORT=
4.5 to 5.5
P40 to P45
VOH(2)
VDDCPU=
3.0 to 3.6
IOL=1.6mA
P77
VDDPORT=
VDD(1) to 5.5
PA2, PA5 to PA7
0.4
Ports B, D
VOL(3)
Ports 5, 6, C
IOL=1.6mA
P70 to P74
VOL(4)
P22, P23
PA0, PA1
IOL=11mA
VDDPORT=
4.5 to 5.5
IOL=3.0mA
VDDPORT=
VDD(1) to 5.5
VDDPORT=
PA3, PA4
Pull-up resistor
Rpu(1)
Ports 0, 1, 2, 3, 4
VOH=0.9VDD
4.5 to 5.5
P75 to P77
Rpu(2)
Rpu(3)
Ports A, B, D
VDDPORT=
VDD(1) to 5.5
VDDCPU=
Ports 5, 6, C
P70 to P74
Hysteresis
voltage
VHYS
0.4
3.0 to 3.6
P75, P76
VOL(5)
VDDCPU=
3.0 to 3.6
1.5
0.4
15
35
80
15
35
150
15
35
150
kΩ
RESB
Ports 1, 2, 3, 4, 5
Ports 1 to 5, 7, A to D
Ports 7, A, B, C, D
PnFSAn=1
0.1VDD
V
Continued on next page.
No.A1853-17/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Parameter
Pin capacitance
Applicable Pin
Symbol
CP
Specification
Conditions
/Remarks
VDD[V]
min
typ
max
unit
• For pins other than that under
All pins
test: VIN=VSS
• f=1MHz
10
pF
• Ta=25°C
Low voltage
VDET(1)
VDDCPU
circuit
On low voltage detection circuit
Excluding the HOLD mode
detection
VDET(2)
VDDCPU
voltage
On low voltage detection circuit
HOLD mode
2.7
2.85
3.0
V
1.27
1.42
1.57
V
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0, SIO1 Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Parameter
Period
Symbol
tSCK(1)
Applicable Pin
SCK0(P12)
Specification
Conditions
/Remarks
VDD[V]
• See Fig. 1.
tSCKL(1)
Input clock
max
unit
2
pulse width
High level
typ
4
SCK1(P45)
Low level
min
tSCKH(1)
2
pulse width
• Automatic communication mode
tSCKHA(1)
• See Fig. 1.
tSCKHBSY
• Automatic communication mode
(1a)
• See Fig. 1.
tSCKHBSY
• Modes other than automatic
(1b)
VDDPORT=
VDD(1) to 5.5
6
tCYC
23
communication mode
4
Serial clock
• See Fig. 1.
Period
Low level
tSCK(2)
SCK0(P12)
• CMOS output selected
SCK1(P45)
• See Fig. 1.
4
tSCKL(2)
1/2
pulse width
Output clock
High level
tSCK
tSCKH(2)
1/2
pulse width
• Automatic communication mode
tSCKHA(2)
• CMOS output selected
• See Fig. 1.
tSCKHBSY
• Automatic communication mode
(2a)
• CMOS output selected
VDDPORT=
VDD(1) to 5.5
6
4
23
tCYC
• See Fig. 1.
• Modes other than automatic
tSCKHBSY
(2b)
communication mode
4
• See Fig. 1.
Serial input
Data setup time
SIO0(P11),
SIO1(P44)
• Specified with respect to rising
Data hold time
0.03
edge of SIOCLK
• See fig. 1.
thDI(1)
VDDPORT=
VDD(1) to 5.5
0.03
Output clock
Input clock
Output
Serial output
tsDI(1)
tdD0(1)
delay time
SO0(P10),
• (Note 4-1-2)
SO1(P43),
1tCYC
SIO0(P11),
tdD0(2)
μs
+0.05
SIO1(P44)
• (Note 4-1-2)
VDDPORT=
VDD(1) to 5.5
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state
change in open drain output mode. See Fig. 1.
No.A1853-18/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
2. SIO0, SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1)
Parameter
Period
Symbol
tSCK(3)
Applicable Pin
SCK0(P12)
Specification
Conditions
/Remarks
VDD[V]
min
• See Fig. 1.
Input clock
Serial clock
tSCKL(3)
High level
1
VDDPORT=
VDD(1) to 5.5
pulse width
tSCKH(3)
tSCKHBSY(3)
Serial input
• Specified with respect to rising
0.03
edge of SIOCLK
VDDPORT=
VDD(1) to 5.5
• See fig. 1.
Data hold time
tCYC
2
SIO0(P11),
SIO1(P44)
thDI(2)
0.03
Output
tdD0(3)
delay time
SO0(P10),
μs
• (Note 4-2-2)
SO1(P43),
Input clock
Serial output
tsDI(2)
unit
1
pulse width
Data setup time
max
2
SCK1(P45)
Low level
typ
SIO0(P11),
VDDPORT=
VDD(1) to 5.5
SIO1(P44)
1tCYC
+0.05
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-2-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state
change in open drain output mode. See Fig. 1.
3. SMIIC0 to SMIIC3 Simple SIO Mode Input/Output Characteristics
Parameter
Input clock
tSCK(4)
Applicable Pin
SM0CK(P22)
Specification
Conditions
/Remarks
VDD[V]
• See Fig. 1.
Low level
tSCKL(4)
High level
SM2CK(PA3)
VDDPORT=
VDD(1) to 5.5
SM3CK(P75)
pulse width
Period
tSCKH(4)
Low level
tSCK(5)
tSCKL(5)
High level
typ
tCYC
SM0CK(P22)
• CMOS output selected
SM1CK(PA0)
• See Fig. 1.
SM2CK(PA3)
8
VDDPORT=
VDD(1) to 5.5
1/2
tSCK
tSCKH(5)
1/2
Serial input
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
Data hold time
thDI(3)
• Specified with respect to rising
0.03
edge of SIOCLK
• See fig. 1.
SM3DA(P76)
VDDPORT=
VDD(1) to 5.5
0.03
Output delay
time
Serial output
tsDI(3)
unit
2
pulse width
Data setup time
max
2
SM3CK(P75)
pulse width
min
4
SM1CK(PA0)
pulse width
Output clock
Serial clock
Period
Symbol
tdD0(4)
SM0DO(P24)
SM0D1(PA2)
SM0D2(PA5)
SM0D3(P77)
SM0DA(P23)
• Specified with respect to falling
μs
edge of SIOCLK
• Specified as interval up to time
when output state starts changing.
• See Fig. 1.
VDDPORT=
VDD(1) to 5.5
1tCYC
+0.05
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
Note 4-5-1: These specifications are theoretical values. Add margin depending on its use.
No.A1853-19/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0 and SIO1 only)
tSCK
SIOCLK:
tSCKL
tSCKH
tsDI
thDI
DATAIN:
DATAOUT:
Data transfer period
(SIO0 and SIO1 only)
SIOCLK:
tSCKL
tSCKHA
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
* Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768
Figure 1 Serial I/O Waveforms
No.A1853-20/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
4. SMIIC0 to SMIIC3 I2C Mode Input/Output Characteristics
Parameter
Symbol
Input clock
tSCL
SM0CK(P22)
Specification
Conditions
/Remarks
VDD[V]
• See Fig. 2.
Low level
tSCLL
High level
SM2CK(PA3)
VDDPORT=
VDD(1) to 5.5
SM3CK(P75)
pulse width
tSCLH
Period
tSCLx
tSCLLx
SM0CK(P22)
High level
• Specified as interval up to time
Tfilt
SM2CK(PA3)
VDDPORT=
VDD(1) to 5.5
1/2
tSCL
1/2
pulse width
tsp
unit
2.5
tSCLHx
SM0C and SM0DA
max
10
when output state starts changing.
SM3CK(P75)
pulse width
typ
2
SM1CK(PA0)
Low level
min
5
SM1CK(PA0)
pulse width
Output clock
Serial clock
Period
Applicable Pin
SM0CK(P22)
pins input spike
SM1CK(PA0)
suppression time
SM2CK(PA3)
• See fig. 2.
SM3CK(P75)
1
SM0DA(P23)
Tfilt
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
time between
start and stop
tBUF
Input
Bus release
SM0CK(P22)
• See fig. 2.
SM1CK(PA0)
2.5
SM2CK(PA3)
SM3CK(P75)
tBUFx
SM0DA(P23)
Output
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• Standard-mode
• Specified as interval up to time
VDDPORT=
VDD(1) to 5.5
5.5
μs
when output state starts changing.
• Fast-mode
1.6
• Specified as interval up to time
when output state starts changing.
Start/restart
tHD; STA
SM0CK(P22)
• When SMIIC register control bit,
SM1CK(PA0)
time
SM2CK(PA3)
• See fig. 2.
SM3CK(P75)
• When SMIIC register control bit,
Input
condition hold
SM0DA(P23)
2.0
Tfilt
I2CSHDS=1
SM1DA(PA1)
• See fig. 2.
SM2DA(PA4)
• Standard-mode
SM3DA(P76)
• Specified as interval up to time
Output
tHD; STAx
I2CSHDS=0
2.5
VDDPORT=
VDD(1) to 5.5
4.1
when output state starts changing.
μs
• Fast-mode
• Specified as interval up to time
1.0
Restart
condition setup
Input
when output state starts changing.
tSU; STA
SM0CK(P22)
• See fig. 2.
SM1CK(PA0)
time
1.0
Tfilt
SM2CK(PA3)
Output
tSU; STAx
SM3CK(P75)
• Standard-mode
SM0DA(P23)
• Specified as interval up to time
SM1DA(PA1)
when output state starts changing.
SM2DA(PA4)
• Fast-mode
SM3DA(P76)
• Specified as interval up to time
VDDPORT=
VDD(1) to 5.5
5.5
μs
1.6
Stop condition
setup time
Input
when output state starts changing.
tSU; STO
SM0CK(P22)
• See fig. 2.
SM1CK(PA0)
1.0
Tfilt
SM2CK(PA3)
Output
tSU; STOx
SM3CK(P75)
• Standard-mode
SM0DA(P23)
• Specified as interval up to time
SM1DA(PA1)
when output state starts changing.
SM2DA(PA4)
• Fast-mode
SM3DA(P76)
• Specified as interval up to time
VDDPORT=
VDD(1) to 5.5
4.9
μs
1.1
when output state starts changing.
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Continued on next page.
No.A1853-21/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Parameter
Applicable Pin
Symbol
SM0CK(P22)
tHD; DAT
Input
Data hold time
Specification
Conditions
/Remarks
VDD[V]
min
typ
max
unit
• See fig. 2.
SM1CK(PA0)
0
SM2CK(PA3)
SM3CK(P75)
tHD; DATx
Output
SM0DA(P23)
SM1DA(PA1)
• Specified as interval up to time
when output state starts changing.
VDDPORT=
VDD(1) to 5.5
Tfilt
1
1.5
SM2DA(PA4)
SM3DA(P76)
SM0CK(P22)
tSU; DAT
Input
Data setup time
• See fig. 2.
SM1CK(PA0)
1
SM2CK(PA3)
SM3CK(P75)
tSU; DATx
Output
SM0DA(P23)
SM1DA(PA1)
• Specified as interval up to time
when output state starts changing.
VDDPORT=
VDD(1) to 5.5
Tfilt
1tSCL
-1.5Tfilt
SM2DA(PA4)
Fall time
Input
SM3DA(P76)
tF
SM0CK(P22)
• See fig. 2.
VDDPORT=
VDD(1) to 5.5
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
tF
SM0DA(P23)
Output
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• When SMIIC register control bits,
PSLW=1, P5V=1
• When SMIIC register control bits,
PSLW=1, P5V=0
• When SMIIC register control bits,
PSLW=0
• Cb ≤ 400pF
300
VDDPORT=5
20+0.1Cb
250
VDDPORT=3
20+0.1Cb
250
ns
VDDPORT=
VDD(1) to 5.5
100
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMICnBRG (n=0, 1, 2, 3), bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC × 1
0
1
tCYC × 2
1
0
tCYC × 3
1
1
tCYC × 4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt > 140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The fast-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1853-22/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
P
SDA
S
Sr
P
tBUF
tHD;STA tR
tHD;STA
tF
tsp
SCK
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2 I2C Timing
5. UART2 to UART5 Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Transfer rate
Symbol
UBR
Applicable Pin
Specification
Conditions
/Remarks
VDD[V]
min
typ
max
unit
U2RX(P16),
U3RX(P34),
U4RX(PD0),
U5RX(PA6),
VDDPORT=
VDD(1) to 5.5
U2TX(P17),
8
4096
tBGCYC
U3TX(P35),
U4TX(PD1),
U5TX(PA7)
Note 4-7: tBGCYC denotes one cycle of the baudrate clock source.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Symbol
Applicable Pin
Specification
Conditions
/Remarks
VDD[V]
High/low level
tPIH(1)
INT0(P30),
• Interrupt source flag can be set.
minimum pulse
tPIL(1)
INT1(P31),
• Event inputs for timers 2 and 3
width
INT2(P32),
min
typ
max
unit
are enabled.
INT3(P33),
INT4(P20),
VDDPORT=
VDD(1) to 5.5
2
tCYC
VDDCPU=
3.0 to 3.6
50
μs
(Note 5-2)
50
μs
INT5(P21),
INT6(P40),
INT7(PB5)
tPIL(2)
RESB
Can be reset via the external
reset pin.
(Note 5-1)
tPIL(3)
VDDCPU
Can be reset by the low voltage
detection circuit.
(Note 5-1)
Note 5-1: This parameter specifies the time required to ensure that the reset sequence is carried out without fail.
The reset may be applied even if this time specification is not satisfied.
Note 5-2: (VDDCPU voltage) ≤ (Low voltage circuit detection voltage)
tPIL
tPIH
Figure 3 Pulse Input Timing Signal Waveform
No.A1853-23/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. 12-bit AD Conversion Mode
Parameter
Symbol
Applicable Pin
/Remarks
Resolution
NAD
AN0(P60)
Absolute accuracy
ETAD
to AN7(P67),
Conversion time
TCAD12
Analog input
VAIN
AN8(P70)
to AN12(P74)
Specification
Conditions
VDDCPU[V]
min
typ
3.0 to 3.6
3.0 to 3.6
Conversion time calculated
3.0 to 3.6
102
3.0 to 3.6
VSS
Analog port
IAINH
VAIN=VDDCPU
3.0 to 3.6
input current
IAINL
VAIN=VSS
3.0 to 3.6
unit
bit
±16
(Note 6-1)
voltage range
max
12
LSB
μs
VDDCPU
1
-1
V
μA
Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC
2. 8-bit AD Conversion Mode
Parameter
Symbol
Applicable Pin
/Remarks
Resolution
NAD
AN0(P60)
Absolute accuracy
ETAD
to AN7(P67),
Conversion time
TCAD8
AN8(P70)
VDDCPU[V]
min
typ
3.0 to 3.6
Conversion time calculated
3.0 to 3.6
32
3.0 to 3.6
VSS
voltage range
Analog port
IAINH
VAIN=VDDCPU
3.0 to 3.6
input current
IAINL
VAIN=VSS
3.0 to 3.6
unit
bit
±1.5
3.0 to 3.6
VAIN
max
8
(Note 6-1)
to AN12(P74)
Analog input
Specification
Conditions
μs
VDDCPU
1
-1
LSB
V
μA
Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD
conversion mode.
No.A1853-24/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
consumption
current
Applicable Pin
VDDCPU
=VDDPORT1
=VDDPORT2
=VDDPLL
(Note 7-1)
IDDOP(2)
Specification
Conditions
/Remarks
VDD[V]
min
typ
max
unit
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (12MHz)
• Internal RC oscillation stopped
3.0 to 3.6
10
15
3.0 to 3.6
8
12
• 1/1 frequency division mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (8MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDOP(3)
mA
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (4MHz)
• Internal RC oscillation stopped
3.0 to 3.6
6
9
3.0 to 3.6
3.5
5
3.0 to 3.6
35
150
3.0 to 3.6
3.5
5
3.0 to 3.6
2.5
4
• 1/1 frequency division mode
IDDOP(4)
• FmX’tal=0kHz (oscillation stopped)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
IDDOP(5)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
μA
• 1/1 frequency division mode
HALT mode
IDDHALT(1)
consumption
current
VDDCPU
=VDDPORT1
=VDDPORT2
=VDDPLL
(Note 7-1)
HALT mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (12MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDHALT(2)
HALT mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (8MHz)
• Internal RC oscillation stopped
mA
• 1/1 frequency division mode
IDDHALT(3)
HALT mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (4MHz)
3.0 to 3.6
1.5
3
3.0 to 3.6
0.2
1
3.0 to 3.6
15
100
3.0 to 3.6
1
30
3.0 to 3.6
15
50
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDHALT(4)
HALT mode
• FmX’tal=0kHz (oscillation stopped)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
IDDHALT(5)
HALT mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
HOLD mode
IDDHOLD(1)
VDDCPU
HOLD mode
consumption
μA
current
HOLDX mode
consumption
IDDHOLD(2)
VDDCPU
HOLDX mode
• FmX’tal=32.768kHz crystal oscillation mode
current
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
No.A1853-25/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Onboard
Symbol
IDDFW(1)
Applicable Pin
/Remarks
VDDCPU
VDDCPU[V]
min
typ
max
unit
• Microcontroller erase consumption
current is excluded.
programming
Specification
Conditions
3.0 to 3.6
10
20
mA
current
Onboard
programming
time
tFW(1)
• 512-byte erase operation
3.0 to 3.6
20
30
ms
tFW(2)
• 2-byte programming operation
3.0 to 3.6
40
60
μs
No.A1853-26/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power Pin Treatment Condition 1 (VDDCPU, VSS1)
Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins:
• Connect among the VDDCPU and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires,
of the same length (L1=L1’, L2=L2’) wherever possible.
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
• The capacitance of C2 should be approximately 0.1μF or larger.
• Please mount a suitable capacitor about C1.
• The VDDCPU and VSS1 traces must be thicker than the other traces.
L2
L1
VDDCPU
C1
C2
VSS1
L1’
L2’
Figure 4
Power Pin Treatment Condition 2 (VDDPORT1 to 2, VSS2 to 3)
Connect capacitors that meet the following conditions between the VDDPORT1 to VSS2 and VDDPORT2 to VSS3
pins:
• Connect among the VDDPORT1 to 2 and VSS2 to 3 pins and the capacitor C3 with the shortest possible lead wires,
of the same length (L3=L3’) wherever possible.
• The capacitance of C3 should be approximately 0.1μF or larger.
• The VDDPORT1 to 2 and VSS2 to 3 traces must be thicker than the other traces.
L3
VDDPORT1/
VDDPORT2
C3
L3’
VSS2/
VSS3
Figure 5
No.A1853-27/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power Pin Treatment Condition 3 (VDDPLL, VSS4)
Connect capacitors that meet the following conditions between the VDDPLL and VSS4 pins:
• Connect among the VDDPLL and VSS4 pins and the capacitors C4 and C5 with the shortest possible lead wires,
of the same length (L4=L4’, L5=L5’) wherever possible.
• Connect a large-capacity capacitor C4 and a small-capacity capacitor C5 in parallel.
• The capacitance of C4 should be approximately 10μF.
• The capacitance of C5 should be approximately 0.1μF.
• The VDDPLL and VSS4 traces must be thicker than the other traces.
L5
L4
VDDPLL
C4
C5
VSS4
L4’
L5’
Figure 6
Power Pin Treatment Condition 4 (VREG, VSS1)
Connect capacitors that meet the following conditions between the VREG and VSS1 pins:
• Connect among the VREG and VSS1 pins and the capacitors C6 with the shortest possible lead wires,
of the same length (L6=L6’) wherever possible.
• The capacitance of C6 should be approximately 1μF.
• The VREG and VSS1 traces must be thicker than the other traces.
L6
VREG
C6
VSS1
L6’
Figure 7
No.A1853-28/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
LPF Pin Treatment Condition (LPFO)
Insert a resistor and capacitors that meet the following conditions between the LPFO and VSS4 pins.
R1 = 3.3kΩ
C7 = 0.068μF
C8 = 0.0039μF
• Routing traces between the LPFO and VSS4 pins and the resistor and capacitors, and between R1 and C7 must be as
short as possible.
* After the PLL circuit is activated, 50ms or more is required for stabilizing oscillation.
LPFO
C8
R1
C7
VSS4
Figure 8
TEST Pin Treatment Condition (TEST)
Insert a resistor that meets the following condition between the TEST and VSS1 pins.
RTEST = 100kΩ
TEST
RTEST
VSS1
Figure 9
No.A1853-29/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Example of Crystal Oscillator Circuit Characteristics
Given below are the characteristics of a sample crystal oscillator circuit that were measured using a SANYO-designated
oscillation characteristics evaluation board and external components with circuit constant values with which the
oscillator vendor confirmed normal and stable oscillation.
Table 1 Example of Crystal Oscillator Circuit Characteristics with a Crystal Resonator
Circuit Constant
Nominal
Vendor
Frequency
Name
32.768kHz
RIVER ELETEC
Oscillator Name
TFX-03
(CL=12.5pF)
C1
C2
Rd
[pF]
[pF]
[Ω]
15
15
Operating
Oscillator
Voltage
Stabilization Time
Range
tmsX'tal(typ)
[V]
[s]
Remarks
VDDCPU=
3.0 to 3.6
680k
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the XT oscillator circuit is executed plus the time interval that is required for the oscillation to get
stabilized after the HOLD mode is released (see Figure 11).
Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the
oscillation characteristics are affected by their trace pattern.
XT1
XT2
Rd
C1
C2
X’tal
Figure 10 XT Oscillator Circuit
No.A1853-30/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power VDDPORT
*1
VDDCPU
Operating VDD
lower limit
0V
Power VDDCPU
Reset time
tPIL(2)
RESB
Internal RC
oscillation
tms
X'tal
XT1, XT2
Operating
mode
Unpredictable
Reset
Initialization instruction
execution
User instruction execution
Figure 11 Reset Time and Oscillation Stabilization Time
*1: The voltage when the power is turned on and off must stand in the following relationship: VDDPORT ≥ VDDCPU.
It should be noted that, while the VDDPORT power is supplied, the I/O pin remains in an undefined state until the
VDDCPU voltage reaches the allowable operation range.
HOLD
release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC
oscillation
tms
X'tal
XT1, XT2
State
HOLD
HALT
Instruction execution
Figure 12 HOLD Release and Oscillation Stabilization Time
No.A1853-31/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Reset Pin Treatment Condition (RESB)
VDDCPU
RRES
RESB
CRES
(Note)
When the power is turned on, the RESB pin must be set to the
low level.
(A reset period of 50μs or longer is required after the power has
stabilized.)
Recommended value
RRES: 100kΩ
CRES: 0.033μF
Figure 13 Reset Circuit
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1853-32/32