LH5164A/AH FEATURES • 8,192 × 8 bit organization • Access times: 80/100 ns (MAX.) • Low-power consumption: Operating: 303 mW (MAX.) LH5164A/D/N @ 80 ns 248 mW (MAX.) LH5164A/D/N/T @ 100 ns 275 mW (MAX.) LH5164AH/HD/HN/HT @ 100 ns Standby: LH5164A/D/N/T: 5.5 µW (MAX.) LH5164AH/HD/HN/HT: TA ≤ 85°C: 16.5 µW (MAX.) TA ≤ 70°C: 5.5 µW (MAX.) • Fully-static operation CMOS 64K (8K × 8) Static RAM PIN CONNECTIONS 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP TOP VIEW NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 5164A-1 Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages • Three-state outputs • Single +5 V power supply • TTL compatible I/O • Wide temperature range available LH5164A: -10 to +70°C LH5164AH: -40 to +85°C • Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP 28-pin, 8 × 13 mm2 TSOP (Type I) DESCRIPTION The LH5164A/AH are static RAMs organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology. The LH5164AH is designed for wide temperature range from -40 to +85°C. 28-PIN TSOP (Type I) TOP VIEW OE 1 28 A11 2 27 CE1 A9 3 26 I/O8 A10 A8 4 25 I/O7 CE2 5 24 I/O6 WE VCC 6 23 I/O5 7 22 I/O4 NC 8 21 GND A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 14 15 A2 A3 5164A-8 Figure 2. Pin Connections for TSOP Package 1 CMOS 64K (8K × 8) Static RAM LH5164A/AH A3 ROW ADDRESS BUFFERS 6 A5 5 A6 4 ROW DECODERS 7 A4 A7 3 A8 25 A9 24 A12 2 I/O1 11 I/O2 12 I/O3 13 I/O4 15 28 VCC MEMORY ARRAY (256 x 256) 14 GND I/O CIRCUITS DATA CONTROL I/O5 16 I/O6 17 I/O7 18 I/O8 19 COLUMN DECODERS COLUMN ADDRESS BUFFER WE 27 OE 22 CE2 26 CE1 20 10 A0 9 A1 8 A2 21 A10 23 A11 NOTE: Pin numbers apply to 28-pin DIP, SK-DIP, or SOP. 5164A-2 Figure 3. LH5164A/AH Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 - A12 SIGNAL Address inputs PIN NAME I/O1 - I/O8 Data inputs and outputs CE1 - CE2 Chip Enable input VCC Power supply WE Write Enable input GND Ground OE Output Enable input NC No connection TRUTH TABLE CE1 CE2 WE OE MODE I/O 1 - I/O 8 SUPPLY CURRENT NOTE H X X X Deselect High-Z Standby (ISB) 1 X L X X Deselect High-Z Standby (ISB) 1 L H L X Write DIN Operating (ICC) 1 L H H L Read DOUT Operating (ICC) L H H H Output disable High-Z Operating (ICC) NOTE: 1. X = H or L 2 CMOS 64K (8K × 8) Static RAM LH5164A/AH ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL 80 ns 100 ns RATING RATING UNIT NOTE Supply voltage VCC -0.3 to +7.0 -0.3 to +7.0 V 1 Input voltage VIN -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 V 1, 2 Operating temperature -10 to +70 Topr Storage temperature Tstg -55 to +150 -10 to +70 °C 3 -40 to +85 °C 4 -55 to +150 °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT RECOMMENDED OPERATING CONDITIONS 1 PARAMETER Supply voltage Input voltage 80 ns SYMBOL VCC 100 ns UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 4.5 5.0 5.5 V VIH 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL -0.3 0.8 -0.3 0.8 V NOTE 2 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT). 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. DC CHARACTERISTICS 1 (VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT Input leakage current ILI -1.0 1.0 µA Output leakage current ILO VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = V IH or WE = VIL VI/O = 0 to VCC CE1 = VIL, VIN = VIL or VIH tCYCLE = 80 ns CE2 = VIH, Outputs open -1.0 1.0 µA 55 mA ICC CE1 = VIL, VIN = VIL or VIH CE2 = VIH, Outputs open Standby current ISB1 Output voltage VOL VOH CE1 = VIL, VIN = 0.2 V or tCYCLE = VCC - 0.2 V 1.0 µs CE2 = VIH, Outputs open CE1 = VIH or CE2 = VIL TA ≤ 70°C CE2 ≤ 0.2 V or CE1 ≥ VCC - 0.2 V TA ≤ 85°C IOL = 2.1 mA IOH = -1 mA Operating current 45 50 tCYCLE = 100 ns NOTE 2 3 mA 10 5 1.0 3.0 0.4 2.4 mA µA µA V V 2, 3, 4 3, 4 NOTES: 1. TA = -10 to 70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. LH5164A/AD/AN/AT 3. LH5164AH/AHD/AHN/AHT 4. CE2 should be ≥ VCC – 0.2 V or ≤ 0.2 V when CE1 ≥ VCC – 0.2 V 3 CMOS 64K (8K × 8) Static RAM LH5164A/AH AC CHARACTERISTICS 1 (1) READ CYCLE (VCC = 5 V ±10%) PARAMETER 80 ns SYMBOL MIN. 100 ns MAX. MIN. Read cycle time tRC Address access time tAA 80 100 ns (CE1) tACE1 80 100 ns (CE2) tACE2 80 100 ns tOE 40 40 ns Chip enable access time Output enable access time Output hold time Chip enable to output in Low-Z NOTE 100 ns tOH 10 10 ns (CE1) tLZ1 10 10 ns 1 (CE2) tLZ2 10 10 ns 1 tOLZ 5 5 ns 1 (CE1) tHZ1 0 30 0 30 ns 1 (CE2) tHZ2 0 30 0 30 ns 1 tOHZ 0 20 0 20 ns 1 Output enable to output in Low-Z Chip enable to output in High-Z 80 UNIT MAX. Output disable to output in High-Z (2) WRITE CYCLE (VCC = 5 V ±10%) PARAMETER 80 ns SYMBOL MIN. Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Output active from end of write WE to output in High-Z OE to output in High-Z tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ 100 ns MAX. MIN. 30 20 100 80 80 0 60 0 40 0 10 0 0 80 70 70 0 60 0 40 0 10 0 0 30 20 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER Input voltage amplitude Input rise/fall time Timing reference level Output load conditions MODE NOTE 0.6 to 2.4 V 10 ns 1.5 V 1TTL + CL (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. 4 UNIT NOTE ns ns ns ns ns ns ns ns ns ns ns 2 2 2 MAX. CMOS 64K (8K × 8) Static RAM LH5164A/AH CAPACITANCE 1 (TA = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input capacitance CIN VIN = 0 V 7 pF Input/output capacitance CI/O VI/O = 0 V 10 pF NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS 1 PARAMETER Data retention voltage SYMBOL VCCDR CONDITIONS Recovery time UNIT NOTE 2.0 5.5 V 2 TA = 25°C 0.2 µA 2, 3 TA = 40°C 0.4 µA 2, 3 0.6 µA 2, 3 TA = 25°C 0.2 µA 2, 4 TA = 70°C 0.6 µA 2, 4 1.5 µA 2, 4 ICCDR VCCDR = 3 V, CE2 ≤ 0.2 V or CE1 ≥ VCCDR - 0.2 V Chip disable to data retention MAX. CE2 ≤ 0.2 V or CE1 ≥ VCCDR - 0.2 V VCCDR = 3 V, CE2 ≤ 0.2 V or CE1 ≥ VCCDR - 0.2 V Data retention current MIN. tCDR 0 ns tR tRC ns 5 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR – 0.2 V 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT 5. t RC = Read cycle time 5 CMOS 64K (8K × 8) Static RAM LH5164A/AH DATA RETENTION MODE CE1 CONTROL (NOTE) VCC tCDR tR 4.5 V 2.2 V VCCDR CE1 ≥ VCCDR - 0.2 V CE1 0V CE2 CONTROL DATA RETENTION MODE VCC 4.5 V tCDR CE2 tR VCCDR 0.8 V 0V CE2 ≥ 0.2 V NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode. 5164A-6 Figure 4. Low Voltage Data Retention tRC A0 - A12 tAA tACE1 CE1 tLZ1 tHZ1 tACE2 CE2 tLZ2 tOE tHZ2 tOLZ OE tOHZ I/O1 - I/O8 DATA VALID tOH NOTE: WE = 'HIGH.' 5164A-3 Figure 5. Read Cycle 6 CMOS 64K (8K × 8) Static RAM LH5164A/AH tWC A0 - A12 OE (NOTE 4) tAW tWR tCW (NOTE 2) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE tOHZ (NOTE 5) HIGH-Z DOUT tDW DIN tDH (NOTE 6) DATA VALID NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied. 5164A-4 Figure 6. Write Cycle 1 7 CMOS 64K (8K × 8) Static RAM LH5164A/AH tWC A0 - A12 tAW tWR (NOTE 4) tCW (NOTE 2) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE (NOTE 5) tWZ tOW HIGH-Z DOUT tDW DIN (NOTE 6) tDH (NOTE 7) DATA VALID OE = 'LOW' NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the outputs will remain high-impedance. 7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied. Figure 7. Write Cycle 2 8 5164A-5 CMOS 64K (8K × 8) Static RAM LH5164A/AH PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 14 0.30 [0.012] 0.20 [0.008] 36.30 [1.429] 35.70 [1.406] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.60 [0.024] 0.40 [0.016] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.020] MIN. MAXIMUM LIMIT MINIMUM LIMIT 28DIP-2 28-pin, 600-mil DIP 28DIP (DIP028-P-0300) DETAIL 28 15 7.05 [0.278] 6.65 [0.262] 1 0° TO 15° 14 0.35 [0.014] 0.15 [0.006] 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.02] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-6 28-pin, 300-mil SK-DIP 9 CMOS 64K (8K × 8) Static RAM LH5164A/AH 28SOP (SOP028-P-0450) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP 10 CMOS 64K (8K × 8) Static RAM LH5164A/AH 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 28 15 12.00 [0.472] 11.60 [0.457] 1 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 14 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] DETAIL 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] 0 - 10° 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP 28-pin, 8 × 13 mm2 TSOP (Type I) ORDERING INFORMATION LH5164A X X Device Type Operating Package Temperature - ## Speed L Power Low-power standby 10 100 Access Time (ns) 80 80 Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (SK-DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) Blank -10 to 70°C H -40 to +85°C CMOS 64K (8K x 8) Static RAM Example: LH5164AD-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, Low-power standby, 28-pin, 300-mil SK-DIP) 5164A-7 11 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. 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