LMH6628QML LMH6628QML Dual Wideband, Low Noise, Voltage Feedback Op Amp Literature Number: SNOSAQ1A LMH6628QML Dual Wideband, Low Noise, Voltage Feedback Op Amp General Description Features The National LMH6628 is a high speed dual op amp that offers a traditional voltage feedback topology featuring unity gain stability and slew enhanced circuitry. The LMH6628's low noise and very low harmonic distortion combine to form a wide dynamic range op amp that operates from a single (5V to 12V) or dual (±5V) power supply. Each of the LMH6628's closely matched channels provides a 300MHz unity gain bandwidth and low input voltage noise ). Low 2nd/3rd harmonic distortion (−65/ density (2nV/ −74dBc at 10MHz) make the LMH6628 a perfect wide dynamic range amplifier for matched I/Q channels. With its fast and accurate settling (12ns to 0.1%), the LMH6628 is also an excellent choice for wide dynamic range, anti-aliasing filters to buffer the inputs of hi resolution analogto-digital converters. Combining the LMH6628's two tightly matched amplifiers in a single package reduces cost and board space for many composite amplifier applications such as active filters, differential line drivers/receivers, fast peak detectors and instrumentation amplifiers. The LMH6628 is fabricated using National’s VIP10™ complimentary bipolar process. To reduce design times and assist in board layout, the LMH6628 is supported by an evaluation board (CLC730036). ■ ■ ■ ■ ■ ■ ■ ■ Available with radiation guraranteed Wide unity gain bandwidth: 300MHz Low noise: 2nV/ Low Distortion: −65/−74dBc (10MHz) Settling time: 12ns to 0.1% Wide supply voltage range: ±2.5V to ±6V High output current: ±85mA Improved replacement for CLC428 300 krad(Si) Applications ■ ■ ■ ■ ■ ■ High speed dual op amp Low noise integrators Low noise active filters Driver/receiver for transmission systems High speed detectors I/Q channel amplifiers Ordering Information NS Part Number SMD Part Number NS Package Number Package Description LMH6628J-QMLV 5962-0254501VPA J08A LMH6628WG-QML 5962-0254501MZA WG10A 8LD CERDIP 10LD CERAMIC SOIC LMH6628WGFQMLV 5962-0254501VZA 300 krad(Si) WG10A 10LD CERAMIC SOIC VIP10™ is a trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 201515 www.national.com LMH6628QML Dual Wideband, Low Noise, Voltage Feedback Op Amp July 12, 2011 LMH6628QML Connection Diagrams 8 Lead Cerdip (J) 10 Lead Ceramic SOIC (WG) 20151550 Top View See NS Package Number WG10A 20151549 Top View See NS Package Number J08A Inverting Frequency Response 20151515 www.national.com 2 LMH6628QML Absolute Maximum Ratings (Note 1) ±7VDC +175°C +300°C V+ - VV+ - V- Supply Voltage Maximum Junction temperature (Note 2) Lead temperature (Soldering, 10 seconds) Differential input voltage Common mode input voltage -65°C ≤ TA ≤ +150°C 1.0W Storage temperature range Power Dissipation (Note 2) Short circuit current (Note 3) Thermal Resistance θJA Cerdip (Still Air) Cerdip (500LF/Min Air Flow) Ceramic SOIC (Still Air) Ceramic SOIC (500LF/Min Air Flow) 135°C/W 75°C/W 200°C/W 145°C/W θJC Cerdip Ceramic SOIC Package Weight (typical) Cerdip Ceramic SOIC ESD Tolerance (Note 4) 30°C/W 19°C/W TBD TBD 4000V Maximum Operating Ratings Supply Voltage Ambient Operating Temperture Range ±2.5V to ±6.0V -55°C ≤ TA ≤ +125°C Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description Temp (°C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 3 www.national.com LMH6628QML LMH6628QML Electrical Characteristics DC Parameters Static and DC Tests The following conditions apply, unless otherwise specified. VCC = +5VDC, AV = +2V, RL = 100Ω, RF = 100Ω, −55°C ≤ TA ≤ +125°C Symbol IB Parameter Conditions Notes Min Max Unit Subgroups (Note 7) -10 +10 μA 1 -20 +20 μA 2 -20 +20 μA 3 -2 +2 mV 1 -2.6 +2.6 mV 2, 3 24 mA 1 24 mA 2 25 mA 3 dB 1 Input Bias Current VIO Input Offset Voltage ICC Supply Current (Note 7) (Note 7) RL = ∞ PSRR Power Supply Rejection Ratio +VS = +4.0V to +5.0V, -VS = -4.0V to -5.0V VOUT Output Voltage Range RL = ∞ AC Parameters 60 dB 2, 3 -5.0 55 +5.0 V 1, 2, 3 Max Unit Subgroups MHz 4 Frequency Domain Response The following conditions apply, unless otherwise specified. VCC = +5VDC, AV = +2V, RL = 100Ω, RF = 100Ω, −55°C ≤ TA ≤ +125°C Symbol Parameter Conditions Notes Min SSBW Small Signal Bandwith -3 dB BW, VO < 0.5 VPP (Note 6) 50 GFP Gain Flatness Peaking 0.1 MHz to 200 MHz, (Note 6) 0.6 dB 4 GFR Gain Flatness Rolloff (Note 6) 0.6 dB 4 AOL Open Loop Gain dB 4 Max Unit Subgroups AC Parameters VO ≤0.5 VPP 0.1 MHz to 20 MHz, VO ≤0.5 VPP (Note 6) 55 Notes Min Distortion and Noise Tests The following conditions apply, unless otherwise specified. VCC = +5VDC, AV = +2V, RL = 100Ω, RF = 100Ω, −55°C ≤ TA ≤ +125°C Symbol Parameter Conditions HD2 Second Harmonic Distortion 1 VPPat10 MHz (Note 6) 50 dBc 4 HD3 Third Harmonic Distortion 1 VPPat10 MHz (Note 6) 60 dBc 4 DC Parameters Drift Values The following conditions apply, unless otherwise specified. Deltas not required on B Level product. Deltas required for S Level product at Group B5 only, or as specified on the Internal Processing Instructions (IPI). Notes Min Max Unit Subgroups Input Bias Current (Note 5) -1.0 +1.0 μA 1 VIO Input Offset Voltage (Note 5) -0.2 +0.2 mV 1 ICC Supply Current (Note 5) -1 +1 mA 1 Symbol Parameter IB www.national.com Conditions RL = ∞ 4 Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA. Note 4: Human body model, 1.5kΩ in series with 100pF. Note 5: If not tested, shall be guaranteed to the limits specified in table 1 Note 6: Group A testing only. Note 7: Pre and post irradiation limits are identical to those listed under electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MILSTD-883, Method 1019. Typical Performance Characteristics (TA = +25°, AV = +2, VCC = ±5V, RF =100Ω, RL = 100Ω, unless specified) Non-Inverting Frequency Response Inverting Frequency Response 20151515 20151513 Frequency Response vs. Load Resistance Frequency Response vs. Output Amplitude 20151510 20151525 5 www.national.com LMH6628QML Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. LMH6628QML Frequency Response vs. Capacitive Load Gain Flatness & Linear Phase 20151516 20151524 Channel Matching Channel to Channel Crosstalk 20151514 20151509 Pulse Response (VO = 2V) Pulse Response (VO = 100mV) 20151511 www.national.com 20151512 6 3rd Harmonic Distortion vs. Output Voltage 20151507 20151508 2nd & 3rd Harmonic Distortion vs. Frequency PSRR and CMRR (±5V) 20151522 20151517 PSRR and CMRR (±2.5V) Closed Loop Output Resistance (±2.5V) 20151523 20151518 7 www.national.com LMH6628QML 2nd Harmonic Distortion vs. Output Voltage LMH6628QML Closed Loop Output Resistance (±5V) Open Loop Gain & Phase (±2.5V) 20151519 20151521 Open Loop Gain & Phase (±5V) Recommended RS vs. CL 20151520 20151526 DC Errors vs. Temperature Maximum VO vs. RL 20151545 20151546 www.national.com 8 Voltage & Current Noise vs. Frequency 20151544 20151547 Settling Time vs. Accuracy 20151548 9 www.national.com LMH6628QML 2-Tone, 3rd Order Intermodulation Intercept LMH6628QML Output settling time when driving capacitive loads can be improved by the use of a series output resistor. See the plot labeled "RS vs. CL" in the Typical Performance section. Application Section LOW NOISE DESIGN Ultimate low noise performance from circuit designs using the LMH6628 requires the proper selection of external resistors. By selecting appropriate low valued resistors for RF and RG, amplifier circuits using the LMH6628 can achieve output noise that is approximately the equivalent voltage input noise multiplied by the desired gain (AV). of 2nV/ LAYOUT Proper power supply bypassing is critical to insure good high frequency performance and low noise. De-coupling capacitors of 0.1μF should be placed as close as possible to the power supply pins. The use of surface mounted capacitors is recommended due to their low series inductance. A good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitance from these nodes to ground causes frequency response peaking and possible circuit oscillation. See OA-15 for more information. National suggests the 730036 (SOIC) dual op amp evaluation board as a guide for high frequency layout and as an aid in device evaluation. DC BIAS CURRENTS AND OFFSET VOLTAGES Cancellation of the output offset voltage due to input bias currents is possible with the LMH6628. This is done by making the resistance seen from the inverting and non-inverting inputs equal. Once done, the residual output offset voltage will be the input offset voltage (VOS) multiplied by the desired gain (AV). National Application Note OA-7 offers several solutions to further reduce the output offset. ANALOG DELAY CIRCUIT (ALL-PASS NETWORK) The circuit in Figure 1 implements an all-pass network using the LMH6628. A wide bandwidth buffer (LM7121) drives the circuit and provides a high input impedance for the source. As shown in Figure 2, the circuit provides a 13.1ns delay (with R = 40.2Ω, C = 47pF). RF and RG should be of equal and low value for parasitic insensitive operation. OUTPUT AND SUPPLY CONSIDERATIONS With ±5V supplies, the LMH6628 is capable of a typical output swing of ±3.8V under a no-load condition. Additional output swing is possible with slightly higher supply voltages. For loads of less than 50Ω, the output swing will be limited by the LMH6628's output current capability, typically 85mA. 20151501 FIGURE 1. The circuit gain is +1 and the delay is determined by the following equations. (1) (2) where Td is the delay of the op amp at AV = +1. The LMH6628QML provides a typical delay of 2.8ns at its −3dB point. FULL DUPLEX DIGITAL OR ANALOG TRANSMISSION Simultaneous transmission and reception of analog or digital signals over a single coaxial cable or twisted-pair line can reduce cabling requirements. The LMH6628's wide bandwidth and high common-mode rejection in a differential amplifier configuration allows full duplex transmission of video, telephone, control and audio signals. In the circuit shown in Figure 3, one of the LMH6628's amps is used as a "driver" and the other as a difference "receiver" amplifier. The output impedance of the "driver" is essentially 20151502 FIGURE 2. Delay Circuit Response to 0.5V Pulse www.national.com 10 LMH6628QML zero. The two R's are chosen to match the characteristic impedance of the transmission line. The "driver" op amp gain can be selected for unity or greater. Receiver amplifier A2 (B2) is connected across R and forms differential amplifier for the signals transmitted by driver A2 (B2). If RF equals RG, receiver A2 (B1) will then reject the signals from driver A1 (B1) and pass the signals from driver B1 (A1). 20151505 FIGURE 5. The acquisition speed of this circuit is limited by the dynamic resistance of the diode when charging Chold. A plot of the circuit's performance is shown in Figure 6 with a 1MHz sinusoidal input. 20151503 FIGURE 3. The output of the receiver amplifier will be: (3) Care must be given to layout and component placement to maintain a high frequency common-mode rejection. The plot of Figure 4 shows the simultaneous reception of signals transmitted at 1MHz and 10MHz. 20151537 FIGURE 6. A current source, built around Q1, provides the necessary bias current for the second amplifier and prevents saturation when power is applied. The resistor, R, closes the loop while diode D2 prevents negative saturation when VIN is less than VC. A MOS-type switch (not shown) can be used to reset the capacitor's voltage. The maximum speed of detection is limited by the delay of the op amps and the diodes. The use of Schottky diodes will provide faster response. 20151531 FIGURE 4. POSITIVE PEAK DETECTOR The LMH6628's dual amplifiers can be used to implement a unity-gain peak detector circuit as shown in Figure 5. ADJUSTABLE OR BANDPASS EQUALIZER A "boost" equalizer can be made with the LMH6628 by summing a bandpass response with the input signal, as shown in Figure 7. 11 www.national.com LMH6628QML bination of Ra and Rb. Select Ra and Rb by either the 10Ω to 5kΩ criteria or by other requirements based on the impedance Vin is capable of driving. Finish the design by determining the value of K from Eq. 8. (7) Figure 8 shows an example of the response of the circuit of Figure 9, where fo is 2.3MHz. The component values are as follows: Ra=2.1kΩ, Rb = 68.5Ω, R2 = 4.22kΩ, R = 500Ω, KR = 50Ω, C = 120pF. 20151506 FIGURE 7. The overall transfer function is shown in Eq. 5. (4) To build a boost circuit, use the design equations Eq. 6 and Eq. 7. (5) (6) Select R2 and C using Eq. 6. Use reasonable values for high frequency circuits - R2 between 10Ω and 5kΩ, C between 10pF and 2000pF. Use Eq. 7 to determine the parallel com- www.national.com 20151543 FIGURE 8. 12 Section Changes 12/03/2010 Date Released Revision A New Corporate Format Release 1 MDS data sheet converted into a Corp. data sheet format. Following MDS data sheet will be Archived MNLMH6628-X-RH, Rev. 0A0 07/12/2011 B Connection Diagrams Replaced 8 Lead Cerdip (J) diagram depicting single Op Amp with diagram depicting dual Op Amp. Also Replaced 10 Lead Ceramic SOIC (WG) diagram depicting single Op Amp with diagram depicting dual Op Amp. 13 www.national.com LMH6628QML Revision History LMH6628QML Physical Dimensions inches (millimeters) unless otherwise noted 8 Lead Cerdip (J) NS Package Number J08A 10 Lead Ceramic SOIC (WG) NS Package Number WG10A www.national.com 14 LMH6628QML Notes 15 www.national.com LMH6628QML Dual Wideband, Low Noise, Voltage Feedback Op Amp Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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