MAXIM MAX1420CCM

19-1981; Rev 0; 5/01
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
♦ 67dB SNR at fIN = 5MHz
♦ 66dB SNR at fIN = 15MHz
♦ Internal +2.048V Precision Bandgap Reference
♦ Differential, Wideband Input T/H Amplifier
♦ Power-Down Modes:
218mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦ Space-Saving 48-Pin TQFP Package
Ordering Information
PART
48 TQFP
MAX1420ECM
-40°C to +85°C
48 TQFP
38
39
40
41
42
43
44
45
37
D9
D8
AGND
AVDD
1
36
2
35
AVDD
AGND
AGND
3
34
4
33
5
32
INP
INN
AGND
6
8
29
AGND
AVDD
AVDD
9
28
10
27
11
26
D5
D4
D3
AGND
12
25
D2
31
DVDD
DGND
DGND
24
23
22
D7
D6
DVDD
DGND
D0
D1
21
20
19
17
16
15
30
AGND
CLK
CLK
AGND
AVDD
DVDD
18
MAX1420
7
AGND
AVDD
AVDD
Functional diagram appears at end of data sheet.
46
48
AGND
AVDD
CML
REFN
REFP
REFIN
AVDD
AGND
PD
OE
D11
D10
Pin Configuration
13
Medical Ultrasound Imaging
CCD Pixel Processing
IR Focal Plane Arrays
Radar
IF & Baseband Digitization
PIN-PACKAGE
0°C to +70°C
The MAX1420 is available in a 7mm ✕ 7mm, 48-pin
TQFP package, and is specified over the commercial
(0°C to +70°C) and the extended industrial (-40°C to
+85°C) temperature range.
Pin-compatible lower speed versions of the MAX1420
are also available. Please refer to the MAX1421 data
sheet for 40Msps and the MAX1422 data sheet for
20Msps.
________________________Applications
TEMP. RANGE
MAX1420CCM
47
In addition to low operating power, the MAX1420 features two power-down modes: reference power-down
and shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, which
results in a typical 2mA supply current reduction. A full
shutdown mode is available to maximize power savings
during idle periods.
The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs.
♦ +3.3V Single Power Supply
14
The MAX1420, +3.3V, 12-bit analog-to-digital converter
(ADC) features a fully-differential input, pipelined, 12stage ADC architecture with wideband track-and-hold
(T/H) and digital error correction, incorporating a fullydifferential signal path. The MAX1420 is optimized for
low-power, high dynamic performance applications in
imaging and digital communications. The converter
operates from a single +3.3V supply, and consumes
only 221mW. The fully-differential input stage has a
small signal -3dB bandwidth of 400MHz and may be
operated with single-ended inputs.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal reference, or
externally applied buffered or unbuffered reference for
applications that require increased accuracy and a different input voltage range.
Features
48-TQFP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1420
General Description
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND..............................................-0.3V to +4V
DVDD, AVDD to DGND..............................................-0.3V to +4V
DGND to AGND.....................................................-0.3V to +0.3V
INP, INN, REFP, REFN, REFIN,
CML, CLK, CLK ....................(AGND - 0.3V) to (AVDD + 0.3V)
D0–D11, OE, PD .....................(DGND - 0.3V) to (DVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Ranges
MAX1420CCM ....................................................0°C to +70°C
MAX1420ECM .................................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK =
62.5MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity
Mid-scale Offset
Mid-scale Offset Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
RES
DNL
INL
12
TA = +25°C, no missing codes
-1
TA = TMIN to TMAX
±0.5
TA = TMIN to TMAX
MSO
±2
-3
GETC
.75
%FSR
%/°C
Internal reference (Note 1)
-5
±0.1
5
External reference applied to REFIN
(Note 2)
-5
±0.2
5
External reference applied to REFP,
CML, and REFN (Note 3)
-1.5
External reference applied to REFP,
CML, and REFN (Note 3)
LSB
LSB
3
3 x 10-4
MSOTC
GE
Bits
1
%FSR
1.5
100 x 106
%/°C
DYNAMIC PERFORMANCE (fCLK = 60MHz, 4096-point FFT)
Signal-to-Noise Ratio
SNR
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
THD
Signal-to-Noise and Distortion
SINAD
Effective Number of Bits
ENOB
Two-Tone
Intermodulation Distortion
2
IMD
fIN = 5MHz
fIN = 15MHz, TA =+25°C
67
62
66
64
72
fIN = 5MHz
fIN = 15MHz, TA =+25°C
72
fIN = 5MHz
-70
fIN = 15MHz, TA =+25°C
-69
fIN = 5MHz
64.5
fIN = 15MHz, TA =+25°C
dB
58.5
63
fIN = 5MHz
10.4
fIN = 15MHz
10.2
fIN1 = 11.566036MHz,
fIN2 = 13.4119138MHz (Note 4)
-74
_______________________________________________________________________________________
dB
-62
dB
dB
Bits
dBc
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK =
62.5MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Gain
DG
±1
%
Differential Phase
DP
±0.25
degrees
22
kΩ
ANALOG INPUTS (INP, INN, CML)
Input Resistance
RIN
Either input to ground
Input Capacitance
CIN
Either input to ground
Common-Mode Input Level
(Note 5)
Common-Mode Input Voltage
Range (Note 5)
4
pF
VCML
VAVDD
✕ 0.5
V
VCMVR
VCML
± 5%
V
Differential Input Range
VIN
±VDIFF
V
Small-Signal Bandwidth
BW-3dB
(Note 7)
400
MHz
Large-Signal Bandwidth
FPBW-3dB
(Note 7)
150
MHz
1
Clock
Cycle
Overvoltage Recovery
OVR
VINP - VINN (Note 6)
1.5 ✕ FS input
INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)
Common-Mode Reference
Voltage
VCML
At CML
VAVDD
✕ 0.5
V
Positive Reference Voltage
VREFP
At REFP
VCML
+ 0.512
V
Negative Reference Voltage
VREFN
At REFN
VCML
- 0.512
V
Differential Reference Voltage
VDIFF
VDIFF = VREFP - VREFN
1.024 ±5%
V
Differential Reference
Temperature Coefficient
±100
REFTC
ppm/°C
EXTERNAL REFERENCE (REFIN = +2.048V)
REFIN Input Resistance
RIN
REFIN Input Capacitance
CIN
10
pF
VREFIN
2.048
±10%
V
REFIN Reference Input Voltage
Differential Reference Voltage
VDIFF
(Note 8)
VDIFF = (VREFP - VREFN)
5
0.95 ✕
VREFIN/2
kΩ
VREFIN/2
1.05 ✕
VREFIN/2
V
200
µA
EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and CML)
REFP, REFN, CML Input Current
IIN
REFP, REFN, CML Input
Capacitance
CIN
-200
15
pF
_______________________________________________________________________________________
3
MAX1420
ELECTRICAL CHARACTERISTICS (continued)
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK =
62.5MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
Differential Reference Voltage
Range
VDIFF
CML Input Voltage Range
CONDITIONS
MIN
TYP
MAX
UNITS
1.024
±10%
V
VCML
1.65
±10%
V
REFP Input Voltage Range
VREFP
VCML +
VDIFF/2
V
REFN Input Voltage Range
VREFN
VCML VDIFF/2
V
VDIFF = VREFP - VREFN
DIGITAL INPUTS (CLK, CLK, PD, OE)
Input Logic High
VIH
Input Logic Low
VIL
0.7 x
VDVDD
CLK, CLK
Input Current
V
0.3 x
VDVDD
V
µA
±330
PD
-20
20
OE
-20
20
Input Capacitance
10
pF
DIGITAL OUTPUTS (D0–D11)
Output Logic High
VOH
IOH = 200µA
Output Logic Low
VOL
IOL = -200µA
Three-State Leakage
VDVDD
- 0.5
0
VDVDD
-10
Three-State Capacitance
V
0.5
V
10
µA
2
pF
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
3.135
3.3
3.465
V
Digital Supply Voltage
VDVDD
2.7
3.3
3.63
V
Analog Supply Current
IAVDD
67
78
mA
REFIN = AGND
66
76
mA
PD = DVDD
10
20
Analog Supply Current with
Internal Reference in Shutdown
Analog Shutdown Current
Digital Supply Current
IDVDD
Digital Shutdown Current
4
8
PD = VDVDD
µA
mA
20
µA
Power Dissipation
PDISS
Analog power dissipation
221
258
mW
Power Dissipation with Internal
Reference in Shutdown (Note 8)
PDISS
REFIN = AGND
218
251
mW
_______________________________________________________________________________________
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK =
62.5MHz (50% duty cycle), digital output load CL ≈ 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Dissipation In Shutdown
PDISS
PD = VDVDD
10
µW
Power-Supply Rejection Ratio
PSRR
(Note 9)
±1
mV/V
TIMING CHARACTERISTICS
Maximum Clock Frequency
fCLK
Clock High
tCH
Figure 6, clock period 16.667ns
60
8.33
ns
Clock Low
tCL
Figure 6, clock period 16.667ns
8.33
ns
Figure 6
7
fCLK
cycles
Pipeline Delay (Latency)
MHz
Aperture Delay
tAD
Figure 10
2
ns
Aperture Jitter
tAJ
Figure 10
2
ps
Data Output Delay
tOD
Figure 6
Bus Enable Time
tBE
Figure 5
5
ns
Bus Disable Time
tBD
Figure 5
5
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
5
10
14
ns
Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
External +2.048V reference applied to REFIN.
Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V.
IMD is measured with respect to either of the fundamental tones.
Specifies the common-mode range of the differential input signal supplied to the MAX1420.
VDIFF = VREFP - VREFN.
Input bandwidth is measured at a 3dB level.
VREFIN is internally biased to +2.048V through a 10kΩ resistor.
Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in VAVDD, using the internal reference.
Typical Operating Characteristics
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty
cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
-40
HD2
HD3
-80
-100
-40
HD2
-60
HD3
-80
-100
-120
5
10
15
20
25
ANALOG INPUT FREQUENCY (MHz)
30
fIN = 37.701219MHz
-20
-40
HD3
HD2
-60
-80
-100
-120
0
0
MAX1420 toc03
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
-20
fIN = 13.4119138MHz
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
AMPLITUDE (dB)
fIN = 5.5449583MHz
-60
0
MAX1420 toc01
0
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
MAX1420 toc02
FFT PLOT (8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
-120
0
5
10
15
20
25
ANALOG INPUT FREQUENCY (MHz)
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
MAX1420
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty
cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
DIFFERENTIAL INPUT
fIN2
fIN1
IMD3 IMD2
IMD3
-120
5
10
15
20
25
30
62
58
54
50
50
1
10
100
1
10
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (fIN = 15MHz)
85
MAX1420 toc07
-56
77
SFDR (dB)
-62
-68
-74
70
60
50
40
69
SNR (dB)
-50
MAX1420 toc08
0
MAX1420 toc06
66
54
-100
THD (dB)
62
58
IMD2
-80
MAX1420 toc05
66
MAX1420 toc09
-60
70
SINAD (dB)
-40
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
70
SNR (dB)
fIN1 = 11.566036MHz
fIN2 = 13.4119138MHz
AIN1 = AIN2 = -6.5dB FS
TWO TONE
ENVELOPE: -0.5dB FS
-20
AMPLITUDE (dB)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1420 toc04
0
61
30
20
10
53
0
-80
-10
45
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
-40 -30 -20
INPUT POWER (dB FS)
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (fIN = 15MHz)
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (fIN = 15MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (fIN = 15MHz)
100
70
60
10
-70
100
-20
MAX1420 toc10
80
1
-30
30
20
10
-10
0
70
60
SFDR (dB)
THD (dB)
40
-50
80
-40
50
-60
MAX1420 toc12
10
MAX1420 toc11
1
SINAD (dB)
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
-50
50
-60
40
-70
30
0
-80
-10
-70
6
-60
-50
-40
-30 -20
INPUT POWER (dB FS)
-10
0
20
-70
-60
-50
-40
-30 -20
INPUT POWER (dB FS)
-10
0
-70
-60
-50
-40 -30 -20
INPUT POWER (dB FS)
_______________________________________________________________________________________
-10
0
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
68
66
fIN = 15MHz
65
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
-65
fIN = 15MHz
-67
MAX1420 toc15
fIN = 15MHz
MAX1420 toc13
70
SIGNAL-TO-NOISE + DISTORTION
vs. TEMPERATURE
MAX1420 toc14
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
SNR (dB)
64
-69
THD (dB)
SINAD (dB)
64
66
63
-71
62
62
-73
61
60
60
-15
10
35
60
85
-75
-40
-15
10
35
60
-40
85
60
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.50
0.25
INL (LSB)
72
INL (LSB)
1
76
0
64
-15
10
35
60
-0.50
-2
85
0
-0.25
-1
68
0
1024
2048
3072
0
4096
1024
2048
3072
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE VREFIN = +2.048V
OFFSET ERROR vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
0
-0.125
-0.250
-0.50
-0.75
-1.00
-0.375
-0.500
-40
-15
10
35
TEMPERATURE (°C)
60
85
-1.25
-40
4096
MAX1420 toc21
63
IAVDD (mA)
-0.25
OFFSET ERROR (%FSR)
0.125
65
MAX1420 toc20
0
MAX1420 toc19
0.250
85
MAX1420 toc18
2
MAX1421 toc17
80
SFDR (dB)
35
TEMPERATURE (°C)
fIN = 15MHz
GAIN ERROR (%FSR)
10
TEMPERATURE (°C)
84
-40
-15
TEMPERATURE (°C)
MAX1420 toc16
-40
61
59
57
55
-15
10
35
TEMPERATURE (°C)
60
85
3.1
3.2
3.3
3.4
3.5
AVDD (V)
________________________________________________________________________________________
7
MAX1420
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty
cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty
cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
70
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
14
MAX1420 toc23
14
MAX1420 toc22
80
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1420 toc24
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
13
12
60
IDVDD (mA)
IDVDD (mA)
IAVDD (mA)
12
10
11
10
50
8
9
40
-15
10
35
60
85
2.7
2.9
3.0
3.2
3.3
3.5
3.6
-40
-15
10
35
60
TEMPERATURE (°C)
DVDD (V)
TEMPERATURE (°C)
ANALOG POWER-DOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
SNR, SINAD, THD, SFDR
vs. CLOCK FREQUENCY
0.12
0.08
0.09
0.06
0.03
0.04
SFDR
SINAD
40
MAX1420 toc27
60
SFDR, SNR, THD, SINAD (dB)
0.12
IDVDD (µA)
0.16
85
80
MAX1420 toc26
0.15
MAX1420 toc25
0.20
IAVDD (µA)
8
6
-40
SNR
20
fIN = 15MHz
0
-20
-40
THD
-60
0
3.20
3.30
3.40
-80
2.7
3.50
2.9
3.0
3.2
3.3
3.5
3.6
20
30
40
50
CLOCK FREQUENCY (MHz)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM
(DC INPUT)
2.025
3.2
3.3
AVDD (V)
3.4
3.5
115171
2.02
100,000
2.00
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
0
2 342
14538
200,000
2.038
MAX1420 toc30
300,000
2.04
53499
6113
2.050
COUNTS
VREF (dB)
400,000
2.06
387312
502186
500,000
153704
2.08
80
600,000
339785
MAX1420 toc28
2.10
2.063
8
70
DVDD (V)
2.075
3.1
60
AVDD (V)
MAX1420 toc29
0
3.10
VREF (V)
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
242 0
N-6 N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6
DIGITAL OUTPUT NOISE
_______________________________________________________________________________________
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
PIN
NAME
FUNCTION
1, 4, 5, 8,
9, 12, 13,
16, 19, 41,
48
AGND
Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10,
11, 14, 15,
20, 42, 47
AVDD
Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between AVDD and AGND.
6
INP
Positive Analog Signal Input
7
INN
Negative Analog Signal Input
17
CLK
Clock Frequency Input. Clock frequency input ranges from 100kHz to 60MHz.
18
CLK
Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is
driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.
21, 31, 32
DVDD
Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between DVDD and DGND.
22, 29, 30
DGND
Digital Ground
23–28
D0–D5
Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
33–38
D6–D11
Digital Data Outputs. D6 through D11, where D11 represents the MSB.
39
OE
Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A
logic “0” allows for the data bits to be read from the outputs.
40
PD
Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.
43
REFIN
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
44
REFP
Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFP should be biased to VCML + VDIFF / 2.
45
REFN
Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF / 2.
46
CML
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel
with 1nF.
_______________________________________________________________________________________
9
MAX1420
Pin Description
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
Detailed Description
The MAX1420 uses a 12-stage, fully-differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle, including the delay through the
output latch. The latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage. This process is
repeated until the signal has been processed by all 12
stages. Each stage provides a 1-bit resolution. Digital
error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing
codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuit
passes the input signal to the two capacitors C2a and
C2b through switches S4a and S4b. Switches S2a and
S2b set the common mode for the operational transcon-
ductance amplifier (OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and
C2b. Switches S4a and S4b are then opened before
S3a, S3b, S4C are closed. The OTA is used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. This value is then presented to
the first stage quantizer and isolates the pipeline from
the fast-changing input. The wide input bandwidth T/H
amplifier allows the MAX1420 to track and sample/hold
analog inputs of high frequencies beyond Nyquist. The
analog inputs INP to INN can be driven either differentially or single-ended. Match the impedance of INP and
INN and set the common-mode voltage to midsupply
(AVDD/2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1420 is determined by
the internally generated voltage difference between
REFP (AV DD /2 + V REFIN /4) and REFN (AV DD /2 VREFIN/4). The MAX1420’s full-scale range is adjustable
through REFIN, which provides high input impedance
for this purpose. REFP, CML (AVDD/2), and REFN are
internally buffered low impedance outputs.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal reference, or externally applied buffered or unbuffered reference for appli-
INTERNAL
BIAS
MDAC
VIN
Σ
T/H
x2
S5a
S2a
C1a
TO NEXT
STAGE
FLASH
ADC
CML
VOUT
S3a
DAC
S4a
2 BITS
OUT
C2a
S4c
VIN
S1
OTA
OUT
STAGE 1
STAGE 2
STAGE 12
S4b
C2b
C1b
S3b
DIGITAL CORRECTION LOGIC
S2b
12
MAX1420
D11–D0
Figure 1. Pipelined Architecture—Stage Blocks
10
MAX1420
INTERNAL
BIAS
S5b
CML
Figure 2. Internal Track-and-Hold Circuit
______________________________________________________________________________________
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
MAX1420
AVDD
50Ω
(AV2DD)
CML
R
0.22µF
1nF
AVDD
2
50Ω
R
(AV2DD
REFP
MAX4284
R
R
AVDD
2
0.22µF
0.5V
)
1nF
MAX1420
AVDD
4
R
50Ω
R
(
REFN AVDD- 0.5V
2
MAX4284
0.22µF
)
1nF
R
AVDD
4
REFIN
R
AGND
0.5V
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
cations that require increased accuracy and a different
input voltage range.
The MAX1420 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN and CML with a capacitor
network of 0.22µF in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is connected to AGND, thereby deactivating the on-chip
buffers of REFP, CML, and REFN. With their buffers
shut down, these nodes become high impedance and
can be driven by external reference sources, as shown
in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1420’s CLK and CLK inputs accept both differential and single-ended input operation and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). Sampling
occurs on the rising edge of the clock signal, requiring
this edge to have the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of
the ADC according to the following relationship:
SNRdB = 20 × log10
1
2π × fIN × t AJ
where fIN represents the analog input frequency and
tAJ is the aperture jitter. Clock jitter is especially critical
for high input frequency applications. The clock input
should always be considered as an analog signal and
routed away from any analog or digital signal lines.
The MAX1420 clock input operates with a voltage
threshold set to AVDD/2. Clock inputs must meet the
specifications for high and low periods as stated in the
Electrical Characteristics.
______________________________________________________________________________________
11
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
OE
INP
D11–D0
ADC
INN
AVDD
OUTPUT
DATA D11–D0
10kΩ
VALID DATA
HIGH-Z
Figure 5. Output Enable Timing
10kΩ
10kΩ
CLK
MAX1420
AGND
Figure 4. Simplified Clock Input Circuit
Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1420 clock input.
Output Enable (OE), Power-Down (PD)
and Output Data (D0–D11)
In addition to low operating power, the MAX1420 features two power-down modes: reference power-down
and shutdown mode. In reference power-down, the in-
Table 1. MAX1420 Output Code for
Differential Inputs
DIFFERENTIAL
INPUT VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET
BINARY
VREF × 2047/2048
+FULL SCALE 1LSB
1111 1111 1111
VREF × 2046/2048
+FULL SCALE 2LSB
1111 1111 1110
VREF × 1/2048
+ 1 LSB
1000 0000 0001
0
Bipolar Zero
1000 0000 0000
-VREF × 1/2048
- 1 LSB
0111 1111 1111
-VREF × 2046/2048
-FULL SCALE +
1 LSB
0000 0000 0001
-VREF × 2047/2048
-FULL SCALE
0000 0000 0000
* VREF = VREFP - VREFN
HIGH-Z
10kΩ
CLK
12
tBD
tBE
ternal bandgap reference is deactivated, which results in
a typical 2mA supply current reduction. A full shutdown
mode is available to maximize power savings during idle
periods.
The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs.
With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs
are latched at the last digital output code prior to the
power-down. All data outputs, D0 (LSB) through D11
(MSB), are TTL/CMOS logic-compatible. There is a
seven clock-cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF), to
avoid large digital currents that could feed back into
the analog portion of the MAX1420, thereby degrading
its performance. The use of buffers (e.g., 74LVCH16244)
on the digital outputs of the ADC can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1420,
add small-series resistors of 100Ω to the digital output
paths, close to the ADC.
Figure 5 displays the timing relationship between output enable and data output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and valid data output. The
MAX1420 samples the analog input signal on the rising
edge of CLK (falling edge of CLK) and output data is
valid seven clock cycles (latency) later.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for level
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associated
______________________________________________________________________________________
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
MAX1420
7 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
ANALOG INPUT
CLK
CLK
tOD
tCH
N-7
DATA OUTPUT
N-6
N-5
tCL
N-4
N-3
N-2
N-1
N
Figure 6. System and Output Timing Diagram
+5V
0.1µF
LOWPASS FILTER
INP
MAX4108
RISO
50Ω
0.1µF
300Ω
*CIN
22pF
0.1µF
-5V
MAX1420
600Ω
0.1µF
44pF*
600Ω
300Ω
CML
0.1µF
0.22µF
+5V
1nF
+5V
0.1µF
600Ω
INPUT
0.1µF
LOWPASS FILTER
MAX4108
300Ω
-5V
0.1µF
INN
MAX4108
RISO
50Ω
300Ω
-5V
*CIN
22pF
0.1µF
300Ω
300Ω
600Ω
*TWO CIN (22pF) CAPS MAY BE REPLACED BY
ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
______________________________________________________________________________________
13
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
25Ω
INP
22pF *
0.1µF
1
VIN
N.C. 2
3
T1
5
4
MAX1420
44pF *
6
CML
0.22µF
1nF
MINICIRCUITS
T1–1T–KK81
25Ω
22pF *
INN
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN
INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
with high-speed op amps. Select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 7, an
isolation resistor (RISO) of 50Ω is placed before the
capacitive load to prevent ringing and oscillation. The
22pF CIN capacitor acts as a small bypassing capacitor.
Connecting CIN from INN to INP may further improve
dynamic performance.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully differential signal, required by the MAX1420 for optimum
performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1420 provides better SFDR and THD
with fully differential input signals over single-ended
input signals, especially for very high input frequencies.
In differential input mode, even-order harmonics are suppressed and each input requires only half the signal
swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high speed, high bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
14
Grounding, Bypassing and
Board Layout
The MAX1420 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
1nF to AGND. AVDD should be bypassed with a similar
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
rules to bypass the digital supply DV DD to DGND.
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital ground (DGND) on the ADCs
package. Join the two ground planes at a single point,
such that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all
ground pins could share the same ground plane, if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces and
remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and
free of 90 degree turns.
_____________________________________________________________________________________
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
MAX1420
VIN
RISO
50Ω
0.1µF
INP
MAX4108
100Ω
1kΩ
CIN
22pF
MAX1420
CML
0.22µF
1nF
RISO
50Ω
100Ω
INN
CIN
22pF
Figure 9. Single-Ended AC-Coupled Input Signal
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
CLK
CLK
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
TRACK
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits):
SNRMAX = (6.02 x N + 1.76)dB
Figure 10. T/H Aperture Timing
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight-line. This straightline can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function once offset and gain errors have been nullified. The static linearity parameters for the MAX1420 are measured using the
best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
In reality, there are other noise sources besides quantization noise, e.g., thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB =
SINADdB −1.76dB
6.02dB
______________________________________________________________________________________
15
MAX1420
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
  2
2
2
2
  V2 + V3 + V4 + V5 
THDdB = 20 × log10 
V1









where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Functional Diagram
CLK
CLK
AVDD
MAX1420
AGND
INTERFACE
INP
PIPELINE ADC
T/H
INN
PD
BANDGAP
REFERENCE
OUTPUT
DRIVERS
DVDD
REF SYSTEM +
BIAS
REFIN REFP CML REFN
D11–D0
DGND
OE
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
______________________________________________________________________________________
16
12-Bit, 60Msps, +3.3V, Low-Power ADC
with Internal Reference
32L/48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1420
Package Information