FUJITSU MB89628RP-SH

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12517-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89628R/629R/P629
MB89628R/629R/P629
■ DESCRIPTION
The MB89628R/629R/P629 have been developed as a general-purpose version of the F2MC*-8L family
consisting of proprietary 8-bit, single-chip microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external
interrupt.
The MB89628R/629R/P629 are applicable to a wide range of applications from welfare to industrial equipment,
including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Large-size RAM
MB89P629: 4 Kbytes
MB89628R: 3 Kbytes
MB89629R: 3 Kbytes
• High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Instruction set optimized for controllers
Test and branch instructions
Bit manipulation instructions, etc.
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic QFP
(DIP-64P-M01)
(FPT-64P-M06)
(Continued)
MB89628R/629R/P629
(Continued)
• Four types of timers
8-bit PWM timer (also usable as a reload timer)
8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.)
16-bit timer/counter
20-bit time-base timer
• Two serial interfaces
Swichable the transfer direction allows communication with various equipment.
• 8-bit A/D converter
Sense mode function enabling comparison at 5 µs
Activation by an external input capable
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to reduce the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
2
MB89628R/629R/P629
■ PRODUCT LINEUP
Part number
Parameter
Classification
MB89628R
MB89629R
Mass production products
(mask ROM products)
MB89P629
One-time PROM
MB89PV620*1
Piggyback/evaluation
product for evaluation and product for evaluation and
development
development
32 K × 8 bits
ROM size
24 K × 8 bits
32 K × 8 bits
(internal PROM, programming
(internal mask ROM)
(internal mask ROM)
with general-purpose EPROM
32 K × 8 bits
(external ROM)
programmer)
RAM size
CPU functions
Ports
8-bit PWM timer
3072 × 8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
Input ports:
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
4096 × 8 bits
1 K × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs/10 MHz
3.6 µs/10 MHz
5 (4 ports also serve as peripherals.)
8 (All also serve as peripherals.)
8 (4 ports also serve as peripherals.)
8
24
53
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms)
8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms)
8-bit pulse width count
timer
16-bit timer/counter
8-bit serial I/O 1,
8-bit serial I/O 2
8-bit A/D converter
External interrupt
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation (Continuous measurement “H” pulse width/“L”
pulse width/from ↑ to ↑/from ↓ to ↓ capable)
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (Rising/falling/both edges selectability)
8-bits
LSB first/MSB first transfer selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
8-bit resolution × 8 channels
A/D conversion mode (conversion time: 18 µs)
Sense mode (conversion time: 5 µs)
Continuous activation by an external activation or an internal timer capable
Reference voltage input
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby modes
Process
Operating voltage*2
EPROM for use
Sleep mode, stop mode
CMOS
2.2 V to 6.0 V
2.7 V to 6.0 V
MBM27C256A-20
*1: The piggyback/evaluation product is applicable to the MB89620 series.
*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) In the case
of the MB89PV620, the voltage varies with the restrictions of the EPROM for use.
3
MB89628R/629R/P629
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89628R
MB89629R
MB89P629
Package
MB89PV620
DIP-64P-M01
×
FPT-64P-M06
×
MDP-64C-P02
×
MQP-64C-P01
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89P629, the program area starts from address 8007H but on the MB89PV620, MB89628R, and
MB89629R starts from 8000H. (On the MB89P629, addresses 8000H to 8006H comprise the option setting
area, option settings can be read by reading these addresses. On the MB89PV620, MB89628R, and
MB89629R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these
addresses in order to maintain compatibility of the MB89P629.)
2. Current Consumption
• In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics”.)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P40 to P47 on the MB89P629.
• A pull-up resistor is not selected for P50 to P57 when the A/D converter is used.
• Options are fixed on the MB89PV620.
4
MB89628R/629R/P629
■ PIN ASSIGNMENT
(Top view)
P36/WTO
P37/PTO
P40
P41
P42
P43
P44/BZ
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
RST
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P35/PWC
P34/EC
P33/SI1
P32/SO1
P31/SCK1
P30/ADST/CLKO
VSS
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
(DIP-64P-M01)
64
63
62
61
60
59
58
57
56
55
54
53
52
P44/BZ
P43
P42
P41
P40
P37/PTO
P36/WTO
VCC
P35/PWC
P34/EC
P33/SI1
P32/SO1
P31/SCK1
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P30/ADST/CLKO
VSS
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
20
21
22
23
24
25
26
27
28
29
30
31
32
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22
P21
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
(FPT-64P-M06)
5
MB89628R/629R/P629
■ PIN DESCRIPTION
Pin no.
SH-DIP
*1
*2
QFP
30
23
X0
31
24
X1
28
21
MOD0
29
22
MOD1
27
20
56 to 49
Circuit
type
Function
A
Cystal oscillator pins
B
Operating mode selection pins
Connect directly to VCC or VSS.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type. “L” is output from this
pin by an internal reset source. The internal circuit is
initialized by the input of “L”.
49 to 42
P00 to P07
D
General-purpose I/O ports
48 to 41
41 to 34
P10 to P17
D
40,
39
33,
32
P20,
P21
F
38,
37
31,
30
P22,
P23
D
36 to 33
29 to 26
P24 to P27
F
58
51
P30/ADST/
CLKO
E
General-purpose I/O port
Also serves as an A/D converter external activation and an
oscillation monitor clock output. This port is a hysteresis
input type.
59
52
P31/SCK1
E
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O 1.
This port is a hysteresis input type.
60
53
P32/SO1
E
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O 1. This
port is a hysteresis input type.
61
54
P33/SI1
E
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O 1. This
port is a hysteresis input type.
62
55
P34/EC
E
General-purpose I/O port
Also serves as the external clock input for the 16-bit timer/
counter. This port is a hysteresis input type.
63
56
P35/PWC
E
General-purpose I/O port
Also serves as the measured pulse input for the 8-bit pulse
width count timer. This port is a hysteresis input type.
1
58
P36/WTO
E
General-purpose I/O port
Also serves as the toggle output for the 8-bit pulse width
count timer. This port is a hysteresis input type.
*1: DIP-64P-M01
*2: FPT-64P-M06
6
Pin name
General-purpose output-only ports
(Continued)
MB89628R/629R/P629
(Continued)
Pin no.
SH-DIP
*1
*2
QFP
2
59
3 to 6
60 to 63
7
Pin name
Circuit
type
Function
P37/PTO
E
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM timer.
This port is a hysteresis input type.
P40 to P43
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
64
P44/BZ
G
N-ch open-drain I/O port
Also serves as a buzzer output. This port is a hysteresis
input type.
8
1
P45/SCK2
G
N-ch open-drain I/O port
Also serves as the clock I/O for the 8-bit serial I/O 2. This
port is a hysteresis input type.
9
2
P46/SO2
G
N-ch open-drain I/O port
Also serves as the data output for the 8-bit serial I/O 2. This
port is a hysteresis input type.
10
3
P47/SI2
G
N-ch open-drain I/O port
Also serves as the data input for the 8-bit serial I/O 2. This
port is a hysteresis input type.
11 to 18
4 to 11
P50/AN0 to
P57/AN7
H
N-ch open-drain output-only port
Also serves as the analog input for the A/D converter.
22 to 25
15 to 18
P60/INT0 to
P63/INT2
I
General-purpose input-only ports
Also serve as an external interrupt input. These ports are a
hysteresis input type.
26
19
P64
I
General-purpose input-only port
This port is a hysteresis input type.
64
57
VCC
—
Power supply pin
32,
57
25,
50
VSS
—
Power supply (GND) pins
19
12
AVCC
—
A/D converter power supply pin
20
13
AVR
—
A/D converter reference voltage input pin
21
14
AVSS
—
A/D converter power supply (GND) pin.
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01
*2: FPT-64P-M06
7
MB89628R/629R/P629
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
R
P-ch
• At an output pull-up resistor (P-ch) of approximately
50 MΩ/5.0 V
• CMOS hysteresis input
N-ch
D
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (except P22 and P23)
E
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
F
• CMOS output
P-ch
N-ch
(Continued)
8
MB89628R/629R/P629
(Continued)
Type
Circuit
Remarks
G
• N-ch open-drain output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(MB89628R and MB89629R only)
H
• N-ch open-drain output
• Analog input
R
P-ch
N-ch
Analog input
I
• Hysteresis input
R
• Pull-up resistor optional
9
MB89628R/629R/P629
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
10
MB89628R/629R/P629
■ PROGRAMMING TO THE EPROM ON THE MB89P629
The MB89P629 is an OTPROM version of the MB89628R and MB89629R.
1. Features
• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode, option area is diagrammed below.
Single chip
Address
0000H
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
0100H
RAM
Register
0200H
1080H
8000H
Not available
0000H
Option area
Option area
8007H
0007H
Program area
(EPROM)
32 KB
PROM
32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P629 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH
while operating as a single chip assign to 0000H to 7FFFH in EPROM mode. For information about each
corresponding option, see “7. Setting OTPROM Options.”)
(3) Program to 0000H to 7FFFH with the EPROM programmer.
11
MB89628R/629R/P629
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
DIP-64P-M01
ROM-64SD-28DP-8L
FPT-64P-M06
ROM-64QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
12
MB89628R/629R/P629
7. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Vacancy
8000H
(0000H)
Bit 6
Vacancy
Bit 5
Bit 4
Readable and
writable
1: Crystal
0: Ceramic
Reset pin
output
1: Yes
2: No
Vacancy
Oscillation
stabilization time
Readable and Readable and
writable
writable
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
reset
1: Yes
0: No
Vacancy
Vacancy
Readable and
writable
Readable and
writable
P07
8001H Pull-up
(0001H) 1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
P17
8002H Pull-up
(0002H) 1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
P37
8003H Pull-up
(0003H) 1: No
0: Yes
P36
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
P57
8004H Pull-up
(0004H) 1: No
0: Yes
P56
Pull-up
1: No
0: Yes
P55
Pull-up
1: No
0: Yes
P54
Pull-up
1: No
0: Yes
P53
Pull-up
1: No
0: Yes
P52
Pull-up
1: No
0: Yes
P51
Pull-up
1: No
0: Yes
P50
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
P63
Pull-up
1: No
0: Yes
P62
Pull-up
1: No
0: Yes
P61
Pull-up
1: No
0: Yes
P60
Pull-up
1: No
0: Yes
8005H
(0005H)
8006H
(0006H)
Readable and Readable and
writable
writable
Readable and
writable
P64
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Reserved bit
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Readable and
writable
Vacancy
Readable and Readable and
writable
writable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• Always write 0 to the reserved bit.
13
MB89628R/629R/P629
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32 (Rectangle)
Adapter socket part number
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in 32-Kbyte PROM on the EPROM programmer is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000H
0080H
I/O
RAM
0480H
8000H
Not available
0000H
Not available
Not available
0007H
8007H
EPROM
32 KB
PROM
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
14
MB89628R/629R/P629
■ BLOCK DIAGRAM
20-bit time-base timer
Clock controller
Reset circuit
(WDT)
RST
P00 to P07
8
P10 to P17
8-bit PWM timer
P37/PTO
8-bit pulse width
count timer
P36/WTO
P35/PWC
CMOS I/O port
Port 0 and port 1
8
Internal bus
Oscillator
Port 3
X0
X1
P34/EC
16-bit timer/counter
P33/SI1
P32/SO1
P31/SCK1
8-bit serial I/O 1
MOD0
MOD1
External bus
interface
P30/ADST/CLKO
CMOS output port
Buzzer output
P44/BZ
4
P40 to P43
N-ch open-drain I/O port
N-ch open-drain output port
8
F2MC-8L
CPU
8-bit A/D converter
Port 5
RAM
8
ROM
External interrupt
Other pins
VCC, VSS × 2
P50/AN0
to P57/AN7
AVR
AVCC
AVSS
4
4
Port 6
P20 to P27
P47/SI2
P46/SO2
P45/SCK2
8-bit serial I/O 2
Port 4
8
Port 2
CMOS I/O port
P60/INT0
to P63/INT3
P64
Input port
15
MB89628R/629R/P629
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89628R/629R/P629 offer a memory space of 64 Kbytes for storing all of I/O, data,
and program areas. The I/O area is located at the lowest address. The data area is provided immediately above
the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables
of interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89628R/629R/P629 is structured as illustrated below.
Memory Space
0000H
MB89PV620
0000H
I/O
MB89628R
I/O
0080H
0080H
RAM *
1 KB
0000H
1
0100H
0200H
I/O
RAM
3 KB
RAM
4 KB
0100H
0100H
Register
Register
Register
0200H
0200H
0C80H
0C80H
MB89P629
0080H
0080H
0100H
0000H
I/O
RAM
3 KB
Register
MB89629R
0200H
0480H
External area
Not available
8000H
Not available
8000H
1080H
8000H
8007H
Not available
Option area*2
A000H
External ROM
32 KB
ROM
32 KB
ROM
24 KB
FFFFH
FFFFH
FFFFH
ROM
32 KB
FFFFH
*1: The internal RAM of the MB89PV620 is 1 Kbyte. The RAM of a development tool can be substituted
for that RAM when the tool is connected. If the MB89PV620 is used as a piggyback product, however,
it runs out of RAM. Note, in addition, that some tools such as the MB2140 series cannot be used due
to mapping restrictions.
*2: Since addresses 8000H to 8006H for the MB89P629 comprise an option area, do not use this area for
the MB89PV620, MB89628R, and MB89629R.
16
MB89628R/629R/P629
3. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
17
MB89628R/629R/P629
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
18
MB89628R/629R/P629
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89628R and MB89629R. The bank currently
in use is indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
19
MB89628R/629R/P629
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
(R/W)
BCTR
External bus pin control register
06H
Vacancy
07H
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Time-base timer control register
Vacancy
0BH
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
BZCR
Buzzer register
10H
(R/W)
PDR5
Port 5 data register
11H
(R)
PDR6
Port 6 data register
12H
(R/W)
CNTR
PWM control register
13H
(W)
COMR
PWM compare register
14H
(R/W)
PCR1
PWC pulse width control register 1
15H
(R/W)
PCR2
PWC pulse width control register 2
16H
(R/W)
RLBR
PWC reload buffer register
17H
Vacancy
18H
(R/W)
TMCR
16-bit timer control register
19H
(R/W)
TCHR
16-bit timer count register (H)
1AH
(R/W)
TCLR
16-bit timer count register (L)
Vacancy
1BH
1CH
(R/W)
SMR1
Serial I/O 1 mode register
1DH
(R/W)
SDR1
Serial I/O 1 data register
1EH
(R/W)
SMR2
Serial I/O 2 mode register
1FH
(R/W)
SDR2
Serial I/O 2 data register
(Continued)
20
MB89628R/629R/P629
(Continued)
Address
Read/write
Register name
Register description
20H
(R/W)
ADC1
A/D converter control register 1
21H
(R/W)
ADC2
A/D converter control register 2
22H
(R/W)
ADCD
A/D converter data register
Vacancy
23H
24H
(R/W)
EIC1
External interrupt control register 1
25H
(R/W)
EIC2
External interrupt control register 2
26H
(R/W)
CLKE
Clock output control register
27H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Note: Do not use vacancies.
21
MB89628R/629R/P629
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
AVCC
VSS – 0.3
VSS + 7.0
V
*1
A/D converter reference input
voltage
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed AVCC + 0.3 V.
VI
VSS – 0.3
VCC + 0.3
V
Except P40 to P47*2
VI2
VSS – 0.3
VSS + 7.0
V
P40 to P47
VO
VSS – 0.3
VCC + 0.3
V
Except P40 to P47*2
VO2
VSS – 0.3
VSS + 7.0
V
P40 to P47
“L” level maximum output
current
IOL

20
mA
“L” level average output current
IOLAV

4
mA
“L” level total maximum output
current
∑IOL

100
mA
“L” level total average output
current
∑IOLAV

40
mA
“H” level maximum output
current
IOH

–20
mA
“H” level average output current
IOHAV

–4
mA
“H” level total maximum output
current
∑IOH

–50
mA
“H” level total average output
current
∑IOHAV

–20
mA
Power consumption
PD

300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Input voltage
Output voltage
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
*1: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
*2: VI and VO must not exceed VCC + 0.3 V.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
22
MB89628R/629R/P629
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Symbol
Parameter
VCC
AVCC
Power supply voltage
Value
Unit
Remarks
Min.
Max.
2.2*
6.0*
V
Normal operation assurance range*
(MB89628R/629R)
2.7*
6.0*
V
Normal operation assurance range*
(MB89P629/PV620)
1.5
6.0
V
Retains the RAM state in stop mode
A/D converter reference input
voltage
AVR
0.0
AVCC
V
Operating temperature
TA
–40
+85
°C
* : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics.”
Operating voltage (V)
6
Analog accuracy
assured in the
AVCC = VCC = 3.5 V to 6.0 V range
5
Operation assurance range
4
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Clock operating frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
0.8
0.4
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89628R/629R.
Figure 1
Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
23
MB89628R/629R/P629
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
“H” level input
voltage
“H” level output
voltage
“L” level output
voltage
Input leakage
current
(Hi-z output
leakage
current)
Pull-up
resistance
Condition
Value
Min.
Typ.
Max.
Unit
VIH
P00 to P07,
P10 to P17,
P22, P23

0.7 VCC

VCC + 0.3
V
VIHS
RST, MOD0,
MOD1,
P30 to P37,
P60 to P64

0.8 VCC

VCC + 0.3
V
VIHS2
P40 to P47

0.8 VCC

VSS + 6.0
V
VIL
P00 to P07,
P10 to P17,
P22, P23

VSS − 0.3

0.3 VCC
V
VILS
RST, MOD0,
MOD1,
P30 to P37,
P40 to P47,
P60 to P64
—
VSS − 0.3

0.2 VCC
V
VD
P50 to P57
—
VSS − 0.3

VSS + 0.3
V
VD2
P40 to P47

VSS − 0.3

VSS + 6.0
V
VOH
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
IOH = –2.0 mA
4.0


V
VOL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50 to P57


0.4
V
VOL2
RST
—
—
0.4
V
ILI1
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P64,
MOD0, MOD1
0.0 V < VI < VCC


±5
µA
RPULL
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P47,
P50 to P57,
P60 to P64,
RST
VI = 0.0 V
25
50
100
kΩ
“L” level input
voltage
Open-drain
output pin
application
voltage
Pin
Symbol
IOL = +4.0 mA
Remarks
Without pull-up
resistor
(Continued)
24
MB89628R/629R/P629
(Continued)
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
Condition
FC = 10 MHz
Normal
operation
mode
ICC
Value
Unit
Remarks
Min.
Typ.
Max.
—
9
15
mA
—
10
18
mA MB89P629
—
3
4
mA
MB89628R,
MB89629R
(External clock)
VCC
ICCS
FC = 10 MHz
Sleep mode
(External clock)
Power supply
current*
ICCH
Stop mode
TA = +25°C
—
—
1
µA
IA
FC = 10 MHz,
when A/D
conversion
is activated
—
1
3
mA
FC = 10 MHz,
TA = +25°C,
when A/D
conversion
is stopped
—
—
1
µA
f = 1 MHz
—
10
—
pF
AVCC
IAH
Input
capacitance
CIN
Other than
AVCC, AVSS,
VCC, and VSS
* : In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included.
The power supply current is measured at the external clock.
25
MB89628R/629R/P629
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
RST “L” pulse width
Value
Condition
tZLZH
—
Min.
Max.
16 tXCYL
—
Unit
Remarks
ns
Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tOFF
tR
2.0 V
VCC
0.2 V
26
0.2 V
0.2 V
MB89628R/629R/P629
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Pin
Value
Condition
Min.
Max.
Unit
Remarks
Clock frequency
FC
X0, X1
1
10
MHz
Clock cycle time
tXCYL
X0, X1
100
1000
ns
Input clock pulse width
PWH
PWL
X0
20
—
ns
External clock
Input clock rising/falling
time
tCR
tCF
X0
—
10
ns
External clock
—
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCR
0.8 VCC
tCF
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symbol
tinst
Value (typical)
Unit
Remarks
4/FC
µs
tinst = 0.4 µs when operating at
FC = 10 MHz
27
MB89628R/629R/P629
(5) Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
Serial clock cycle time
tSCYC
SCK1, SCK2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
tSHIX
SCK1, SI1
SCK2, SI2
Serial clock “H” pulse width
tSHSL
SCK1, SCK2
1 tinst*
—
µs
Serial clock “L” pulse width
tSLSH
SCK1, SCK2
1 tinst*
—
µs
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
0
200
ns
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
1/2 tinst*
—
µs
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
tSHIX
SCK1, SI1
SCK2, SI2
1/2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
28
Condition
Internal shift
clock mode
External shift
clock mode
Remarks
MB89628R/629R/P629
Internal Shift Clock Mode
tSCYC
SCK1
SCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO1
SO2
0.8 V
tIVSH
SI1
SI2
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
tSLSH
SCK1
SCK2
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO1
SO2
2.4 V
0.8 V
tIVSH
SI1
SI2
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
29
MB89628R/629R/P629
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Peripheral input “H” pulse width 2
tILIH2
Peripheral input “L” pulse width 2
tIHIL2
Peripheral input “H” pulse width 2
tILIH2
Peripheral input “L” pulse width 2
tIHIL2
Pin
Condition
PWC,
EC, INT0
to INT3
—
A/D mode
ADST
Sense mode
Value
Max.
2 tinst*
—
µs
2 tinst*
—
µs
32 tinst*
—
µs
32 tinst*
—
µs
8 tinst*
—
µs
8 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
PWC
EC
INT0 to INT3
tILIH1
0.2 VCC
0.2 VCC
tIHIL2
tILIH2
0.8 VCC
ADST
0.2 VCC
30
0.8 VCC
0.8 VCC
0.2 VCC
Unit
Min.
0.8 VCC
Remarks
MB89628R/629R/P629
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Typ.
Max.
—
—
8
bit
—
—
±1.5
LSB
—
—
±1.0
LSB
—
—
±0.9
LSB
AVSS – 1.0 LSB
AVSS + 0.5 LSB
AVSS + 2.0 LSB
mV
AVR – 3.0 LSB
AVR – 1.5 LSB
AVR
mV
—
—
0.5
LSB
—
44 tinst*
—
µs
—
12 tinst*
—
µs
AN0 to
—
—
10
µA
AN7
0.0
—
AVR
V
0.0
—
AVCC
V
—
100

µA
—
—
1
µA
—
—
Linearity error
Differential linearity error
Zero transition voltage
VOT
Full-scale transition
voltage
VFST
AVR = AVCC
—
Interchannel disparity
A/D mode conversion
—
time
Sense mode conversion
time
Analog port input current
—
IAIN
Analog input voltage
—
Reference voltage
—
Unit
Min.
Resolution
Total error
Value
Remarks
AVR = 5.0 V,
when A/D
IR
conversion
AVR
Reference voltage
supply current
activated
AVR = 5.0 V,
IRH
when A/D
conversion
stopped
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
31
MB89628R/629R/P629
Digital output
1111
1111
Theoretical conversion value
1111
1110
Actual conversion value
(1 LSB × N + VOT)
1 LSB =
Linearity error =
Differential linearity error =
Total error =
0000
0000
0000
AVR
256
VNT – (1 LSB × N + VOT)
1 LSB
V( N + 1 ) T – VNT
–1
1 LSB
VNT – (1 LSB × N + 1 LSB)
1 LSB
0010
0001
0000
VOT
VNT
V (N + 1)T
VFST
Analog input
(2) Precautions
• Input impedance of the analog input pins
The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the
sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
C = 33 pF
Analog input pin
If the analog input
impedance is
higher than 10 kΩ,
it is recommended
to connect an
external capacitor
of approx. 0.1 µF.
Comparator
R = 6 kΩ
. 8 instruction cycles
Close for
.
after activating A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
32
MB89628R/629R/P629
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
33
MB89628R/629R/P629
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
34
MB89628R/629R/P629
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
35
MB89628R/629R/P629
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
36
MB89628R/629R/P629
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
37
L
38
B
C
D
E
F
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
5
ADDC
A
SUBC
A
XCH
XOR
AND
OR
A, T
A
A
A
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
C
D
E
F
rel
rel
rel
rel
B
MOVW XCHW
IX,#d16
A,IX
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
MOVW
MOVW
A,@IX +d @IX +d,A
A
CLRB
BBC
dir: 6 dir: 6,rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
CMP
@IX +d,#d8 @IX +d,#d8
9
MOV
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
OR
A,@IX +d
8
XOR
AND
A,@IX +d A,@IX +d
MOV
CMP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
CLRB
BBC
MOVW MOVW MOVW XCHW
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
MOV @IX
+d,A
7
SUBC
A,@IX +d
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
MOV
A,@IX +d
ADDC
A,@IX +d
DAS
6
CMP
A,@IX +d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
CMPW ADDCW SUBCW XCHW XORW ANDW ORW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
A
A
SETC
4
A
CMP
PUSHW POPW MOV
JMP
CALL
MOVW CLRC
IX
addr16 addr16
IX
ext,A
PS,A
RORC
A
DIVU
3
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
ROLC
A
SETI
7
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
6
9
5
8
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89628R/629R/P629
■ INSTRUCTION MAP
MB89628R/629R/P629
■ MASK OPTIONS
Model
MB89628R/
MB89629R
MB89P629
MB89PV620
Specifying procedure
Specify when
ordering masking
Set with EPROM
programmer
Setting not
possible
No.
1
2
Selectable per pin. Can be set per pin.
Pull-up resistors
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P64
(P50 to P57 must be set (P40 to P47 are
Power-on reset
With power-on reset
Without power-on reset
available only for
resistor when an A/D
without a pull-up
converter is used.)
resistor.)
Selectable
Setting possible
Fixed to with
power-on reset
Selectable
Setting possible
Fixed to crystal
oscillator of 218/FC
Selectable
Setting possible
Fixed to with reset
output
Oscillation stabilization time selection
3
Crystal oscillator: (218/FC) (26.2 ms/10 MHz)
14
Ceramic oscillator: (2 /FC) (1.64 ms/10 MHz)
4
Reset pin output
With reset output
Without reset output
Fixed to without
pull-up resistor
to without a pull-up
■ ORDERING INFORMATION
Part number
MB89628RP-SH
MB89629RP-SH
MB89P629P-SH
MB89628RPF
MB89629RPF
MB89P629PF
Package
Remarks
64-pin Plastic SH-DIP
(DIP-64P-M01)
64-pin Plastic QFP
(FPT-64P-M06)
MB89PV620C-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV620CF
64-pin Ceramic MQFP
(MQP-64C-P01)
39
MB89628R/629R/P629
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
+0.22
58.00 –0.55
+.008
2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
5.65(.222)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
1.00 –0
+.020
.039 –0
0.45±0.10
(.018±.004)
0.51(.020)MIN
15°MAX
19.05(.750)
TYP
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
40
1994 FUJITSU LIMITED D64001S-3C-4
55.118(2.170)REF
Dimensions in mm (inches)
MB89628R/629R/P629
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
3.35(.132)MAX
20.00±0.20(.787±.008)
51
0.05(.002)MIN
(STAND OFF)
33
52
32
14.00±0.20
(.551±.008)
18.70±0.40
(.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
20
64
"A"
LEAD No.
19
1
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
0.15±0.05(.006±.002)
0.20(.008)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F64013S-3C-2
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
0 10°
1.20±0.20
(.047±.008)
Dimensions in mm (inches)
41
MB89628R/629R/P629
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
INDEX AREA
2.54±0.25
(.100±.010)
33.02(1.300)REF
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
42
19.05±0.30
(.750±.012)
1994 FUJITSU LIMITED M64002SC-1-4
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
Dimensions in mm (inches)
MB89628R/629R/P629
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
1994 FUJITSU LIMITED M64004SC-1-3
10.82(.426)
0.15±0.05 MAX
(.006±.002)
Dimensions in mm (inches)
43
MB89628R/629R/P629
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 1015, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 189554
Tel: 336-1600
Fax: 336-1609
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9606
 FUJITSU LIMITED Printed in Japan
44