MOTOROLA MTE30N50E

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SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
30 AMPERES
500 VOLTS
RDS(on) = 0.150 OHM
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche mode and switch efficiently. This new
energy design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, PWM motor controls, and other
inductive loads. The avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
• 2500 V RMS Isolated ISOTOP Package
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• Very Low Internal Parasitic Inductance
• IDSS and VDS(on) Specified at Elevated Temperature
• U.L. Recognized, File #E69369

4
1
3
2
D
G
SOT–227B
S
1.
2.
3.
4.
Source
Gate
Drain
Source 2
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
500
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
500
Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
30
12
80
Adc
Total Power Dissipation @ 25°C
Derate above 25°C
PD
250
2.0
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
Rating
Operating and Storage Temperature Range
Apk
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL= 30 Apk, L = 10 mH, RG = 25 Ω)
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.5
62.5
°C/W
TL
260
°C
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
mJ
3000
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
ISOTOP is a trademark of SGS–THOMSON Microelectronics.
Preferred devices are Motorola recommended choices for future use and best overall value.
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MTE30N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
500
—
560
566
—
—
—
—
—
—
10
200
—
—
100
2.0
—
3.2
7.0
4.0
—
mV/°C
—
0.13
0.15
Ohms
—
—
4.1
—
5.0
7.0
gFS
17
—
—
mhos
Ciss
—
7200
10080
pF
Coss
—
775
1200
Crss
—
120
250
td(on)
—
32
60
tr
—
105
175
td(off)
—
160
275
tf
—
115
200
QT
—
235
350
Q1
—
35
—
Q2
—
110
—
Q3
—
65
—
—
—
0.95
0.88
1.2
—
trr
—
485
—
ta
—
312
—
tb
—
173
—
QRR
—
8.2
—
µC
Internal Drain Inductance
LD
—
5.0
—
nH
Internal Source Inductance
LS
—
5.0
—
nH
Characteristic
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 15 Adc)
RDS(on)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 30 Adc)
(VGS = 10 Vdc, ID = 15 Adc)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 250 Vdc, ID = 30 Adc,
VGS = 10 Vdc,
RG = 4.7 Ω)
Fall Time
Gate Charge
(see figure 8)
(VDS = 400 Vdc, ID = 30 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 30 Adc, VGS = 0 Vdc)
(IS = 30 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTE30N50E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25°C
50
I D , DRAIN CURRENT (AMPS)
60
VGS = 10 V
8V
6V
40
30
5V
20
VDS ≥ 10 V
50
I D , DRAIN CURRENT (AMPS)
60
40
30
100°C
20
10
10
25°C
4V
0
TJ = – 55°C
0
0
4
8
2
6
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
12
2
0.35
VGS = 10 V
0.3
TJ = 100°C
0.25
0.2
25°C
0.15
0.1
– 55°C
0.5
0
0
10
20
30
40
ID, DRAIN CURRENT (AMPS)
6.5
7
50
60
0.17
TJ = 25°C
0.16
0.15
VGS = 10 V
0.14
15 V
0.13
0.12
0
Figure 3. On–Resistance versus Drain Current
and Temperature
2.5
10
20
30
40
ID, DRAIN CURRENT (AMPS)
50
60
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
10000
VGS = 10 V
ID = 15 A
VGS = 0 V
TJ = 125°C
2
1000
I DSS, LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
3
4
3.5
4.5
5.5
5
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 1. On–Region Characteristics
2.5
1.5
1
100
25°C
10
0.5
0
– 50
100°C
– 25
25
75
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
1
0
100
200
300
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
500
Figure 6. Drain–To–Source Leakage Current
versus Voltage
3
MTE30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
100000
24000
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
20000
VGS = 0 V
16000
12000
Crss
Ciss
8000
Coss
4000
0
10
Crss
5
0
VGS
5
10
15
20
25
10000
Ciss
1000
Coss
100
10
10
Crss
100
1000
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
TJ = 25°C
DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
600
QT
10
500
8
VGS
Q1
6
400
Q2
300
4
200
ID = 30 A
TJ = 25°C
2
0
VDS
Q3
0
50
100
150
Qg, TOTAL GATE CHARGE (nC)
200
100
0
250
10000
t, TIME (ns)
12
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTE30N50E
VDD = 250 V
ID = 30 A
VGS = 10 V
TJ = 25°C
1000
td(off)
tf
tr
100
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and
Drain–To–Source Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
9
30
QRR, STORED CHARGE (µ C)
8
I S , SOURCE CURRENT (AMPS)
dlS/dt = 100 A/µs
VDD = 50 V
TJ = 25°C
7
6
5
4
3
2
0
6
12
18
24
30
VGS = 0 V
TJ = 25°C
20
10
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
IS, SOURCE CURRENT (AMPS)
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Stored Charge
Figure 11. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
MTE30N50E
SAFE OPERATING AREA
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
VGS = 20 V
SINGLE PULSE
TC = 25°C
100 µs
10
1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
10
1
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
3000
ID = 30 A
2500
2000
1500
1000
500
0
1000
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
25
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTE30N50E
PACKAGE DIMENSIONS
A
H
B
L
C
R
Q
G
4
3
1
2
M N
P
D
E
F
S
" 0.2 Nm
STYLE 1:
PIN 1.
2.
3.
4.
Recommended screw torque: 1.3
Maximum screw torque: 1.5 Nm
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
DIM
A
B
C
D
E
F
G
H
L
M
N
P
Q
R
S
MILLIMETERS
MIN
MAX
31.50
31.70
7.80
8.20
4.10
4.30
14.90
15.10
30.10
30.30
38.00
38.20
4.00
11.80
12.20
8.90
9.10
12.60
12.80
25.20
25.40
1.95
2.05
4.10
0.75
0.85
5.50
INCHES
MIN
MAX
1.240
1.248
0.307
0.322
0.161
0.169
0.586
0.590
1.185
1.193
1.496
1.503
0.157
0.464
0.480
0.350
0.358
0.496
0.503
0.992
1.000
0.076
0.080
0.157
0.030
0.033
0.217
SOURCE
GATE
DRAIN
SOURCE 2
SOT–227B
Motorola TMOS Power MOSFET Transistor Device Data
7
MTE30N50E
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8
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*MTE30N50E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTE30N50E/D