ONSEMI NB100LVEP91MN

NB100LVEP91
2.5V / 3.3V Any Level
Positive Input to −2.5V /
−3.3V / −5V NECL Output
Translator
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
NECL output signals (-2.5 V / -3.3 V / -5 V).
To accomplish the level translation the LVEP91 requires three
power rails. The VCC supply should be connected to the positive
supply, and the VEE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
VEE and VCC should be bypassed to ground via 0.01 F capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
• Typical Maximum Frequency > 2.0 GHz
• 430 ps Typical Propagation Delay
• Operating Range: VCC = 2.375 V to 3.8 V;
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MARKING
DIAGRAM*
20
20
1
1
24
1
24
N100
LP91
ALYW
1
24 PIN QFN
MN SUFFIX
CASE 485L
A
WL, L
YY, Y
WW, W
VEE = -2.375 V to -5.5 V; GND = 0 V
NB100LVEP91
AWLYYWW
SO-20
DW SUFFIX
CASE 751D
= Assembly Location
= Wafer Lot
= Year
= Work Week
• Q Output will Default LOW with Inputs Open or at GND
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2003
January, 2003 - Rev. 2
1
Device
Package
Shipping
NB100LVEP91DW
SO-20
38 Units/Rail
NB100LVEP91DWR2
SO-20
1000/Tape & Reel
NB100LVEP91MN
QFN-24
93 Units/Rail
NB100LVEP91MNR2
QFN-24
3000/Tape & Reel
Publication Order Number:
NB100LVEP91/D
NB100LVEP91
Positive Level
Input
NECL Output
D0
Q0
D0
PIN DESCRIPTION
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
FUNCTION
PIN
Dn*, Dn**
Qn, Qn
VBB
VCC
VEE
GND
NC
VCC
VBB
GND
VEE
Any Level Inputs
ECL Outputs
PECL Reference Voltage Output
Positive Supply (2.5 V, 3.3 V)
Negative Supply (-2.5 V, -3.3 V, -5 V)
Ground
No Connect
*Pins will default differentially LOW when left open.
**Pins will default to VCC/2 when left open.
GND GND Q1
24
Figure 1. Logic Diagram
VCC Q0
Q0 GND Q1 Q1 GND Q2
Q2 NC
20
18
12
19
17
16
15
14
13
11
NB100LVEP91
1
2
3
VCC
D0
D0 VBB D1
4
5
6
7
8
D1 VBB D2
9
10
D2
VEE
23
Q1 GND GND
22
21
20
19
Q0
1
18
Q2
Q0
2
17
Q2
VCC
3
16
VEE
VCC
4
15
VEE
D0
5
14
D2
D0
6
13
D2
NB100LVEP91
7
VBB
8
9
D1
D1
10
11
NC VBB
12
VCC
Warning: All VCC, VEE, and GND pins must be externally connected to Power Supply to guarantee proper operation.
Warning: All VCC, VEE, and GND pins must be externally connected to Power Supply to guarantee proper operation.
The thermally conductive exposed pad on package bottom
(see case drawing) must be attached to a heat-sinking conduit.
Figure 2. SOIC-20 Lead Pinout (Top View)
Figure 3. QFN-24 Lead Pinout (Top View)
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
75 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 150 V
> 2 kV
Level 1
UL 94 V-0 @ 0.125 in
446 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
NB100LVEP91
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Power Supply
GND = 0 V
3.8 to 0
V
VEE
NECL Power Supply
GND = 0 V
-5.5 to 0
V
VI
PECL Input Voltage
GND = 0 V
VI VCC
3.8 to 0
V
VOP
Operating Voltage
GND = 0 V
VCC - VEE
9.3 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
PECL VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
JESD 51-3 (1S-Single Layer Test Board)
0 lFPM
500 LFPM
20 SOIC
20 SOIC
90
60
°C/W
°C/W
JA
Thermal Resistance (Junction-to-Ambient)
JESD 51- 6 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 LFPM
24 QFN
47.3
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
20 SOIC
30 to 35
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL INPUT DC CHARACTERISTICS VCC = 2.5 V, VEE = -2.375 to -5.5 V, GND = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
10
14
20
10
14
20
10
14
20
mA
ICC
Power Supply Current
VIH
Input HIGH Voltage
1335
VCC
1335
VCC
1275
VCC
mV
VIL
Input LOW Voltage
GND
875
GND
875
GND
875
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 4)
0
2.5
0
2.5
0
2.5
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
D
D
150
0.5
-150
0.5
-150
A
0.5
-150
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / -0.125 V.
4. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
LVPECL INPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = -2.375 V to -5.5 V; GND = 0 V (Note 5)
-40 °C
Symbol
Characteristic
Min
Typ
10
16
25°C
Max
Min
Typ
16
85°C
Max
Min
Typ
16
Max
Unit
ICC
VCC Power Supply Current
24
10
24
10
24
mA
VIH
Input HIGH Voltage (Single-Ended)
2135
VCC
2135
VCC
2135
VCC
mV
VIL
Input LOW Voltage (Single-Ended)
GND
1675
GND
1675
GND
1675
mV
VBB
Output Voltage Reference (Note 6)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential) (Note 6)
3.3
0
3.3
0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1875
0
150
D
D
0.5
-150
1875
150
0.5
-150
0.5
-150
1875
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
5. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / -0.925 V.
6. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
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3
NB100LVEP91
NECL OUTPUT DC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -5.5 V; GND = 0 V (Note 7)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
38
50
68
38
50
68
mA
IEE
VEE Power Supply Current
VOH
Output HIGH Voltage (Note 8)
-1 145
-1020
-895
-1 145
1020
-895
-1030
-1020
-895
mV
VOL
Output LOW Voltage (Note 8)
-1945
-1725
-1600
-1945
-1725
-1600
-1945
-1725
-1600
mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Output parameters vary 1:1 with GND.
8. All loading with 50 resistor to GND-2 volts.
AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -5.5 V; GND = 0 V
-40 °C
Symbol
25°C
Min
Typ
fin < 1.0 GHz
fin < 1.5 GHz
575
525
800
750
Differential
Single-Ended
375
300
500
450
600
650
Characteristic
Max
85°C
Min
Typ
Max
600
525
800
750
375
300
500
450
600
675
Min
Typ
Max
550
400
800
750
400
300
550
500
650
750
ps
Unit
Vopp
Output Voltage Amplitude
(Figure 4)
tPLH
tPHL0
Propagation Delay
D to Q
tSKEW
Pulse Skew (Note 9)
Output-to-Output (Note 10)
Part-to-Part (Diff) (Note 10)
15
25
50
75
95
125
15
30
50
75
105
125
15
30
70
80
105
150
ps
tJITTER
RMS Random Clock Jitter (Note 11)
fin = 2.0 GHz
Peak-to-Peak Data Dependant Jitter fin = 2.0 Gbps
(Note 12)
0.5
20
2.0
0.5
20
2.0
0.5
20
2.0
ps
VPP
Input Voltage Swing (Note 13)
200
800
1200
200
800
1200
200
800
1200
mV
tr, tf
Output Rise/Fall Times Q
(20% - 80%)
75
150
250
75
150
250
75
150
275
ps
9. Pulse Skew = |tPLH - tPHL|
10. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
11. RMS Jitter with 50% Duty Cycle Input Clock Signal.
12. Peak-to-Peak Jitter with input NRZ PRBS 231- 1 at 2.0 Gbps.
13. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of ≈ 50.
850
10
8.0
Q AMP
7.0
650
6.0
5.0
550
4.0
450
3.0
2.0
350
1.0
RMS JITTER
250
0.5
1.0
1.5
FREQUENCY (GHz)
Figure 4.
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4
2.0
0
2.5
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
9.0
750
mV
NB100LVEP91
Application Information
and the maximum input swing of 3.0 V. Within these
conditions, the input voltage can range from VCC to GND.
Examples interfaces are illustrated below in a 50 environment (Z = 50 )
All NB100LVEP91 inputs can accept LVPECL, LVTTL,
LVCMOS, HSTL, CML, or LVDS signal levels. The
limitations for differential input signal (LVDS, HSTL,
LVPECL, or CML) are the minimum input swing of 150 mV
VCC
Z
VCC
LVPECL91
LVDS
Driver
VCC
Z
D
LVPECL
Driver
50 D
Z
D
50 GND
VTT = VCC - 2.0 V
VEE
GND
Figure 5. Standard LVPECL Interface
VCC
GND
VCC
Z
Z
D
LVPECL91
50 D
CML
Driver
D
Z
VCC
VCC
50 HSTL
Driver
VEE
Figure 6. Standard LVDS Interface
VCC
50 LVPECL91
100 D
Z
GND
VCC
LVPECL91
Z
D
50 GND
GND
VEE
GND
GND
VEE
GND
Figure 8. Standard 50 Load CML Interface
Figure 7. Standard HSTL Interface
VCC
Z
GND
VCC
LVPECL91
LVCMOS
Driver
D
LVTTL
Driver
1.5 V
(Reference Voltage)
VCC
VCC
Z
D
LVPECL91
Open
GND
VEE
GND
Figure 9. Standard LVTTTL Interface
D
D
GND
VEE
Figure 10. Standard LVCMOS Interface
(D will default to VCC/2 when left open. A
reference voltage of VCC/2 should be applied to
D input, if D is interfaced to CMOS signals.)
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5
NB100LVEP91
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device
Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
-
ECLinPS Circuit Performance at Non-Standard VIH Levels
AN1405
-
ECL Clock Distribution Techniques
AN1503
-
ECLinPS I/O SPICE Modeling Kit
AN1504
-
Metastability and the ECLinPS Family
AN1560
-
Low Voltage ECLinPS SPICE Modeling Kit
AN1650
-
Using Wire-OR Ties in ECLinPS Designs
AN1672
-
The ECL Translator Guide
AND8002
-
Marking and Date Codes
AND8020
-
Termination of ECL Logic Devices
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NB100LVEP91
PACKAGE DIMENSIONS
SO-20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-05
ISSUE F
A
20
X 45 h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
SEATING
PLANE
A1
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L-01
ISSUE O
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
B
PIN 1
IDENTIFICATION
E
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
L
2X
0.15 C
0.15 C
2X
A2
0.10 C
A
0.08 C
A3
A1
SEATING
PLANE
REF
C
D2
e
L
7
12
6
13
E2
24X
b
1
0.10 C A B
18
24
19
e
0.05 C
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MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.23
0.28
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.35
0.45
NB100LVEP91
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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NB100LVEP91/D