PCS5I9774 September 2006 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features The PCS5I9774 features two reference clock inputs and • Output frequency range: 8.3MHz to 125MHz provides 14 outputs partitioned in 3 banks of 5, 5, and 4 • Input frequency range: 4.2MHz to 62.5MHz outputs. Bank A and Bank B divide the VCO output by 4 or • 2.5V or 3.3V operation 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, • Split 2.5V/3.3V outputs see Functional Table. These dividers allow output to input • 14 Clock outputs: Drive up to 28 clock lines ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each • 1 Feedback clock output LVCMOS compatible output can drive 50Ω series or • 2 LVCMOS reference clock inputs parallel • 150pS max output-output skew terminated transmission lines, each output can drive one or • PLL bypass mode two traces giving the device an effective fanout of 1:28. • ‘SpreadTrak’ The PLL is ensured stable given that the VCO is configured • Output enable/disable to run between 200MHz to 500MHz. This allows a wide • Pin compatible with MPC9774 and CY29774 range of output frequencies from 8.3MHz to 125MHz. For • Industrial temperature range: -40°C to +85°C normal operation, the external feedback input, FB_IN, is • 52Pin 1.0mm TQFP package connected to the feedback output, FB_OUT. The internal • RoHS Compliance VCO is running at multiples of the input reference clock set terminated transmission lines. For series by the feedback divider, see Frequency Table. Functional Description When PLL_EN is LOW, PLL is bypassed and the reference high-performance clock directly feeds the output dividers. This mode is fully 125MHz PLL-based zero delay buffer designed for static and the minimum input clock frequency specification high-speed clock distribution applications. does not apply. The PCS5I9774 is a low-voltage Block Diagram VCO_SEL PLL_EN TCLK_SEL TCLK0 TCLK1 FB_IN ÷2 PLL 200500MHZ ÷2/÷4 ÷4 CLK STOP QA0 QA1 QA2 QA3 QA4 SELA ÷2/÷4 CLK STOP ÷4/÷6 CLK STOP SELB QB0 QB1 QB2 QB3 QB4 QC0 QC1 SELC QC2 QC3 CLK_STP# ÷4/÷6/÷8/÷12 FB_OUT FB_SEL(1.0) MR#/OE PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS5I9774 September 2006 rev 0.4 VSS 1 QB0 NC VDDQB VSS QC3 VDDQC QC2 VSS QC1 VDDQC QC0 VSS VCO_SEL Pin Configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VSS MR#/OE 2 38 QB1 CLK_STP# 3 37 VDDQB SELB 4 36 QB2 SELC 5 35 VSS PLL_EN 6 34 QB3 PCS5I9774 SELA 7 33 VDDQB TCLK_SEL 8 32 QB4 TCLK0 9 31 FB_IN TCLK1 10 30 VSS NC 11 29 FB_OUT VDD 12 28 VDDFB AVDD 13 27 NC VDDQA QA0 VSS QA1 VDDQA QA2 FB_SEL1 VSS QA3 VDDQA QA4 AVSS FB_SEL0 14 15 16 17 18 19 20 21 22 23 24 25 26 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 12 PCS5I9774 September 2006 rev 0.4 Pin Description1 Pin Name I/O Type Description 9 TCLK0 I, PD LVCMOS LVCMOS/LVTTL reference clock input 10 TCLK1 I, PU LVCMOS LVCMOS/LVTTL reference clock input 16, 18, 21, 23, 25 QA(4:0) O LVCMOS Clock output bank A 32, 34, 36, 38, 40 QB(4:0) O LVCMOS Clock output bank B 44, 46, 48, 50 QC(3:0) O LVCMOS Clock output bank C 29 FB_OUT O LVCMOS Feedback clock output. Connect to FB_IN for normal operation. 31 FB_IN I, PU LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 2 MR#/OE I, PU LVCMOS Output enable/disable input. See Table 2. 3 CLK_STP# I, PU LVCMOS Clock stop enable/disable input. See Table 2. 6 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 8 TCLK_SEL I, PD LVCMOS Reference select input. See Table 2. 52 VCO_SEL I, PD LVCMOS VCO divider select input. See Table 2. 7, 4, 5 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 3. 20, 14 FB_SEL(1,0) I, PD LVCMOS Feedback dividers select input. See Table 4. 17, 22, 26 VDDQA Supply VDD 2.5V or 3.3V Power supply for bank A output clocks2,3 33, 37, 41 VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clocks2,3 45, 49 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks2,3 28 VDDFB Supply VDD 2.5V or 3.3V Power supply for feedback output clock2,3 13 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL2,3 12 VDD Supply VDD 2.5V or 3.3V Power supply for core and inputs2,3 15 AVSS Supply Ground Analog Ground 1, 19, 24, 30, 35, 39, 43, 47, 51 VSS Supply Ground Common Ground 11, 27, 42 NC No Connection Note: 1.PU = Internal pull up, PD = Internal pull down. 2.A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 12 PCS5I9774 September 2006 rev 0.4 ‘SpreadTrak’ When a zero delay buffer is not designed to pass the Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Spread Spectrum feature through, the result is a PCS59774A is designed so as not to filter off the Spread significant amount of tracking skew which may cause Spectrum feature of the Reference Input, assuming it problems in the systems requiring synchronization. exists. Table 1. Frequency Table Feedback Output Divider VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) ÷8 Input Clock * 8 25MHz to 62.5MHz 25MHz to 50MHz ÷12 Input Clock * 12 16.6MHz to 41.6MHz 16.6MHz to 33.3MHz ÷16 Input Clock * 16 12.5MHz to 31.25MHz 12.5MHz to 25MHz ÷24 Input Clock * 24 8.3MHz to 20.8MHz 8.3MHz to 16.6MHz ÷32 Input Clock * 32 6.25MHz to 15.625 MHz 6.25MHz to 12.5MHz ÷48 Input Clock * 48 4.2MHz to 10.4MHz 4.2MHz to 8.3MHz Table 2. Function Table (configuration controls) Control Default 0 1 TCLK_SEL 0 TCLK0 TCLK1 VCO_SEL 0 VCO÷2 (high input frequency range) VCO÷4 (low input frequency range) PLL_EN 1 PLL enabled. The VCO output connects to the output dividers MR#/OE 1 CLK_STP# 1 Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. QA, QB, and QC outputs disabled in LOW state. FB_OUT is not affected by CLK_STP#. Outputs enabled Outputs enabled Table 3. Function Table (Bank A, B and C) VCO_SEL SELA QA(4:0) SELB QB(4:0) SELC QC(3:0) 0 0 ÷4 0 ÷4 0 ÷8 0 1 ÷8 1 ÷8 1 ÷12 1 0 ÷8 0 ÷8 0 ÷16 1 1 ÷16 1 ÷16 1 ÷24 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 12 PCS5I9774 September 2006 rev 0.4 Table 4. Function Table (FB_OUT) VCO_SEL FB_SEL1 FB_SEL0 FB_OUT 0 0 0 ÷8 0 0 1 ÷16 0 1 0 ÷12 0 1 1 ÷24 1 0 0 ÷16 1 0 1 ÷32 1 1 0 ÷24 1 1 1 ÷48 Absolute Maximum Conditions Parameter Description Condition VDD DC Supply Voltage VDD DC Operating Voltage Functional VIN Min Max Unit -0.3 5.5 V 2.375 3.465 V DC Input Voltage Relative to VSS -0.3 VDD+ 0.3 V VOUT DC Output Voltage Relative to VSS -0.3 VDD+ 0.3 V VTT Output termination Voltage LU Latch Up Immunity Functional 200 RPS Power Supply Ripple Ripple Frequency < 100kHz TS Temperature, Storage Non Functional -65 +150 °C TA Temperature, Operating Ambient Functional -40 +85 °C TJ VDD ÷2 V mA 150 mVp-p Temperature, Junction Functional 150 °C ØJC Dissipation, Junction to Case Functional 23 °C/W ØJA Dissipation, Junction to Ambient Functional 55 °C/W ESDH FIT ESD Protection (Human Body Model) Failure in Time 2000 Manufacturing test 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. Volts 10 ppm 5 of 12 PCS5I9774 September 2006 rev 0.4 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH VOL VOH IIL Input Voltage, High Output Voltage, Low1 Output Voltage, High1 Input Current, Low2 LVCMOS IOL= 15mA IOH= –15mA VIL= VSS IIH Input Current, High VIL= VDD 2 IDDA PLL Supply Current AVDD only IDDQ Quiescent Supply Current All VDD pins except AVDD IDD Dynamic Supply Current Outputs loaded @ 100MHz CIN Input Pin Capacitance ZOUT Min Typ 1.7 Max Unit 0.7 V VDD+0.3 0.6 -100 V V V µA 100 µA 10 mA 8 mA 1.8 5 135 mA 4 Output Impedance 14 Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output terminated transmission lines 2. Inputs have pull-up or pull-down resistors that affect the input current. 18 pF 22 Ω drives up to two 50 Ωseries- DC Electrical Specifications (VDD= 3.3V ± 5%, TA= -40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH Input Voltage, High LVCMOS VOL Output Voltage, Low1 VOH IIL IIH 2.0 Max 0.8 V V 0.55 0.30 Output Voltage, High1 Input Current, Low2 Input Current, High2 VIL= VDD PLL Supply Current AVDD only Quiescent Supply Current All VDD pins except AVDD IDD Dynamic Supply Current Outputs loaded @ 100MHz 2.4 5 V µA 100 µA 10 mA 8 mA mA 4 12 15 V -100 225 Input Pin Capacitance Output Impedance Unit VDD + 0.3 IOL= 24 mA IDDA CIN Typ IOL= 12 mA IOH=-24 mA VIL= VSS IDDQ ZOUT Min pF 18 Ω Note: 1. Driving one 50Ω parallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series-terminated transmission lines 2. Inputs have pull-up or pull-down resistors that affect the input current. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 12 PCS5I9774 September 2006 rev 0.4 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO fin Description Max Unit 200 400 MHz ÷8 Feedback 25 50 ÷12 Feedback 16.6 33.3 ÷16 Feedback 12.5 25 ÷24 Feedback 8.3 16.6 ÷32 Feedback 6.3 12.5 ÷48 Feedback 4.2 8.3 Bypass mode (PLL_EN = 0) 0 200 25 75 % 1.0 nS VCO Frequency Input Frequency frefDC Input Duty Cycle tr, tf TCLK Input Rise/FallTime fMAX Condition Maximum Output Frequency Min Typ 0.7V to 1.7V MHz ÷4 Output 50 100 ÷8 Output 25 50 ÷12 Output 16.6 33.3 ÷16 Output 12.5 25 ÷24 Output 8.3 16.6 45 55 % MHz DC Output Duty Cycle tr, tf Output Rise/Fall times 0.7V to 1.8V 0.1 0.75 nS t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, does not include jitter -100 100 pS tsk(O) Output-to-Output Skew Skew within Bank 150 pS Bank-to-Bank Skew Banks at same frequency Banks at different frequency tsk(B) tPLZ, HZ tPZL, ZH BW 150 pS 200 Output Disable Time 10 nS Output Enable Time 10 nS PLL Closed Loop Bandwidth (–3 dB) 0.5 -1.0 MHz Same frequency 100 Multiple frequencies 250 tJIT(CC) Cycle-to-Cycle Jitter pS tJIT(PER) Period Jitter 100 pS tJIT(φ) I/O Phase Jitter 125 pS tLOCK Maximum PLL Lock Time 1 mS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 12 PCS5I9774 September 2006 rev 0.4 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO Description Condition Max Unit 200 500 MHz ÷8 Feedback 25 62.5 ÷12 Feedback 16.6 41.6 ÷16 Feedback 12.5 31.25 ÷24 Feedback 8.3 20.8 ÷32 Feedback 6.25 15.625 ÷48 Feedback 4.2 10.4 Bypass mode (PLL_EN = 0) 0 200 25 75 % 1.0 nS VCO Frequency fin Input Frequency Min Typ MHz frefDC Input Duty Cycle tr, tf TCLK Input Rise/FallTime 0.8V to 2.0V fMAX Maximum Output Frequency ÷4 Output 50 125 ÷8 Output 25 62.5 ÷12 Output 16.6 41.6 ÷16 Output 12.5 31.25 ÷24 Output 8.3 20.8 45 55 % 0.1 1.0 nS -100 100 pS pS DC Output Duty Cycle tr, tf Output Rise/Fall times 0.8V to 2.4V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within Bank 150 tsk(B) Bank-to-Bank Skew Banks at same voltage, same frequency 150 Banks at same voltage, different frequency 225 Banks at different voltage 250 MHz pS tPLZ, HZ Output Disable Time 10 nS tPZL, ZH Output Enable Time 10 nS BW tJIT(CC) tJIT(PER) PLL Closed Loop Bandwidth (–3dB) Cycle-to-Cycle Jitter 0.5 - 1.0 Same frequency 150 Multiple frequencies 300 Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time MHz I/O at same VDD pS 100 pS 150 pS 1 mS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 12 PCS5I9774 September 2006 rev 0.4 Zo = 50 ohm Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset VDD VDD/2 GND tP T0 DC = tP / T0 x 100% Figure 3. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 4. Output-to-Output Skew, tsk(O) 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 12 PCS5I9774 September 2006 rev 0.4 Package Information 52-lead TQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.4646 0.4803 11.8 12.2 D1 0.3898 0.3976 9.9 10.1 E 0.4646 0.4803 11.8 12.2 E1 0.3898 0.3976 9.9 10.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0102 0.0150 0.26 0.38 b1 0.0106 0.0130 0.27 0.33 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.0256 BASE 0.65 BASE 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 12 PCS5I9774 September 2006 rev 0.4 Ordering Information Part Number Marking Package Type Operating Range PCS5P9774G-52-ET PCS5P9774G 52-pin TQFP, Tray, Green Commercial PCS5P9774G-52-ER PCS5P9774G 52-pin TQFP – Tape and Reel, Green Commercial PCS5I9774G-52-ET PCS5I9774G 52-pin TQFP, Tray, Green Industrial PCS5I9774G-52-ER PCS5I9774G 52-pin TQFP – Tape and Reel, Green Industrial Device Ordering Information P C S 5 I 9 7 7 4 G - 5 2 - E T R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 12 PCS5I9774 September 2006 rev 0.4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9774 Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 12