IGNS DES W E T OR N DUC ED F TE PRO D N MME BSTITU ECOSheet SU R Data January 2002 T 40N NO IBLE S IRF5 S PO IRF540, RF1S540SM 28A, 100V, 0.077 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17421. Features • 28A, 100V • rDS(ON) = 0.077Ω • Single Pulse Avalanche Energy Rated • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Ordering Information D PART NUMBER PACKAGE BRAND IRF540 TO-220AB IRF540 RF1S540SM TO-263AB RF1S540SM G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S540SM9A. S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation GATE DRAIN (FLANGE) SOURCE IRF540, RF1S540SM Rev. B IRF540, RF1S540SM TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T pkg IRF540, RF1S540SM 100 100 28 20 110 ±20 120 0.8 230 -55 to 175 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current SYMBOL BVDSS VGS(TH) IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge rDS(ON) gfs td(ON) tr td(OFF) MIN TYP MAX UNITS 100 - - V VGS = VDS, ID = 250µA 2 - 4 V VDS = 95V, VGS = 0V - - 25 µA VDS = 0.8 x Rated BV DSS, VGS = 0V, TJ = 150oC - - 250 µA 28 - - A - - ±100 nA VDS > ID(ON) x rDS(ON) MAX, VGS = 10V (Figure 7) VGS = ±20V - 0.060 0.077 Ω 8.7 13 - S VDD = 50V, ID ≈ 28A, RG ≈ 9.1Ω, RL = 1.7Ω MOSFET Switching Times are Essentially Independent of Operating Temperature - 15 23 ns - 70 110 ns - 40 60 ns - 50 83 ns VGS = 10V, ID = 28A, VDS = 0.8 x Rated BV DSS , Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 38 59 nC - 8 - nC - 21 - nC VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 1450 - pF - 550 - pF - 100 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 1.25 oC/W ID = 17A, VGS = 10V (Figures 8, 9) VDS ≥ 50V, ID = 17A (Figure 12) tf Qg(TOT) Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 10) LD Measured From the Contact Screw on Tab To Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D Measured From the Drain Lead, 6mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 80 oC/W RθJA RF1S540SM Mounted on FR-4 Board with Minimum Mounting Pad - - 62 oC/W ©2002 Fairchild Semiconductor Corporation IRF540, RF1S540SM Rev. B IRF540, RF1S540SM Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISD Pulse Source to Drain Current (Note 3) ISDM D MIN TYP MAX - - 28 UNITS A - - 110 A G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge VSD TJ trr TJ QRR TJ = 25oC, ISD = 27A, VGS = 0V (Figure 13) = 25oC, ISD = 28A, dISD/dt = 100A/µs = 25oC, ISD = 28A, dISD/dt = 100A/µs - - 2.5 V 70 150 300 ns 0.2 1.0 1.9 µC NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 440µH, RG = 25Ω, peak IAS = 28A. Unless Otherwise Specified 1.2 30 1.0 24 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 18 12 6 0.2 0 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 25 0 150 25 175 50 75 100 150 125 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W) 10 1 0.5 PDM 0.2 0.1 0.1 t1 t2 0.05 0.02 0.01 0.01 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC SINGLE PULSE 10-4 10-3 10-2 10-1 1 10 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2002 Fairchild Semiconductor Corporation IRF540, RF1S540SM Rev. B IRF540, RF1S540SM Typical Performance Curves Unless Otherwise Specified (Continued) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX SINGLE PULSE TJ = MAX RATED TC = 25o C 100 50 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 300 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms VGS = 7V VGS = 10V VGS = 8V 40 30 VGS = 6V 20 VGS = 5V 10 10ms VGS = 4V 1 0 1 100 10 300 0 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ID, DRAIN CURRENT (A) ID(ON), ON-STATE DRAIN CURRENT (A) 100 VGS = 8V 40 VGS = 7V VGS = 10V 30 VGS = 6V 20 VGS = 5V 10 VGS = 4V 0 0 2 1 3 4 5 10 175oC 0.1 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.8 ON RESISTANCE (Ω) rDS(ON), DRAIN TO SOURCE 25oC 1 FIGURE 6. SATURATION CHARACTERISTICS 0.6 0.4 VGS = 10V 0.2 VDS ≥ 50V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS, DRAIN TO SOURCE VOLTAGE (V) 1.0 60 FIGURE 5. OUTPUT CHARACTERISTICS 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 12 24 36 48 VDS, DRAIN TO SOURCE VOLTAGE (V) 2.4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 28A 1.8 1.2 0.6 VGS = 20V 0 0 25 50 75 100 125 ID, DRAIN CURRENT (A) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2002 Fairchild Semiconductor Corporation 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF540, RF1S540SM Rev. B IRF540, RF1S540SM Typical Performance Curves 3000 ID = 250µA 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 2400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 1.05 0.95 0.85 1800 CISS 1200 COSS 600 CRSS 0.75 -60 -40 -20 0 20 40 0 80 100 120 140 160 180 60 1 10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 1000 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 16 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 20 25oC 12 175oC 8 4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 100 175oC 25oC 10 0 0 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 30 40 1 50 0.6 1.2 1.8 2.4 VSD, SOURCE TO DRAIN VOLTAGE (V) 0 ID , DRAIN CURRENT (A) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT VGS, GATE TO SOURCE VOLTAGE (V) 20 3.0 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 28A VDS = 50V 16 VDS = 20V 12 VDS = 80V 8 4 0 0 12 24 36 48 60 Qg , GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE ©2002 Fairchild Semiconductor Corporation IRF540, RF1S540SM Rev. B IRF540, RF1S540SM Test Circuits and Waveforms VDS BVDSS tP L VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 16. UNCLAMPED ENERGY WAVEFORMS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT tON tOFF td(ON) td(OFF) tr VDS RL tf 90% 90% + RG - VDD 10% 0 10% 90% DUT VGS VGS 0 12V BATTERY 0.2µF VDS (ISOLATED SUPPLY) VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd D G Ig(REF) VDS DUT 0 S IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation VGS Qgs 0.3µF 0 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT CURRENT REGULATOR 50% 10% IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF540, RF1S540SM Rev. B