BACK RJ21P3AA0PT 1/1.8-type Interline Color CCD Area Sensor with 3 370 k Pixels RJ21P3AA0PT • Package : 20-pin half-pitch DIP [Plastic] (P-DIP020-0500) Row space : 12.20 mm DESCRIPTION The RJ21P3AA0PT is a 1/1.8-type (8.93 mm) solidstate image sensor that consists of PN photodiodes and CCDs (charge-coupled devices). With approximately 3 370 000 pixels (2 152 horizontal x 1 567 vertical), the sensor provides a stable highresolution color image. PIN CONNECTIONS 20-PIN HALF-PITCH WDIP TOP VIEW FEATURES OD 1 • Optical size : 8.93 mm (aspect ratio 4 : 3) 8.93 mm 1 544 3 210 k effective pixels 2 080 • • • • • • • • • • • • • • • Interline scan format Square pixel Number of image pixels : 2 096 (H) x 1 560 (V) Number of effective pixels : 2 080 (H) x 1 544 (V) Number of optical black pixels – Horizontal : 2 front and 54 rear – Vertical : 5 front and 2 rear Number of dummy bits – Horizontal : 24 – Vertical : 2 Pixel pitch : 3.45 µm (H) x 3.45 µm (V) R, G, and B primary color mosaic filters Supports monitoring mode Low fixed-pattern noise and lag No burn-in and no image distortion Blooming suppression structure Built-in output amplifier Built-in overflow drain voltage circuit and reset gate voltage circuit Variable electronic shutter 20 OS GND 2 19 GND OFD 3 18 NC5 PW 4 17 NC4 ØRS 5 16 ØV1A NC1 6 15 ØV1B NC2 7 14 ØV2 ØH1 8 13 ØV3A NC3 9 12 ØV3B ØH2 10 11 ØV4 (P-DIP020-0500) PRECAUTIONS • The exit pupil position of lens should be 30 to 55 mm from the top surface of the CCD. • Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 RJ21P3AA0PT PIN DESCRIPTION SYMBOL OD PIN NAME Output transistor drain OS ØRS Output signals ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 ØH1, ØH2 Vertical shift register clock Horizontal shift register clock Reset transistor clock OFD Overflow drain PW GND P-well Ground NC1, NC2, NC3, NC4, NC5 No connection ABSOLUTE MAXIMUM RATINGS PARAMETER Output transistor drain voltage (TA = +25˚C) SYMBOL VOD RATING 0 to +18 UNIT V NOTE Overflow drain voltage VOFD Reset gate clock voltage VØRS Internal output Internal output V V 1 2 Vertical shift register clock voltage Horizontal shift register clock voltage VØV VØH VPW to +18 –0.3 to +12 V V Voltage difference between P-well and vertical clock VPW-VØV –27 to 0 V Voltage difference between vertical clocks VØV-VØV 0 to +18 V Storage temperature TSTG –40 to +85 ˚C Ambient operating temperature TOPR –20 to +70 ˚C 3 NOTES : 1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 24 Vp-p. 2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p. 3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 26 V. 2 RJ21P3AA0PT RECOMMENDED OPERATING CONDITIONS PARAMETER Ambient operating temperature SYMBOL TOPR MIN. TYP. 25.0 MAX. UNIT ˚C Output transistor drain voltage Overflow drain clock p-p level VOD VØOFD 14.55 15.0 15.45 V 20.7 21.5 22.8 V 1 Ground P-well voltage GND VPW VØVL V V 2 –6.65 V LOW level Vertical shift register clock INTERMEDIATE level HIGH level VØV1AL, VØV1BL, VØV2L VØV3AL, VØV3BL, VØV4L 0.0 –8.0 –7.35 VØV1AI, VØV1BI, VØV2I VØV3AI, VØV3BI, VØV4I VØV1AH, VØV1BH –7.0 0.0 V 14.55 15.0 15.45 V –0.05 0.0 +0.05 V Horizontal shift LOW level VØV3AH, VØV3BH VØH1L, VØH2L register clock HIGH level VØH1H, VØH2H 4.5 4.8 5.5 V VØRS fØV1A, fØV1B, fØV2 4.5 4.8 5.5 V Reset gate clock p-p level Vertical shift register clock frequency Horizontal shift register clock frequency fØV3A, fØV3B, fØV4 fØH1, fØH2 7.50 kHz 18.00 MHz fØRS 18.00 MHz Reset gate clock frequency NOTE 1 NOTES : 1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly. 2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected to VL of V driver IC. * To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on VPW first and then turn on other powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied. 3 RJ21P3AA0PT CHARACTERISTICS (Drive method : 1/30 s frame accumulation) (TA = +25˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS". Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.) PARAMETER Standard output voltage SYMBOL VO Photo response non-uniformity PRNU Saturation output voltage VSAT Dark output voltage Dark signal non-uniformity VDARK DSNU Sensitivity (green channel) Smear ratio R (G) SMR Image lag Blooming suppression ratio Output transistor drain current MIN. TYP. 150 450 530 320 400 130 MAX. UNIT mV NOTE 2 10 % mV 3 4 mV 5 0.5 0.5 3.0 2.0 mV mV 1, 6 1, 7 160 –90 –82 mV dB 8 9 1.0 % AI ABL IOD 1 000 10 11 4.0 8.0 mA NOTES : 6. The average output voltage under non-exposure conditions. 7. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively. 8. The average output voltage of G signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm. 9. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square. 10. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. • Within the recommended operating conditions of VOD, VOFD of the internal output satisfies with ABL larger than 1 000 times exposure of the standard exposure conditions, and VSAT larger than 320 mV. 1. TA = +60˚C 2. The average output voltage of G signal under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV. 3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax – Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively. 4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is high. (for still image capturing) 5. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is low. 4 RJ21P3AA0PT PIXEL STRUCTURE OPTICAL BLACK (2 PIXELS) OPTICAL BLACK (2 PIXELS) OPTICAL BLACK (54 PIXELS) 2 096 (H) x 1 560 (V) 1 pin OPTICAL BLACK (5 PIXELS) COLOR FILTER ARRAY (1, 1 560) Pin arrangement of the vertical readout clock (2 096, 1 560) ØV3B ØV1A ØV3B ØV1B ØV3B ØV1B ØV3B ØV1B ØV3A ØV1B ØV3B ØV1B ØV3B ØV1B ØV3B ØV1A ØV3B ØV1B G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G ØV3B ØV1B ØV3B ØV1B ØV3B ØV1B ØV3A ØV1B ØV3B ØV1B ØV3B ØV1B ØV3B ØV1A ØV3B ØV1B ØV3B ØV1B G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G (1, 1) (2 096, 1) 5 RJ21P3AA0PT TIMING CHART TIMING CHART EXAMPLE Pulse diagram in more detail is shown in the figure q to r after next page. Field accumulation mode q VD 227.5 q' 455 1 ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 ØOFD (at OFD shutter operation) OFDC At first frame Frame accumulation accumulation mode mode w 227.5 At first field Field accumulation mode accumulation mode e 848 1 455 1 ; ; ; ; ; ; r q q' q q' 848 1 227.5 455 1 227.5 455 1 ; ; ; ; ; ; OS (Number of vertical line) Field accumulation Not for use Not for use (NOTE 1) (NOTE 1) mode (5, 12, 19...) Frame accumulation mode (1, 3, 5, 7, 9...) (2, 4, 6, 8, 10...) Not for use (NOTE 2) Field accumulation mode (5, 12, 19..) (5, 12, 19..) (5, 12, 19..) NOTES : 1. Do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. Do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * Start the exposure period after 10 ms later that OFDC is high, and finish before change swept transfer. * Apply at least an OFD shutter pulse to OFD in each field accumulation mode. 6 RJ21P3AA0PT q VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡ 2 640 clk/H 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD 1475 OS 1489 1503 1517 1531 1545 1559 1482 1496 1510 1524 1538 1552 RG GB RG GB RG GB RG GB RG GB RG GB RG 5 12 19 26 33 40 47 54 61 68 RG GB RG GB RG GB RG GB RG GB OB3 q' VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡ 444 445 446 447 448 449 450 451 452 453 454 455 1 2 3 4 5 6 7 8 9 2 640 clk/H 10 11 12 13 14 15 16 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD OS 1475 1489 1503 1517 1531 1545 1559 1468 1482 1496 1510 1524 1538 1552 GB RG GB RG GB RG GB RG GB RG GB RG GB RG 7 OB3 5 12 19 26 33 40 47 54 61 68 RG GB RG GB RG GB RG GB RG GB RJ21P3AA0PT w VERTICAL TRANSFER TIMING ¿AT FIRST FRAME ACCUMULATION MODE¡ 451 452 453 454 455 1 2 3 4 5 6 7 8 2 640 clk/H … 61 62 63 64 65 66 67 68 69 70 71 72 73 9 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Charge swept transfer (2 112 stages) OFDC ØOFD OB2 OB4 OS 1 3 5 7 RG RG RG RG Not for use * Do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. e VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ 844 845 846 847 848 1 2 3 4 5 6 7 8 9 2 640 clk/H … 61 62 63 64 65 66 67 68 69 70 71 72 73 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 Charge swept transfer (2 112 stages) OFDC ØOFD 1549 OS 1553 1557 1551 1555 1559 RG RG RG RG RG RG OB1 OB3 OB5 Not for use 8 2 4 6 GB GB GB RJ21P3AA0PT r VERTICAL TRANSFER TIMING ¿AT FIRST FIELD ACCUMULATION MODE¡ 837 838 839 840 841 842 843 844 845 846 847 848 1 2 3 4 5 6 7 8 9 2 640 clk/H 10 11 12 13 14 15 16 HD VD ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFDC ØOFD 1534 OS 1538 1542 1546 1550 1554 1558 OB2 1536 1540 1544 1548 1552 1556 1560 GB GB GB GB GB GB GB GB GB GB GB GB GB GB Not for use * Do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. 9 RJ21P3AA0PT READOUT TIMING ¿FIELD ACCUMULATION MODE¡ 2640 (0) 2640 (0) 260 260 HD 698 824 908 ØV1A 166 ØV1B 222 992 ØV2 1034 1160 866 ØV3A 194 ØV3B 950 250 ØV4 38.9 µs (698 bits) 57.6 µs (1 034 bits) 7.02 µs (126 bits) 7.02 µs (126 bits) READOUT TIMING ¿FRAME ACCUMULATION MODE¡ w 2640 (0) 2640 (0) 260 260 HD ØV1A ØV1B 698 824 908 16 166 992 36 222 ØV2 ØV3A ØV3B 16 194 866 36 250 950 ØV4 38.9 µs (698 bits) e 2640 (0) 7.02 µs (126 bits) 2640 (0) 260 260 HD ØV1A ØV1B 16 908 36 992 166 222 ØV2 1034 1160 866 ØV3A ØV3B 36 950 ØV4 7.02 µs (126 bits) 57.6 µs (1 034 bits) 10 194 250 RJ21P3AA0PT HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-1 2640 (0) 54 82 110 138 166 1 clk = 55.7 ns (= 1/18.0 MHz) 222 250 260 278 194 HD ØH1 ØH2 ØRS OS ππ2096 OB (54) 28 clk (= 1.56 µs) 4-stage transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 3-stage transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 152 208 OFD * Keep over 1.56 µs when vertical transfer clock pulse is overlapping. 11 RJ21P3AA0PT HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-2 278 306 334 362 390 418 446 1 clk = 55.7 ns (= 1/18.0 MHz) 518 474 HD ØH1 ØH2 ØRS OS PRE SCAN (24) OB (2) OUTPUT (2 096) 1ππππππππ 4-stage transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 3-stage transfer ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFD * Keep over 1.56 µs when vertical transfer clock pulse is overlapping. 12 RJ21P3AA0PT HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-1 2640 (0) 54 82 110 138 166 1 clk = 55.7 ns (= 1/18.0 MHz) 222 250 260 278 194 HD ØH1 ØH2 ØRS OS ππ2096 OB (54) 56 clk (= 3.11 µs) ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 208 152 OFD * Keep over 3.11 µs when vertical clock pulse is overlapping. HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-2 278 306 334 362 390 418 446 1 clk = 55.7 ns (= 1/18.0 MHz) 474 508 HD ØH1 ØH2 ØRS OS PRE SCAN (24) OB (2) OUTPUT (2 096) 1ππππππππ ØV1A ØV1B ØV2 ØV3A ØV3B ØV4 OFD * Keep over 3.11 µs when vertical transfer clock pulse is overlapping. 13 RJ21P3AA0PT CHARGE SWEPT TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡ w, e 2H 0 3H 4H 5H ••••••• 260 65H 66H 2640 HD ØV1A ØV1B 56 96 76 136 116 176 156 216 2616 16 196 2636 36 ØV2 ØV3A ØV3B 56 96 76 136 116 176 156 216 2616 16 2636 36 196 ØV4 1 2 3 ••••••• 2110 2111 2112 * Keep over 1.56 µs when vertical transfer clock pulse of charge swept transfer is overlapping. 14 VL V2 V4 NC V3B V3A V1B V1A VMa VH 15 13 14 15 16 17 18 19 20 21 22 23 24 9 8 7 5 (*1) 6 4 270 pF 3 (*1) 2 1 11 12 13 14 15 16 17 18 19 20 RJ21P3AA0PT 10 NC1 ØV1B ØV3A ØV3B ØV4 Be sure to use the parameter indicated in this circuit example. (*1) ØRS, OFD : Do not connect to DC voltage directly. ØV2 VDD +VDD V3X VH1AX V1X V2X OFDX VH3BX VMb 1 POFD 2 0. 1 µF ØRS LR36685 + 3 ØH2 4 NC3 5 100 k$ 0.01 µF 1 M$ ØH1 6 1.0 µF NC2 7 100 $ PW 8 33 k$ OFD 9 47 µF OD 12 11 10 47 k$ 1 M$ CCD OUT + V4X VH3AX 5.6 k$ GND VH1BX VH ØH2 VL (VPW) ØRS ØH1 OFDC VOD RJ21P3AA0PT SYSTEM CONFIGURATION EXAMPLE OS GND NC5 NC4 ØV1A VOFDH VH3BX OFDX V2X V1X VH1AX V3X GND + VH3AX V4X VH1BX + RJ21P3AA0PT PACKAGE OUTLINES 20 DIP (P-DIP020-0500) (Unit : mm) Center of effective imaging area and center of package 6.9±0.075 0.4±0.4 11 11.2±0.1 (◊2) 12±0.1 0.4±0.4 6±0.075 20 ¬ Rotation error of die : ¬ = 1.0˚MAX. (◊ 1 : Effective imaging area) (◊ 2 : Lid's size) CCD 1 10 12.2±0.1 13±0.1 (◊2) Refractive index : nd = 1.5 0.02 (◊1) A ±0.1 2.4±0.1 13.8 A 20-0.3TYP. 20-0.64TYP. A' 0.5±0.05 (◊2) 1.41±0.025 2.9±0.1 3.5±0.1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; P-1.27TYP. Glass Lid ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; CCD ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Package ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; A' 0.02 (◊1) 0.04 0.25±0.1 +0.3 0.2 M 12.2 –0 16 RJ21P3AA0PT (In the case of plastic packages) – The leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. PRECAUTIONS FOR CCD AREA SENSORS 1. Package Breakage In order to prevent the package from being broken, observe the following instructions : 1) The CCD is a precise optical component and the package material is ceramic or plastic. Therefore, ø Take care not to drop the device when mounting, handling, or transporting. ø Avoid giving a shock to the package. Especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn’t fixed. 2) When applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. In addition, when applying force, do it at a point below the stand-off part. Glass cap Package Lead Fixed Stand-off 3) When mounting the package on the housing, be sure that the package is not bent. – If a bent package is forced into place between a hard plate or the like, the package may be broken. 4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore, ø Do not hit the glass cap. ø Do not give a shock large enough to cause distortion. ø Do not scrub or scratch the glass surface. – Even a soft cloth or applicator, if dry, could cause flaws to scratch the glass. (In the case of ceramic packages) – The leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. Low melting point glass Lead 2. Electrostatic Damage As compared with general MOS-LSI, CCD has lower ESD. Therefore, take the following antistatic measures when handling the CCD : 1) Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 M$ between the human body and the ground to be on the safe side. 2) When directly handling the device with the fingers, hold the part without leads and do not touch any lead. Fixed Stand-off 17 RJ21P3AA0PT 3) To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dustcleaning tape. 4) When storing or transporting the device, put it in a container of conductive material. 4. Other 1) Soldering should be manually performed within 5 seconds at 350°C maximum at the tip of soldering iron. 2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD. 3)* Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters. 3. Dust and Contamination Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. In order to minimize dust or contamination on the glass surface, take the following precautions : 1) Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be, if possible, class 1 000 at least.) 2) Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended : ø Dust from static electricity should be blown off with an ionized air blower. For antielectrostatic measures, however, ground all the leads on the device before blowing off the dust. ø The contamination on the glass surface should be wiped off with a clean applicator soaked in isopropyl alcohol. Wipe slowly and gently in one direction only. – Frequently replace the applicator and do not use the same applicator to clean more than one device. ◊ Note : In most cases, dust and contamination are unavoidable, even before the device is first used. It is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. * Only for color devices 18