VISHAY SI7636DP

SPICE Device Model Si7636DP
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72791
S-60145Rev. B, 13-Feb-06
www.vishay.com
1
SPICE Device Model Si7636DP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
1.9
ID(on)
VDS ≥ 5 V, VGS = 10 V
1882
VGS = 10 V, ID = 25 A
0.0033
0.0033
VGS = 4.5 V, ID = 19 A
0.0040
0.0040
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
rDS(on)
V
A
Ω
Forward Transconductancea
gfs
VDS = 15 V, ID = 25 A
95
110
S
Forward Voltagea
VSD
IS = 2.9 A, VGS = 0 V
0.83
0.72
V
37
32
16.5
16.5
Dynamicb
Total Gate Charge
Gate-Source Charge
Qg
Qgs
VDS = 15 V, VGS = 4.5 V, ID = 20 A
Gate-Drain Charge
Qgd
8.5
8.5
Turn-On Delay Time
td(on)
22
24
13
16
70
90
55
32
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
tf
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
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Document Number: 72791
S-60145Rev. B, 13-Feb-06
SPICE Device Model Si7636DP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72791
S-60145Rev. B, 13-Feb-06
www.vishay.com
3