SM5876AM 3rd-order Σ∆, 2-channel D/A Converter OVERVIEW PINOUT MLEN CKSL CKO DVSS BCKI DI DVDD LRCI TSTN LO AVDDL LON The SM5876AM operates from a 2.7 to 5.5 V supply, and is available in 24-pin SSOPs. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 12 13 MCK MDT RSTN MUTEO XVSS XTO XTI XVDD RO AVDDR RON AVSS PACKAGE DIMENSIONS Unit: mm 24-pin SSOP 5.40 0.20 7.80 0.30 ■ System clock • 768fs (33.8688MHz) • 384fs (16.9344MHz) Crystal oscillator circuit built-in Infinity-zero detector circuit built-in MSB first, rear-packed serial data input format (≤ 64fs bit clock) 8-times oversampling digital filter • 32 dB stopband attenuation • ±0.05 dB passband ripple • −0.34 dB passband correction for 70 kHz LPF 3-line microcontroller interface for output mode and attenuator control settings 16 output modes Deemphasis filter operation • 36 dB stopband attenuation • −0.09 to +0.23 dB deviation • −0.34 dB passband correction for 70 kHz LPF Attenuator • 8-bit attenuator (linear 256 steps) • Independent left/right-channel set function • Soft mute function (approx. 1024/fs mute time) Σ∆ 2-channel D/A converter • 3rd-order noise shaper • 32fs oversampling 44.1 kHz sampling frequency 2.7 to 5.5 V operating supply voltage range (4.5 to 5.5 V operating supply voltage range with 768fs system clock) 24-pin SSOP Molybdenum-gate CMOS process 24 + 0.1 0.15 − 0.05 10.05 0.20 10.20 0.30 1.80 0.10 ■ 1 S M5 8 7 6 AM The SM5876AM is a 3rd-order Σ∆, 2-channel D/A converter LSI for CD-ROM digital audio reproduction equipment. It incorporates an 8-times oversampling digital filter, deemphasis filter, attenuator, and soft mute circuits built-in., using NPC’s Molybdenum-gate CMOS technology. 0.7 0.8 0.36 0.10 0.10 0.10 2.10MAX NIPPON PRECISION CIRCUITS INC. 0.50 0.20 0 10 NIPPON PRECISION CIRCUITS—1 SM5876AM BLOCK DIAGRAM LRCI BCKI DI Input interface MLEN MCK MDT L R Filter & attenuation operation block Microcontroller interface L RSTN MUTEO CKO R Timing control CKSL XVSS XTO DVSS DVDD L PWM data generation block XTI Noise shaper operation block R TSTN XVDD AVDDL AVDDR LO LON AVSS RON RO PIN DESCRIPTION Number Name I/O Description 1 MLEN Ip Microcontroller control latch clock input 2 CKSL Ip 768fs/384fs clock select. 768fs when HIGH, and 384fs when LOW. 3 CKO O Oscillator clock buffer output 4 DVSS 5 BCKI Ip Data bit clock input pin 6 DI Ip Serial data input pin 7 DVDD 8 LRCI Ip Sample data rate (fs) clock input pin. Left channel when HIGH, and right channel when LOW. 9 TSTN Ip Test input pin 10 LO O Left-channel analog output (+) 11 AVDDL 12 LON 13 AVSS 14 RON Digital ground pin Digital supply pin Left-channel analog supply pin O Left-channel analog output (−) Analog ground pin O Right-channel analog output (−) NIPPON PRECISION CIRCUITS—2 SM5876AM Number Name I/O Description 15 AVDDR 16 RO 17 XVDD 18 XTI I Crystal oscillator or external clock input pin 19 XTO O Crystal oscillator output pin 20 XVSS 21 MUTEO O Infinity-zero detector output (analog mute control) 22 RSTN Ip Reset pin. Reset when LOW. 23 MDT Ip Microcontroller control data input pin 24 MCK Ip Microcontroller control clock input pin Right-channel analog supply pin O Right-channel analog output (+) Crystal oscillator supply pin Crystal oscillator ground pin I: INPUT O: OUTPUT Ip: Input with pull-up Registor SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Symbol Rating Unit Supply voltage range DV DD, AV DD, XVDD −0.3 to 7.0 V Input voltage range1 V IN1 DV SS − 0.3 to DV DD + 0.3 V XTI input voltage range V IN XV SS − 0.3 to XVDD + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Symbol Rating Unit DV DD, AV DD, XVDD 4.5 to 5.5 V DV DD − XVDD, DV DD − AV DD, XV DD − AV DD, DV SS − XVSS, DV SS − AV SS, XV SS − AV SS ±0.1 V Topr −40 to 85 °C 1. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. Also applicable during supply switching. Recommended Operating Conditions 5 V operation: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Supply voltage range Supply voltage variation Operating temperature range NIPPON PRECISION CIRCUITS—3 SM5876AM 3 V operation: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR, CKSL = LOW (384fs) Parameter Supply voltage range Supply voltage variation Symbol Rating Unit DV DD, AV DD, XVDD 2.7 to 4.5 V DV DD − XVDD, DV DD − AV DD, XV DD − AV DD, DV SS − XVSS, DV SS − AV SS, XV SS − AV SS ±0.1 V Topr −20 to 70 °C Operating temperature range DC Electrical Characteristics 5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = −40 to 85 °C Rating Parameter DVDD digital supply current1 XVDD system clock supply current1 Symbol Condition Unit min typ max IDDD – 15 25 mA IDDX – 6 10 mA AVDD analog supply current1 IDDA Total current – 1 2 mA XTI HIGH-level input voltage V IH1 Clock input 0.7XVDD – – V XTI LOW-level input voltage V IL1 Clock input – – 0.3XVDD V XTI AC-coupled input voltage V INAC 0.3XVDD – – V p-p HIGH-level input voltage2 V IH2 2.4 – – V LOW-level input voltage2 V IL2 – – 0.5 V HIGH-level output voltage3 VOHA IOH = −1 mA AV DD − 0.4 – – V LOW-level output voltage3 VOLA IOL = 1 mA – – 0.4 V CKO HIGH-level output voltage VOHC IOH = −1 mA DV DD − 0.4 – – V CKO LOW-level output voltage VOLC IOL = 1 mA – – 0.4 V XTI HIGH-level input current IIH1 V IN = XVDD – 12 25 µA XTI LOW-level input current IIL1 V IN = 0 V – 12 25 µA LOW-level input current2 IIL2 V IN = 0 V – 12 25 µA Input leakage current2 ILH V IN = DV DD – – 1.0 µA 1. DV DD = AV DD = XVDD = 5 V, CKSL = HIGH (768fs), XTI clock input frequency fXTI = 33.8688 MHz, no output load, NPC-standard input data pattern. 2. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. 3. Pins LO, LON, RO, RON,MUTEO. 3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = −20 to 70 °C Rating Parameter DVDD digital supply current1 XVDD system clock supply current1 Symbol Condition Unit min typ max IDDD – 6 9 mA IDDX – 1.5 3 mA AVDD analog supply current1 IDDA Total current – 0.5 1 mA XTI HIGH-level input voltage V IH1 Clock input 0.7XVDD – – V NIPPON PRECISION CIRCUITS—4 SM5876AM Rating Parameter Symbol Condition Clock input Unit min typ max – – 0.3XVDD V XTI LOW-level input voltage V IL1 XTI AC-coupled input voltage V INAC 0.3XVDD – – V p-p HIGH-level input voltage2 V IH2 2.4 – – V LOW-level input voltage2 V IL2 – – 0.5 V HIGH-level output voltage3 VOHA IOH = −0.5 mA AV DD − 0.4 – – V LOW-level output voltage3 VOLA IOL = 0.5 mA – – 0.4 V CKO HIGH-level output voltage VOHC IOH = −0.5 mA DV DD − 0.4 – – V CKO LOW-level output voltage VOLC IOL = 0.5 mA – – 0.4 V XTI HIGH-level input current IIH1 V IN = XVDD – 4 15 µA XTI LOW-level input current IIL1 V IN = 0 V – 4 15 µA LOW-level input current2 IIL2 V IN = 0 V – 4 15 µA Input leakage current2 ILH V IN = DV DD – – 1.0 µA 1. DV DD = AV DD = XVDD = 3 V, CKSL = LOW (384fs), XTI clock input frequency fXTI = 16.9344 MHz, no output load, NPC-standard input data pattern. 2. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. 3. Pins LO, LON, RO, RON,MUTEO. AC Electrical Characteristics 5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = −40 to 85 °C 3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = −20 to 70 °C, CKSL = LOW (384fs system clock) System clock (XTI) Crystal Oscillator Rating Parameter Oscillator frequency Symbol fOSC Condition Unit min typ max 768fs 8.0 33.8688 35.6 MHz 384fs 4.0 16.9344 17.8 MHz External clock input Rating Parameter HIGH-level clock pulsewidth LOW-level clock pulsewidth Clock pulse cycle Symbol tCWH tCWL tXI Condition Unit min typ max 768fs 13.0 14.75 62.5 ns 384fs 26.0 29.5 125 ns 768fs 13.0 14.75 62.5 ns 384fs 26.0 29.5 125 ns 768fs 28.0 29.5 125 ns 384fs 56.0 59.0 250 ns NIPPON PRECISION CIRCUITS—5 SM5876AM XTI input clock t CWH VIH1 0.5VDD VIL1 t CWL t XI Serial input (BCKI, DI, LRCI) Rating Parameter Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns BCKI pulse cycle tBCY 1/(64fs) – – ns DI setup time tDS 50 – – ns DI hold time tDH 50 – – ns Last BCKI rising edge to LRCI edge tBL 50 – – ns LRCI edge to first BCKI rising edge tLB 50 – – ns Serial input timing t BCWH t BCY t BCWL BCKI 1.5V t DS t DH DI 1.5V t BL LRCI t LB 1.5V NIPPON PRECISION CIRCUITS—6 SM5876AM Control input (MCK, MDT, MLEN) Rating Parameter Symbol Unit min typ max MCK HIGH-level pulsewidth tMCWH 140 – – ns MCK LOW-level pulsewidth tMCWL 140 – – ns MCK pulse cycle tMCY 280 – – ns MDT setup time tMDS 100 – – ns MDT hold time tMDH 100 – – ns MLEN setup time tMLS 1/(192fs) + 20 – – ns MLEN hold time tMLH 1/(192fs) + 20 – – ns MLEN level pulsewidth T MLH 1/(192fs) + 20 – – ns Rise time tr – – 50 ns Fall time tf – – 50 ns Control input timing MCK 1.5V tMCWH tMCWL tMCY MDT 1.5V tMDH tMDS tMLH tMLS 1.5V MLEN tMLY tf MCK MDT MLEN tr 2.4V 2.4V 0.5V 1.5V 0.5V Reset Input (RSTN) Rating Parameter RSTN LOW-level pulsewidth after supply rising edge Symbol tRSTN Unit min typ max 50 – – ns NIPPON PRECISION CIRCUITS—7 SM5876AM Theoretical Filter Characteristics Deemphasis OFF overall characteristics Frequency band Attenuation (dB) Parameter f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.05 – +0.05 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 32 – – 0.4535fs 20.0 kHz – −0.34 – Passband ripple Stopband attenuation Built-in analog LPF compensation Overall frequency characteristic (deemphasis OFF) 0 10 Gain (dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 Frequency (fs) 5.0 6.0 7.0 8.0 Passband characteristic (deemphasis OFF) 0.0 Gain (dB) 0.2 0.4 0.6 0.8 0.000 0.125 0.250 0.375 0.4535 0.500 Frequency (fs) NIPPON PRECISION CIRCUITS—8 SM5876AM Deemphasis ON overall characteristics Frequency band Attenuation (dB) Parameter Deviation from ideal deemphasis filter characteristics Stopband attenuation Built-in analog LPF compensation f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.09 – +0.23 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 36 – – 0.4535fs 20.0 kHz – −0.34 – Overall frequency characteristic (deemphasis ON) 0 10 Gain (dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 Frequency (fs) 5.0 6.0 7.0 8.0 Passband characteristic (deemphasis ON) 0 2 Gain (dB) 4 6 8 10 12 0.000 0.125 0.250 Frequency (fs) 0.375 0.4535 0.500 NIPPON PRECISION CIRCUITS—9 SM5876AM AC Analog Characteristics 5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 5 V, AVDD = AVDDL = AVDDR, CKSL = 0 V, deemphasis OFF, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 °C Rating Parameter Symbol Condition Unit min typ max THD + N 1 kHz, 0 dB – 0.005 0.01 % LSI output level1 Vout1 1 kHz, 0 dB – 1.53 – V rms Evaluation board output level Vout2 1 kHz, 0 dB 1.8 2.0 2.2 V rms Dynamic range D.R 1 kHz, −60 dB 88 92 – dB Signal-to-noise ratio2 S/N 1 kHz, 0/−∞ dB 88 92 – dB Channel separation Ch. Sep 1 kHz, −∞/0 dB 84 86 – dB Total harmonic distortion 1. The LSI output level = 0.3058AV DD Vrms. 2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise. 3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 3 V, AVDD = AVDDL = AVDDR, CKSL = 0 V, deemphasis OFF, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 °C Rating Parameter Symbol Condition Unit min typ max THD + N 1 kHz, 0 dB – 0.007 – % LSI output level1 Vout1 1 kHz, 0 dB – 0.92 – V rms Evaluation board output level Vout2 1 kHz, 0 dB – 1.2 – V rms Dynamic range D.R 1 kHz, −60 dB – 90 – dB Signal-to-noise ratio2 S/N 1 kHz, 0/−∞ dB – 90 – dB Channel separation Ch. Sep 1 kHz, −∞/0 dB – 82 – dB Total harmonic distortion 1. The LSI output level = 0.3058AV DD Vrms. 2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise. NIPPON PRECISION CIRCUITS—10 SM5876AM AC Measurement Circuit and Conditions Measurement circuit block diagram CKO (768fs/384fs) BCK Signal Generator LRCK(fs) DATA Left Channel Evaluation L/R Channel Board Selector Right Channel fs= 44.1kHz DATA= 16bit Distortion Analyzer 10kΩ Input Impedance NF Corporation 3346A RMS Measurement Shibasoku AD725C Measurement conditions Parameter1 Total harmonic distortion Symbol THD + N 3346A left/right-channel selector switch THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF Output level Vout Dynamic range DR D-RANGE Signal-to-noise ratio S/N THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON Channel separation Ch. Sep THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF 1. Pins LO and RO should have an output load of 10 kΩ (min). NIPPON PRECISION CIRCUITS—11 MUTEO CKO MDT MCK LRCI BCKI DI MLEN CKSL RSTN J1 SW3 SM5876 MLEN CKSL CKO DVSS MCK MDT RSTN XVSS 10p X'tal MUTEO XVSS XTO XTI XVDD RO AVDDR RON SW4 BCKI DI DVDD LRCI AVSS 0.01µ 0.01µ 0.1µ 0.1µ 220µ + 0.1µ 0.1µ 220p 10k 10k 10k 220p 10k 10p 0.01µ + + DVSS DVDD 24k 100µ 24k 100µ 100µ 100µ 8.2k 8.2k 100µ 8.2k 8.2k + + TSTN LO AVDDL LON + XVDD U4 NJM5532 1/2 100p + 24k 100p U3 NJM5532 1/2 100p − − + 24k 100p 680p 15k 680p 15k 22k 22k AVSS AVDD U3 NJM5532 1/2 + − U4 NJM5532 1/2 100p 15k − + + + 100k 2.2µ 100k 2.2µ 0.01µ 10µ 10µ 100p 15k 0.01µ 0.01µ 0.01µ 10µ 10µ + + 100 100 AGND L OUTPUT R OUTPUT VEE VCC SM5876AM Measurement circuit NIPPON PRECISION CIRCUITS—12 SM5876AM FUNCTIONAL DESCRIPTION System Clock/Speed Switching (XTI, XTO, CKO, CKSL) Note that the input clock accuracy and signal-tonoise ratio greatly influence the AC analog characteristics. Accordingly, care should be taken to ensure that the clock is free from jitter. The system clock on XTI can be set to run at one of two speeds, 384fs (normal speed) or 768fs (doublespeed), where fs is the input frequency on LRCI. The speed for CD playback is set by the input level on CKSL, as shown in table 1. The system clock can be controlled by a crystal oscillator comprising a crystal connected between XTI and XTO and the built-in CMOS inverter. Alternatively, an external system clock can be input on XTI. As the internal CMOS inverter has a feedback resistor, the external clock can be AC coupled to XTI. The system clock is output on CKO. Table 1. System clock select CKSL Parameter Symbol HIGH LOW fXI (= 1/tXI) 768fs 384fs CD playback XTI frequency fXI 33.8688 MHz at fs = 44.1 kHz 16.9344 MHz at fs = 44.1 kHz CKO output clock frequency fCO 768fs 384fs TSYS 2tXI tXI XTI input clock frequency Internal system clock period System Reset (RSTN) The device should be reset in the following cases. ■ ■ ■ The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation and output timing counter are synchronized on the next LRCI rising edge, as shown in figure 1. At power ON When LRCI and/or the system clock XTI stop, or other abnormalities occur. When switching the XTI clock 768fs ⇔ 384fs. RSTN Low 1 2 3 9 10 LRCI Internal Reset LO(LON) RO(RON) Output Muted Figure 1. System reset timing Output mute At power-ON reset (when RSTN goes LOW), the outputs LO (LON) and RO (RON) enter the output mute state. Mute is released on the 9th LRCI rising edge after RSTN goes HIGH. During this cycle, the timing reset can cause output noise to be generated. NIPPON PRECISION CIRCUITS—13 SM5876AM Infinity-Zero Detector (analog mute control) Output (MUTEO) The SM5876AM outputs an infinity-zero detection output signal under the following circumstances. 1. When an infinity-zero occurs on both the left and right channels. 2. When an infinity-zero occurs in the input data for the channel set by the output mode setting. 3. When the output mode setting is muting for both the left and right channels. 4. When the attenuation counter for both the left and right channels is 0 (−∞). Also from immediately after a reset input on RSTN until the initialization cycle finishes and the first data cycle occurs. In cases 1 and 2, from when an infinity-zero is detected a period of 214 × (1/fs) ≈ 0.37 seconds takes place before MUTEO goes HIGH. In cases 3 and 4, from when the attenuation counter value is 0 a period of 214 × (1/fs) ≈ 0.37 seconds takes place before MUTEO goes HIGH. 214/fs 1 2 3 8 9 LRCI DI Signal No Signal Signal RSTN MUTEO Initialize Figure 2. MUTEO output timing Audio Data Input (DI, BCKI, LRCI) The digital audio data is input on DI in MSB-first, 2s-complement, 16-bit serial format. Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the bit clock BCKI. The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset, as long as the clock frequency ratio between LRCI and the system clock XTI is maintained, phase differences between LRCI, BCKI and the system clock XTI do not affect the functional operation. Also, any jitter present on the data input clock does not appear as output pulse jitter. The bit clock frequency on BCKI should be between 32fs and 64fs. Operating Modes (MLEN, MDT, MCK) The microcontroller data is used to control the following parameters. Digital attenuator Digital attenuation is controlled by attenuation data input on MDT. MDT, can control the left and right channels either independently or together (independent when the MDT attenuation control flag is LOW, and together when HIGH). The left-channel counter contents DATTL and the right-channel counter contents DATTR control the left-channel gain and right-channel gain, respectively, using the following equations. DATTL Left-channel gain = 20 × log ------------------- [dB] 255 DATTR Right-channel gain = 20 × log -------------------- [dB] 255 After system reset initialization, independent left/right-channel attenuation mode with the maximum gain of 0 dB is the default. Deemphasis filter (MDT DEM flag) The built-in digital deemphasis filter is designed to operate at 44.1 kHz. Deemphasis is ON when the DEM flag is HIGH, and OFF when the DEM flag is LOW. After reset, deemphasis OFF is the default. The attenuation operation is determined by a mathematical operation of the internal 8-bit up/down counter’s output data on the signal data. The 8-bit up/down counter, when attenuation data is input on NIPPON PRECISION CIRCUITS—14 SM5876AM Output mode setting (MDT 4-bit data) The left-channel and right-channel outputs can be set to any one of 16 different modes, as shown in table 2. Table 2. Output mode control PL0 PL1 PL2 PL3 Left-channel output Right-channel output Notes 0 0 0 0 Mute Mute Mute 0 0 0 1 Mute R 0 0 1 0 Mute L 0 0 1 1 Mute (L + R)/2 0 1 0 0 R Mute 0 1 0 1 R R 0 1 1 0 R L 0 1 1 1 R (L + R)/2 1 0 0 0 L Mute 1 0 0 1 L R 1 0 1 0 L L 1 0 1 1 L (L + R)/2 1 1 0 0 (L + R)/2 Mute 1 1 0 1 (L + R)/2 R 1 1 1 0 (L + R)/2 L 1 1 1 1 (L + R)/2 (L + R)/2 Reverse Stereo “Stereo” is the default after system reset. “Mute” refers to soft muting. Soft mute (output mode setting) The channel output muting set by the output mode control 4-bit data is soft mute mode. The attenuation counter output decrements by 1 step at a time, reducing the gain. The signal is completely muted after a time of (1024/fs), which corresponds to approximately 23.2 ms when fs = 44.1 kHz. Conversely, when soft mute is released using the output mode control, the attenuation counter output increments by 1 step at a time, increasing the gain. The time taken to return to 0 dB from full muting is also (1024/fs). When an attenuation value is set, the output gain decreases from the value set by the attenuation data until the gain is −∞. Similarly for mute release, the output gain increases from the current value until the gain is 0 dB. Upon system reset initialization, mute is released, which corresponds to the maximum gain of 0 dB. MUTE 0 dB Gain –∞ 1024/fs 1024/fs Figure 3. Soft mute operation example Attenuator control (ATC flag) The attenuator control (ATC) flag is input on MDT. When the ATC flag is HIGH, the left-channel and right-channel attenuator data is common. In this mode, the left-channel data is used for both channels. Soft mute operation is shown in figure 3. NIPPON PRECISION CIRCUITS—15 SM5876AM TIMING DIAGRAMS Input Timing (DI, BCKI, LRCI) 1/fs Left Channel Right Channel 16 bit DI MSB LSB 16 bit MSB LSB BCKI (64fs MAX) LRCI (MDT, MCK, MLEN) L channel Attenuation Data R channel Attenuation Data Output Mode Control MCK 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MDATA LSB MSB LSB 7 6 5 PL0 PL1 PL2 4 3 2 1 0 PL3 DEM ATC MSB MLEN Data is recognized on the rising edge of MLEN. NIPPON PRECISION CIRCUITS—16 SM5876AM TYPICAL APPLICATIONS Input Interface Circuit X'tal XTI XTO CKO 44.1kHz LRCI SM5876 DI 2.1168MHz BCKI Note that the output analog characteristics and other specifications are not guaranteed for a particular format or application circuit. Output Analog Processing Circuit (Left channel only is shown.) LON SM5876 − + LO LOUT NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koutou-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9504BE 1996.06 NIPPON PRECISION CIRCUITS—17