SUMMIT SMT4504

SMT4504
Preliminary Information1 (See Last Page)
Four-Channel Loss-Less TrakkerTM Power Supply Manager
FEATURES & APPLICATIONS
INTRODUCTION
• Loss-Less Tracking function
- No power MOSFET switches
• Programmable Slew-Rate, Tracking and Voltage
Monitoring Functions
• Directly Interfaces to DC-DC Converters,
Monolithic Controllers or LDOs
• Programmable Sequence Orders
• Programmable Tracking Slew Rates
• Eliminates Series Power MOSFETs
• Programmable OV/UV Threshold Limits
• Under Voltage Lock-Out (VDD and VCTRL_SUP)
• 4k-Bit user configurable Nonvolatile Memory
• I2C 2-wire serial bus for programming
configuration and monitoring status
Applications
• Monitor, Sequence and Slew-Rate Control of
Distributed Power and Point of Use Power
Supplies
• Multi-voltage Processors, DSPs, ASICs used in
Telecom, CompactPCI or server systems
The SMT4504 is an intelligent power supply
sequencer, tracker, and voltage monitor. The
SMT4504 tracks or sequences up to 4 power supplies
by uniquely controlling the Enable and TRIM (SoftStart) functions of DC-DC converters, Monolithic
Controllers or LDOs. Each Channel is individually
programmable for undervoltage/overvoltage threshold
settings, sequence position and slew rates. Two or
more supplies allocated to the same sequence
position are tracked, while assigning individual
supplies to a unique sequence position causes them
to be sequenced with controlled slew rates.
The SMT4504 monitors the supplies for faults and
is programmable to take any of several actions upon
the occurrence of a fault. The voltage monitoring
threshold step size is better than ±1%.
Power supply sequencing can be executed in any
order. During power-off sequencing, the SMT4504
sequences the supplies in the reverse order as poweron.
Using the I2C interface, a host system can
communicate with the SMT4504 status register,
optionally control power-on/off software and utilize 4Kbits of nonvolatile memory.
SIMPLIFIED APPLICATIONS DRAWING
5V
5V
GND
VDD
VCTRL_SUP
12V
VIN
VCTRLA
VDD_CAP
I2C
BUS
SDA
DC-DC
Converter
PUPA
SMT4504
V+
2.5VIN
TRIM
ON/OFF
V-
DSP/
µP/
NPU/
FPGA/
ASIC
VMA
Monolithic
Controller
SCL
GND
VIN
VCTRLB
PWR_ON#
PUPB
IRQ#
PWR_ON
-E/A
Soft-Start
V+
1.2VIN
V-
GND
VMB
IRQ#
Figure 1 – Applications Schematic, the SMT4504 Loss-Less TrakkerTM can track different types of supplies
together. Note: This is an applications example only. Some pins, components and values are not shown.
Summit Microelectronics, Inc
2071 1.1 01/07/05
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SMT4504
Preliminary Information
3 .3 V
2 .5 V
1 .8 V
1 .5 V
Figure 2A – Example Power Supply Sequencing and Tracking using the SMT4504. Any order of supply
sequencing/tracking can be applied using the SMT4504.
GENERAL DESCRIPTION
The SMT4504 consists of several major functional
blocks: the power supply monitors, the sequencing and
tracking outputs; the programmable output circuitry; the
timing and control block; the I2C interface and the
nonvolatile memory array.
The analog acquisition system monitors all channels via
the OV/UV sensors. The UV/OV sensors are the four
power supply voltage channels and the VDD and
VCTRL_SUP supplies. The setting of the OV/UV trip
points is made via the I2C serial data port.
Once PWR_ON is asserted a programmable delay timer
must first expire after which the PUP (Point of Use
Power) output(s) so required are enabled. The PUPs are
generally connected to the Enable pin of the converter
controlled by the SMT4504 Any channel not requiring
closed-loop tracking of the voltage is programmed to
assert its output (PUP) once the previous sequence
timer has expired. Otherwise all PUPs are asserted
upon the completion of the PWR_ON delay timer.
The power supply manager block is also used to assign
a given power supply a sequence position; sequence
timeout period and track-up/down slew rate setting.
These settings determine the time and the rate at which
each supply is turned on. When more than one supply is
assigned to a sequence position their voltages will be
Summit Microelectronics, Inc
tracked during the period of time when they are turned
on via the VCTRLX pins and monitored via the VMX pins.
These events are controlled by the sequence and
tracking block.
An additional feature of the SMT4504 allows the
supplies that are assigned the same sequence position
to be tracked at the same or different slew rates for
applications requiring supplies to be started at the same
time but to ramp up at different rates. (Figure 2A)
The next major block is a programmable output block.
The SMT4504 provides a great deal of flexibility in
choosing the fault trigger source for the fault outputs.
The sources include multiple combinations of UV/OV
conditions. The fault outputs’ assertion polarities are
also programmable.
Programming of the SMT4504 is performed over the
industry standard I2C, 2-wire serial data interface. It
allows configuration of the device, real-time control of
the power-on/power-off processes and reading of the
status registers. The bus interfaces the host to 4k bits of
nonvolatile memory and the programmable configuration
registers.
The 4k bits of user configurable nonvolatile memory
uses industry standard non-volatile memory technology.
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SMT4504
Advanced Information
3.3V
2.5V
1.8V
1.5V
tSR = 125% of Setting
tSR = 150% of Setting
tSR = 75% of Setting
tSR = 100% of Setting
Figure 2B – Example Power Supply Tracking flexibility using the SMT4xx4 set to the same sequence
position but different slew rates on each channel.
Summit Microelectronics, Inc
2071 1.1 01/07/05
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SMT4504
Preliminary Information
SIMPLIFIED BLOCK DIAGRAM
HEALTHY
VMA
MR#
IRQ_CLR#
IRQ & RST
Logic
Supply Manager A
Force
Shutdown
Arbitration
VMB
IRQ#
RST#
VCTRLA
PUPA
Supply Manager B
VCTRLB
PUPB
VCTRLC
VMC
VCTRLTracking/
Sequence Logic
Supply Manager C
PUPC
VCTRLD
PUPD
LINK_A
VMD
LINK_B
Supply Manager D
VRLINK
Enable
Logic
A0
Bus Interface
Configuration,
Status and GP
Registers
FS#
PWR_ON
WP
A1
SCL
SDA
VDD/VGG
Control
VDD_CAP
Summit Microelectronics, Inc
GND
2071 1.1 01/07/05
VGG
VDD
4
SMT4504
Preliminary Information
PIN DESCRIPTIONS
Pin Name
Type
Number
VCTRLC
VMC
VCTRLD
VMD
IRQ
OUT
IN
OUT
IN
OUT
1
2
3
4
5
HEALTHY
OUT
6
RST
OUT
7
LINK_B
I/O
8
LINK_A
I/O
9
GND
STATUSA
PWR
OUT
10
11
STATUSB
OUT
12
STATUSC
OUT
13
STATUSD
OUT
14
SEATED#
IN
15
FS#
I/O
16
PWR_ON
I/O
17
I/O
DATA
CLK
IN
IN
IN
IN
18
25
26
27
28
29
30
MR#
IN
31
GND
VDD
PWR
PWR
34
35
VRLINK
SDA
SCL
A0
A1
A2
WP
Summit Microelectronics, Inc
Function
Control voltage used to track/sequence the converters
Channel C converter output or sense+ line
Control voltage used to track/sequence the converters
Channel D converter output or sense+ line
Programmable active high/low open drain latched output. Asserted when
programmed power supply is in a fault condition.
Programmable active high/low output asserted when all Fault conditions are
clear
Programmable active high/low open drain output signals when all
programmed power supplies are within the monitored limits and the MR signal
is inactive. RST has a programmable timeout period with options for
0.64/50/100/200ms.
Active low open drain I/O connected to LINK_B pin other SMT4504’s for
linked operation
Active low open drain I/O connected to LINK_A pin other SMT4504’s for
linked operation
Ground of the part
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low input internally pulled up to VDD_CAP with 75k ohm resistor
Force shutdown active low I/O used to turn off all converter enable signals.
Do not drive FS# high.
Active high I/O signals the start of the power sequencing. When asserted the
part will sequence the supplies on and when de-asserted the part will
sequence the supplies off. Do not drive PWR_ON high.
External tracking ramp reference
Bi-directional I2C Data line
I2C Clock line
I2C device bus address assignment pin.
I2C device bus address assignment pin.
I2C device bus address assignment pin.
Programmable active high/low write protect input. When asserted the
configuration registers are write protected and the write protect volatile
register is set.
Active low input. When asserted the RST output will be allowed to de-assert
after a reset timeout if there are no reset sources still active.
Ground of the part
Power supply of the part
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SMT4504
Preliminary Information
PIN DESCRIPTIONS (CONTINUED)
Pin Name
Type
Number
VCTRL_SUP
PWR
37
VDD_CAP
PUPA
PUPB
PUPC
PUPD
VCTRLA
VMA
VCTRLB
VMB
GND
N/C
CAP
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
PWR
N/C
38
39
40
41
42
43
44
45
46
47
19-24, 32,
33, 36, 48
Function
Voltage supply input used for driving the VCTRLX outputs. Programmable for
5V, 8V or 12V.
External capacitor input used to filter the internal supply voltage
Programmable active high/low open drain converter enable output
Programmable active high/low open drain converter enable output
Programmable active high/low open drain converter enable output
Programmable active high/low open drain converter enable output
Control voltage used to track/sequence the converters
Channel A converter output or sense+ line
Control voltage used to track/sequence the converters
Channel B converter output or sense+ line
Ground of the part
No Connect
PACKAGE AND PIN CONFIGURATION
NC
VDD
VMB
VCTRLB
VMA
VCTRLA
PUPD
PUPC
PUPB
PUPA
VDD_CAP
WAS_SUP?
48
47
46
45
44
43
42
41
40
39
38
37
48 LEAD TQFP
VCTRLC
1
36
NC
VMC
2
35
VDD
VCTRLD
3
34
GND
VMD
4
33
NC
SCL
STATUSB
12
25
SDA
Summit Microelectronics, Inc
24
26
NC
11
23
STATUSA
NC
A0
22
27
NC
10
21
GND
NC
A1
20
28
NC
9
19
LINK_A
NC
A2
18
29
VRLINK
8
17
LINK_B
PWR_ON
WP
16
30
FS#
7
15
RST
SEATED#
MR#
14
NC
31
STATUSD
32
6
13
5
STATUSC
IRQ
HEALTHY
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SMT4504
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias ...................... -55°C to 125°C
Storage Temperature............................ -65°C to 150°C
Terminal Voltage with Respect to GND:
VMA, VMB, VMC, VMD ....................-0.3V to 6.0V
PUPA, PUPB, PUPC, PUPD ........................................ 15V
All Others .........................................VDD + 0.7V
Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 secs) .................... 300°C
Junction Temperature.......................…….....…...150°C
ESD Rating per JEDEC…………………..…..…..1000V
Latch-Up testing per JEDEC………..…..…......±100mA
Stresses listed under Absolute Maximum Ratings may cause permanent to
the device. These are stress ratings only and functional operation of the
device at these or any other conditions outside those listed in the operational
sections of the specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device performance and
reliability.
Devices are ESD sensitive. Handling precautions are
recommended.
Temperature Range (Industrial)...........–40°C to +85°C
(Commercial) ............–5°C to +70°C
VDD Supply Voltage .................................. 2.7V to 5.5V
12VIN Supply Voltage.............................. 8.0V to 15.0V
VIN ............................................................ GND to VDD
VOUT ...................................................... GND to 15.0V
Package Thermal Resistance (θJA)
48 Lead TQFP………………..……………….…80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
RELIABILITY CHARACTERISTICS
Data Retention…………………………..…..100 Years
Endurance…………………….……….100,000 Cycles
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
3.3V aux supply
Min.
Typ.
Max
Unit
2.7
5.5
V
4.5
14
V
VDD
Supply Voltage
VCTRL_SUP
VCTRLX Supply Voltage
IDD
Power Supply Current
TBD
mA
IGG
Power Supply Current
TBD
mA
PVIT
Programmable Threshold (VMX
Inputs)
X-bit resolution
XXmV/bit
TBD
6.0
V
PVIT
Programmable Threshold (VDD and
VGG Inputs)
X-bit resolution
XXmV/bit
TBD
V
PUP characteristics
VOL
Output Low Voltage
ISINK = TBD
0
0.4
V
VDD = 2.7V
0.9xVDD
VDD
V
VDD = 5.0V
0.7xVDD
VDD
V
VDD = 2.7V
-0.1
0.1xVDD
V
VDD = 5.0V
-0.1
0.3xVDD
V
ISINK = TBD
0
0.4
V
All other input and output characteristics
VIH
Input High Voltage (FS,
PWR_ON/OFF, MR#)
VIL
Input Low Voltage (FS, PWR_ON,
MR)
VOL
Programmable Open Drain Outputs
(RST#, FS#, IRQ#)
Summit Microelectronics, Inc
2071 1.1 01/07/05
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SMT4504
Preliminary Information
PROGRAMMABLE AC SPECIFICATIONS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
tDPON
TTRACKER_SLEW
TTRACKER_SLEW
tPRTO
Description
Min.
Programmable delay from PWR_ON to PUPs
asserted and PUP to PUP delay
Programmable internal tracking on/off slew rate
Programmable external tracking on/off slew rate
step size (25V/S-250V/S)
Programmable Reset Timeout Periods
Typ.
Max.
Unit
0.64
ms
12.5
ms
25
ms
50
ms
250
V/S
500
V/S
750
V/S
1000
V/S
25
V/S
0.64
mS
50
mS
100
mS
200
mS
OFF
tABORT
Programmable Abort Power-On/Off Timer
Summit Microelectronics, Inc
2071 1.1 01/07/05
100
ms
200
ms
400
ms
8
SMT4504
Preliminary Information
APPLICATIONS INFORMATION
SEQUENCING
The SMT4504 is a programmable controller for
lossless (requires no pass MOSFETs) power supply
sequencing/tracking. Up to four channels can be
sequenced in any order with several delay options.
Before the SMT4504 begins the power-on sequencing,
the UV sensors monitor the VDD and the
VCTRL_SUP inputs. The power-on sequencing will
not begin until both these inputs are above their UV
threshold.
In order for a power supply to be sequenced it must
first be enabled by a PUP output. This channel must
also be programmed to participate in the sequence
and be assigned a sequence position (one of 12). A
sequence position is given to each channel as an
order number in the sequence event. The sequence
position assignments must begin at position 1 and
must not skip positions. Also, multiple channels can be
programmed into the same sequence position to
enable voltage tracking of the supplies. Multiple
corresponding channels sharing a common sequence
position will have their voltages tracked during the
power-on and power-off events only if each channel
uses the VCTRLX pin on the converter. Otherwise the
PUP output simply enables this power supply with no
regard for closed loop voltage tracking.
Each channel selected for sequencing is given a
power-on and power-off delay. The first power-on
delay is a delay from assertion of the PWR_ON input
to the assertion of all PUP outputs (sequence position
1). The power-off delay is the delay from the VMX input
of one channel turning off to the beginning of another
VMx output turning off. Tracking or sequencing down
begins immediately when the PWR_ON pin is deasserted.
Power-on sequencing can be initiated by asserting the
PWR_ON/OFF input or by writing to the power-on bit
of the command register. For automatic start-up the
PWR_ON/OFF pin can be tied active. The power-on
sequencing begins with the power-on delay time of the
channel(s) in sequence position 1. Once this delay has
timed out all PUP outputs assigned to this position will
go active. At this point the supply connected to the
VM input will begin to turn on via the action between
the VCTRLX output and the supply’s TRIM or other
interface pin such as soft-start. When this supply
reaches its programmed threshold (under-voltage) and
the sequence delay timer is expired, the sequence
position counter will change to position 1 and the
Summit Microelectronics, Inc
power-on delay timer for the channel(s) in sequence
position 2 will begin. This will repeat until all channels
that were programmed for sequencing have turned on
and are not in fault conditions. Power-on sequencing
is considered complete when supplies assigned the
last used sequence position go above their UV setting.
Power-off sequencing can be initiated by de-asserting
the PWR_ON/OFF pin, by writing to the power-off bit
of the command register, or triggered off of a selected
fault condition.
The SMT4504 is configured to
sequence the supplies off in the reverse order of the
power-on sequence. During the power-off sequence
power-on commands as well as activity on the
PWR_ON/OFF pin is ignored.
The power-off sequencing begins immediately with the
channel(s) in the last sequence position of the poweron sequence (reverse order). Once the supplies in this
sequence position have reached 100mV or less and
the delay timer has timed out the PUP will turn off. At
this point the supply connected to the next sequence
position will begin to turn off. When this supply falls
below the 100mV limit, the sequence position counter
will change to the next position and the power-off
delay timer for the channel(s) in current sequence
position will begin.
This will repeat until all channels that were
programmed for sequencing have turned off. At this
point the SMT4504 will monitor the VDD and
VCTRL_SUP inputs as precursor conditions to poweron sequencing.
During sequencing an abort timer is available. The
abort timer starts each time a PUP output goes active.
If the abort timer times out before the VMX input goes
out of fault, all channels are shut down and the abort
bit is set in the status register. This is to avoid the case
where one or more channels are not capable of
reaching their minimum level. The abort timer is
available for sequence up and sequence down. If the
abort timer shuts the sequencing down the
PWR_ON/OFF pin must be toggled to re-start. The
timeout period of the abort timer is programmable.
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SMT4504
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
MONITORING
Once the power-on sequence is underway, the
SMT4504 monitors VMX inputs and the VDD and
VCTRL_SUP supply voltages. The SMT4504
compares the voltages with the programmable low and
high limits (UV/OV). Each of these limits can be
programmed to trigger the RST, IRQ# or HEALTHY
input as well as a force shutdown or power-off
operation if exceeded.
FORCED SHUTDOWN
The Forced Shutdown function is used to immediately
turn off all PUP outputs when there is not enough time
to perform a power-off sequence. Forced Shutdown
can be initiated by asserting the FS pin, by writing to
the forced shutdown bit of the command register, or
triggered by one or more channels going out of limits.
Forced Shutdown cannot be triggered by a channel
going out of limit until the power-on sequence has
completed. Forced Shutdown will latch the PUP
outputs in the off state until the FS pin is de-asserted
and the PWR_ON pin is toggled. Input on the
PWR_ON pin will be ignored until all supplies are
below their OFF thresholds.
COMMUNICATING WITH THE SMT4504
All communication with the SMT4504 takes place over
the I2C bus. The part has several registers that contain
information about the channels that are being
controlled and the set point and limit information. The
slave address for the configuration registers and the 4k of memory is programmable. When accessing the
configuration registers, [A1, A0] is used as the bus
address. Write protection for the SMT4504 is located
in a volatile register where the power-on state is
defaulted to write protect.
SUMMARY OF DEVICE OPERATION
When the SMT4504 first receives power it will hold all
PUP outputs and the HEALTHY output in their inactive
state. The RST output will be held active. At this point,
the VCTRLX outputs will be turned on to their
respective programmed voltages. The device will then
monitor the VDD and VCTRL_SUP inputs until both
are in the appropriate range.
Summit Microelectronics, Inc
Once the PWR_ON/OFF signal goes active and the
VDD and VCTRL_SUP input is within range, the PUP
outputs of all channels in sequence position 1 will go
active and the device will monitor those converter
outputs. Once those converter outputs have gone
above the UV settings, the PUP outputs of the
channels in sequence position 2 will go active.
As the channels are powering on, the device will
monitor the VDD and VCTRL_SUP inputs. The
HEALTHY output will go active when all trigger
sources are within their programmed limits. The RST
output will go inactive a programmable timeout period
after all trigger sources are within their programmed
limits and the MR signal has gone inactive.
During the power-on sequence an abort timer will start
as each PUP output goes active. The channel that is
associated with that PUP must reach its lower limit
before the abort timer expires. If it does not then all
channels are shut down and the Abort Timer bit is set
in Status Register1.
Once the power-on sequence is complete, the device
will monitor all. The result of each monitor conversion
will be compared against the preset high and low limits
for that channel. If a voltage channel is found to be out
of limits then HEALTHY will be de-asserted. In either
case the UV/OV sensors will continue to monitor all
channels. When the problem channel is back in limits
the HEALTHY will be asserted again. The number of
sequential conversions that must be completed in
order to declare in or out of limit is set in Configuration
Register 1. The state of the channels can be checked
by reading the status registers.
When the PWR_ON/OFF pin is de-asserted the device
will begin a power-off operation. First, HEALTHY will
go inactive. Then the SMT4504 will de-assert the last
VCTRLX (or PUP) output and monitor the
corresponding voltage output. When the output has
dropped below the “off” limit for a programmed number
of consecutive conversions the next VCTRLX (or PUP)
outputs will be de-asserted in the reverse sequence
order as power-on (3-0). A power-off operation can
also be initiated by a fault condition on any of the
channels. During the power-off sequencing the abort
timer is again used to ensure that the sequencing
takes place properly. If the abort timer finishes before
a channel drops below the off level, all channels will
be shut down and the Abort Timer bit is set in Status
Register 1.
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SMT4504
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The end user can obtain the Summit SMX3200
programming
system
for
device
prototype
development. The SMX3200 system consists of a
programming Dongle, cable and WindowsTM GUI
software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
SMX3200
is
available
from
the
website
(www.summitmicro.com).
The SMX3200 programming Dongle/cable interfaces
directly between a PC’s parallel port and the target
application. The device is then configured on-screen
via an intuitive graphical user interface employing
drop-down menus.
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be
directly downloaded to the SMT4504 via the
programming Dongle and cable. An example of the
connection interface is shown in Figure 4.
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations.
This will ensure proper device
operation in the end application.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable conn
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
Positive
Supply
VDD_CAP
SMT4504
MR#
SDA
SCL
10
8
6
4
2
9
7
5
3
1
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserv
Pin 3, GND
Pin 1, GND
0.1µF
GND
Common
Ground
Figure 4 – SMX3200 Programmer I2C serial bus connections to program the SMT4504.
Summit Microelectronics, Inc
2071 1.1 01/07/05
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SMT4504
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (tHIGH)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM665.
The device type identifier for the memory array is
generally set to 1010BIN following the industry standard
for a typical nonvolatile memory. There is an option to
change the identifier to 1011BIN allowing it to be used
on a bus that may be occupied by other memory
devices. The configuration registers are grouped with
the memory array and thus use 1010BIN or 1011BIN as
the device type identifier. The command and status
registers as well as the 10-bit ADC are accessible with
the separate device type identifier of 1001BIN.
The bus address bits A[1:0] are programmed into the
configuration registers. Bus address bit A[2] can be
programmed as either 0 or biased by the A2 pin. The
bus address accessed in the address byte of the serial
data stream must match the setting in the SMM665
and on the A2 pin.
Summit Microelectronics, Inc
Any access to the SMM665 on the I2C bus will
temporarily halt the monitoring function. This is true
not only during the monitor mode, but also during
Power-on and Power-off sequencing when the device
is monitoring the channels to determine if they have
turned on or turned off.
The SMM665 halts the monitor function from when it
acknowledges the address byte until a valid stop is
received.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 8, 9, 11, 13 and 14. A Start
condition followed by the address byte is provided by
the host; the SMM665 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM665 responds with an acknowledge;
the host then clocks in on byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM665. This is accomplished by a issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 10, 12 and 15 for an
illustration of the read sequence.
2071 1.1 01/07/05
12
SMT4504
Preliminary Information
The word address must be set each time the memory
2
I C PROGRAMMING INFORMATION (CONTINUED)
is accessed. Memory writes and reads are shown in
Figures 13, 14 and 15.
The SMM665 powers up into a write protected mode.
Writing a code to the volatile write protection register
COMMAND AND STATUS REGISTERS
can disable the write protection. The write protection
The command and status registers are located at
register is located at address 87HEX of slave address
slave address 1001BIN. Writes and reads of the
1001BIN.
command and status registers are shown in Figures
Writing 0101BIN to bits [7:4] of the write protection
16 and 17.
register allow writes to the general-purpose memory
ADC CONVERSIONS
while writing 0101BIN to bits [3:0] allow writes to the
An ADC conversion on any monitored channel can be
configuration registers. The write protection can reperformed and read over the I2C bus using the ADC
enable by writing other codes (not 0101BIN) to the write
read command. The ADC read command, shown in
protection register. Writing to the write protection
Figure 18, starts with a dummy write to the 1001BIN
register is shown in Figure 7.
slave address. Bits [6:3] of the word address byte are
CONFIGURATION REGISTERS
used to address the desired monitored input. Once
The majority of the configuration registers are grouped
the device acknowledges the channel address, it
with the general-purpose memory located at either
begins the ADC conversion of the addressed input.
slave address 1010BIN or 1011BIN. The bus address
This conversion requires 70µs to complete. During
bits, A[1:0], used to differentiate the general-purpose
this conversion time, acknowledge polling can be
memory from the configuration registers are set to
used. The SMM665 will not acknowledge the address
11BIN. Bus address bit A[2] can be programmed as
bytes until the conversion is complete. When the
either 0 or biased by the A2 pin.
conversion has completed, the SMM665 will
Two additional configuration registers are located at
acknowledge the address byte and return the 10-bit
addresses 83HEX and 84HEX of slave address 1001BIN.
conversion along with a 4-bit channel address echo.
Writing and reading the configuration registers is
GRAPHICAL USER INTERFACE (GUI)
shown in Figures 8, 9, 10,11 and 12.
Device configuration utilizing the Windows based
Note: Configuration writes or reads of registers 00HEX
SMM665 graphical user interface (GUI) is highly
to 0FHEX should not be performed while the SMM665 is
recommended. The software is available from the
margining.
Summit website (www.summitmicro.com). Using the
GUI in conjunction with this datasheet and Application
GENERAL-PURPOSE MEMORY
Note 33, simplifies the process of device prototyping
The 4k-bit general-purpose memory is located at
and the interaction of the various functional blocks. A
either slave address 1010BIN or 1011BIN. The bus
programming Dongle (SMX3200) is available from
address bits, A[1:0], used to differentiate the generalSummit to communicate with the SMM665. The
purpose memory from the configuration registers are
Dongle connects directly to the parallel port of a PC
set to 00BIN for the first 2k-bits and 01BIN for the second
and programs the device through a cable using the I2C
2k-bits. Bus address bit A[2] can be programmed as
bus protocol.
either 0 or biased by the A2 pin.
Slave Address
Bus Address
Register Type
1001BIN
A2 A1 A0
1010BIN
or
1011BIN
A2 0 0
A2 0 1
A2 1 1
Write Protection Register,
Command and Status Registers,
Two Configuration Registers,
ADC Conversion Readout
1st 2-k Bits of General-Purpose
Memory nd
2 2-k Bits of General-Purpose
Memory
Configuration Registers
Table 1 - Address bytes used by the SMM665.
Summit Microelectronics, Inc
2071 1.1 01/07/05
13
SMT4504
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S
T
A
R
T
Configuration
Register Address = 87 HEX
Bus Address
1
0
0
A
2
1
A
1
A
0
W
1
0
A
C
K
Slave
0
0
0
1
8 H EX
S
T
O
P
Data = 55 HEX
1
1
0
1
0
1
0
1
0
1
A
C
K
7 HEX
A
C
K
5 HEX Unlocks
General Purpose
EE
W rite Protection
Register Address
5 HEX Unlocks
Configuration
Registers
Figure 7 – Write Protection Register Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
S
A
0
1
A
2
1
1
C
7
W
C
6
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 8 – Configuration Register Byte Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
A
2
1
1
C
7
W
C
6
C
5
C
4
C
3
C
2
Data (1)
C
1
C
0
A
C
K
Slave
D
7
D
6
D
7
D
6
Slave
D
5
D
4
D
3
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Data (2)
Master
D
5
S
T
O
P
Data (16)
D
2
D
1
D
0
D
7
D
6
D
5
A
C
K
D
2
D
1
D
0
D
7
D
6
D
5
A
C
K
D
4
D
3
D
2
D
1
D
0
A
C
K
Figure 9 – Configuration Register Page Write
Summit Microelectronics, Inc
2071 1.1 01/07/05
14
SMT4504
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
A
2
1
1
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
S
A
0
A
2
1
1
R
A
C
K
A
C
K
D
7
0
A
C
K
A
C
K
Data (1)
Bus Address
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 10 - Configuration Register Read
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
0
1
A
2
A
1
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 11 - Configuration Register with Slave Address 1001BIN Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
0
1
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
A
2
A
1
A
0
R
A
C
K
A
C
K
D
7
0
A
C
K
A
C
K
Data (1)
Bus Address
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 12 - Configuration Register with Slave Address 1001BIN Read
Summit Microelectronics, Inc
2071 1.1 01/07/05
15
SMT4504
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
0
1
S
A
0
1
A
2
0
/
1
0
C
7
W
C
6
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 13 – General Purpose Memory Byte Write
S
T
A
R
T
Master
Configuration
Register Address
Bus Address
0
1
S
A
0
1
A
2
0
/
1
0
C
7
W
C
6
C
5
C
4
C
3
Data (1)
C
2
C
1
C
0
D
7
A
C
K
Slave
Master
D
6
D
5
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
S
T
O
P
Data (16)
Data (2)
D
7
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
A
C
K
Slave
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 14 - General Purpose Memory Page Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
A
2
0
0
/
1
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
A
2
0
0
/
1
R
A
C
K
A
C
K
D
7
0
A
C
K
A
C
K
Data (1)
Master
Bus Address
S
A
0
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 15 - General Purpose Memory Read
Summit Microelectronics, Inc
2071 1.1 01/07/05
16
SMT4504
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Command and Status
Register Address
Bus Address
1
0
0
1
A
2
A
1
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 16 – Command and Status Register Write
Master
S
T
A
R
T
Command and Status
Register Address
Bus Address
1
0
0
1
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
A
2
A
1
A
0
R
A
C
K
A
C
K
D
7
0
A
C
K
A
C
K
Data (1)
Master
Bus Address
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 17 - Command and Status Register Read
Master
S
T
A
R
T
1
0
0
1
Bus Address
Channel Address
A
2
C
H
3
A
1
A
0
C
H
1
C
H
0
0
0
0
A
C
K
Slave
Master
0
W
C
H
2
S
T
A
R
T
S
T
A
R
T
Slave
0
0
1
A
2
A
1
A
0
0
0
1
A
2
A
1
A
0
R
0
C
H
3
C
H
2
C
H
1
C
H
0
N
A
C
K
A
C
K
Channel Address Echo
R
1
A
C
K
Bus Address
1
Bus Address
0
D
9
D
8
N
A
C
K
10-Bit ADC Data
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 18 – ADC Conversion Read
Summit Microelectronics, Inc
2071 1.1 01/07/05
17
SMT4504
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS – SMT4504-172
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF
R10
R11
R12
R13
R14
R15
R18
R19
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R3A
R3B
R3C
R3D
R3E
R40
R41
Contents
0D
83
0D
FF
0E
61
0E
C7
0F
54
0B
22
7F
3F
03
01
8F
9F
AF
BF
CF
DF
00
00
0D
60
0D
DC
0E
45
0E
A2
0F
08
0F
D6
00
12
48
0D
B9
Register
R42
R43
R44
R45
R46
R47
R48
R49
R4A
R4B
R4C
R4D
R4E
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R8A
R8B
R8C
R8D
R8E
R8F
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
R9A
R9B
Contents
0E
39
0E
A4
0F
16
0F
B4
06
7F
00
12
48
42
48
82
3E
2A
B8
12
F6
41
C8
81
B9
2A
34
12
49
49
5C
81
52
29
D7
11
EB
41
3E
81
33
Register
R9C
R9D
R9E
R9F
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RAA
RAB
RAC
RAD
RAE
RAF
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB8
RB9
RBA
RBB
RBC
RBD
RBE
RBF
RC0
RC1
RC2
RC3
RC4
Contents
29
9A
11
AE
41
0B
80
F6
29
5D
11
71
40
CE
80
8F
29
1F
11
33
2A
67
0A
52
03
FF
03
FF
0D
9A
0D
56
0F
E0
0F
E0
0B
38
0B
38
09
Register
RC5
RC6
RC7
RC8
RC9
RCA
RCB
RCC
RCD
RCE
RCF
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
REA
REB
Contents
90
09
90
0C
00
0C
00
0F
FF
0F
FF
0C
00
0C
00
0F
D8
0F
D8
00
3D
00
3D
00
3D
00
3D
00
3D
00
3D
RC1
The default device ordering number is SMT4504F-172, is programmed as described above
and tested over the commercial temperature range. Application Note 33 contains a
complete description of the Windows GUI and the default settings of each of the 154
individual Configuration Registers.
Summit Microelectronics, Inc
2071 1.1 01/07/05
18
SMT4504
Preliminary Information
PACKAGES
48 PIN TQFP PACKAGE
0.354
(9.00)
BSC (A)
0.276
(7.00)
BSC (B)
Inches
(Millimeters)
0.02
(0.5)
BSC
0.007 - 0.011
(0.17 - 0.27)
DETAIL "A"
(B)
(A)
0.037 - 0.041
0.95 - 1.05
Pin 1
Indicator
0.039
(1.00)
0.047
MAX.
(1.2)
A
B
0 o Min to
8 o Max
0.004 - 0.008
(0.09 - 0.20)
0.018 - 0.030
(0.45 - 0.75)
DETAIL "B"
Summit Microelectronics, Inc
2071 1.1 01/07/05
19
SMT4504
Preliminary Information
PART MARKING
Summit Part Number
SUMMIT
SMT4504F
Annn
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
xx
AYYWW
Pin 1
Date Code (YYWW)
Lot tracking code (Summit use)
Part Number suffix
(Contains Customer specific ordering requirements)
Drawing not to scale
Product Tracking Code (Summit use)
ORDERING INFORMATION
SMT4504
Summit Part Number
F
nnn
Part Number Suffix (see page 18)
Specific requirements are contained in the suffix
such as Commercial or Industrial Temp Range,
Hex code, Hex code revision, etc.
Package
F=48 Lead TQFP
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.
Revision 1.1 - This document supersedes all previous versions.
Please check the Summit Microelectronics, Inc. web site at
www.summitmicro.com for data sheet updates.
© Copyright 2005 SUMMIT MICROELECTRONICS, Inc.
Power Management for Communications™
I2C is a trademark of Philips Corporation. MS Windows is a trademark of Microsoft Corporation.
Trakker and Loss-Less Trakker are trademarks of Summit Microelectronics Inc.
Summit Microelectronics, Inc
2071 1.1 01/07/05
20