TI SN65HVD96DR

SN65HVD96
www.ti.com
SLLSE35 – JUNE 2010
SymPol™ Transceiver
Check for Samples: SN65HVD96
FEATURES
•
1
•
2
•
•
•
•
Communicate Without Errors on Normal or
Reversed-Wire Bus Lines
Up to 5 Mbps Signaling
Industrial Temperature Range: –40°C to 85°C
Symmetric Polarity Receiver
Thresholds ≥ 100 mV Receiver Hysteresis
Connect up to 32 Nodes on one Bus
•
Transient Protection
– ±12 kV Human Body Model on Bus Pins
– ±25 V Repetitive Transient Pulse on Bus
Pins
Additional Reliability Features:
– Bus Standoff From –35 V to 40 V
– Driver Output Short-Circuit Current Limit
– Automatic Thermal Shutdown and
Recovery
DESCRIPTION
The SN65HVD96 is specifically designed to meet the requirements for a transceiver which operates with no
errors if the twisted-pair signal wires are connected normally or reversed. This allows for error free operation in
applications where the signal wires may become inadvertently reversed during installation or maintenance. This
feature is corrected internally so no intervention from the controller or operator is required.
Similar to RS-485, these transceivers can be used for point-to-point, multi-drop, or multi-point networks.
Sympol™ devices are not backwards compatible with, but are an upgrade to, existing RS-485 networks. The
pin-out is identical to the industry-standard SN75176 transceiver, allowing direct upgrade from RS-485 to
SymPol. Current-limited differential outputs protect in case of driver contention on a party-line bus. High receiver
input impedance allows connection of at least 32 nodes. Several fault tolerant features are integrated into the
device from operational hazards. Current limiting on the driver outputs protects against short-circuit faults, and
operates independently on each driver output. An automatic thermal shutdown protects the driver circuits against
over temperature conditions. The receiver output enters a deterministic failsafe state if the bus connection is left
disconnected or if the bus wires are shorted together.
The small outline integrated circuit (SOIC) package saves board space compared to equivalent discrete
implementations. These devices are fully characterized for operation over the industrial temperature range of
–40°C to 85°C.
SN65HVD96
R
RE
DE
Driver signaling(DE = high)
8
1
D
A or B
B
B or A
A
|VID|
2
3
VOD
7
D
Vcc
4
Receiver detecting(RE = low)
passive
active
passive
active
R
B
6
A
Temp.
SHDN
5
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Sympol is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN65HVD96
SLLSE35 – JUNE 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.5 to 7
V
–35 to 40 dc
V
–0.3 to VCC+0.3
V
±25 dc
V
Voltage input transient pulse, A and B, per ISO 7637
±200
V
Electro-static discharge per JEDEC Std. 22 A114 A and B, Human Body Model
±12
kV
Electro-static discharge per JEDEC Std. 22 A114 all pins, Human Body Model
±5
kV
Electro-static discharge per JEDEC Std. 22 C101 all pins, Charged Device Model
±2
kV
Supply voltage, VCC
Voltage range at A or B
Voltage range at logic pins (D, DE, RE)
Voltage input range, transient pulse, A and B, through 100Ω
Electro-static discharge per JEDEC Std. 22 A115 all pins, Machine Model
±200
V
Receiver output current
±20
mA
170
°C
Junction temperature, TJ
Continuous total power dissipation
(1)
(see Dissipation Rating Table)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
SN65HVD96
THERMAL METRIC (1)
qJA
Junction-to-ambient thermal resistance (2)
qJC(top)
Junction-to-case(top) thermal resistance
qJB
Junction-to-board thermal resistance
UNITS
124.5
(3)
55.9
(4)
50.2
(5)
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
qJC(bottom)
8 PINS SOIC
Junction-to-case(bottom) thermal resistance
4.9
(6)
°C/W
46.0
(7)
n/a
TEST CONDITIONS
Pd
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2
Power Dissipation
VCC = 5.25 V, TJ = 150°C, RL = 300 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver) 290 5-V supply, unterminated (8)
188
VCC = 5.25 V, TJ = 150°C, RL = 100 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver) 5-V supply, RS-422 load (8)
251
VCC = 5.25 V, TJ = 150°C, RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver) 5-V supply, RS-485 load (8)
319
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Driver and receiver enabled, 50% duty cycle square-wave signal at 5 Mbps.
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SN65HVD96
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SLLSE35 – JUNE 2010
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
–7
12
V
High-level input voltage (Driver, driver enable, and receiver enable inputs)
2
VCC
V
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
0
0.8
V
Differential input voltage
–12
12
V
IO
Output current, Driver
–70
70
mA
IO
Output current, Receiver
–2
2
mA
RL
Differential load resistance
54
1/tUI
Signaling rate
TA
Operating free-air temperature
VCC
Supply voltage
VI
Input voltage at any bus terminal (separately or common mode) (1)
VIH
VIL
VID
(1)
Ω
60
0
5
Mbps
–40
85
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD(ACT)|
TEST CONDITIONS
Driver differential output voltage
magnitude (active)
MIN
RS-485 common-mode load, see Figure 2
1.5
RS-485 differential load RL = 54 Ω,
CL = Open, see Figure 3
1.5
RS-422 differential load RL = 100 Ω,
CL = Open, see Figure 3
|VOD(PAS)|
Driver differential output voltage
magnitude (passive)
TYP
MAX
UNIT
V
2
RS-485 common-mode load, See Figure 2
50
RS-485 differential load RL = 54 Ω,
CL = Open, see Figure 3
20
RS-422 differential load RL = 100 Ω,
CL = Open, see Figure 3
25
No Load
50
mV
VOC(SS)
Steady-state common-mode output
voltage
Voc = (VA + VB) / 2
RL = 54Ω
ΔVOC
Change in differential driver output
common-mode voltage
Voc(D=High) – Voc(D=Low)
RL = 54Ω
VIT(ACT)
Active-going receiver differential input
threshold
VID = VA – VB or VID = VB – VA
VIT(PASS)
Passive-going receiver differential input
threshold
500
625
mV
VHYS
Receiver differential input threshold
hysteresis (VIT(ACT) - VIT(PASS))
100
150
mV
VOH
Receiver high-level output voltage
–20 µA ≥ IO ≥ –2 mA
VOL
Receiver low-level output voltage
20 µA ≤ IO ≤ 2 mA
II
Logic pins input current
IOZ
Receiver output high-impedance current
VO = 0 V or Vcc, RE at Vcc
IOS
Driver short-circuit output current
–7 V < Vo < +12 V
II
Bus input current (passive driver)
Vcc = 4.75 to 5.25 V or
Vcc=0V, DE at 0V, other
bus pin at 0V
ICC
Supply current (quiescent), no load
1
Vcc/2
–0.2
775
2.4
–100
V
0.2
V
900
mV
3.7
V
100
mA
–10
10
uA
350
mA
1
mA
–0.8
mA
20
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V
0.4
–350
VI = 12 V
VI = –7 V
3
mA
3
SN65HVD96
SLLSE35 – JUNE 2010
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
trise , tfall
Driver differential output rise/fall time
15
30
ns
tpAP , tpPA
Driver propagation delay
40
80
ns
tSK(P)
Driver differential output pulse skew,
|tpAP – tpPA|
1
10
ns
tpZA, tpAZ
Driver enable/disable time
D = GND, RL= 54 Ω, CL= 50 pF,
See Figure 4
50
80
ns
8
15
ns
CL= 15 pF, See Figure 5
70
90
ns
5
15
ns
20
100
ns
RL= 54 Ω, CL= 50 pF, See Figure 3
RECEIVER
trise, tfall
Receiver output rise/fall time
tPHL , tPLH
Receiver propagation delay time
tSK(P)
Receiver output pulse skew,|tPHL – tPLH|
tPZL, tPZH,
tPLZ, tPHZ
Receiver enable/disable time
See Figure 6
FUNCTION TABLE
DRIVER
DE
D
L or OPEN
X
Z
Driver Disabled (Passive)
L
H
Driver Active
H or Open
Z
Driver Passive
VID
R
X
Z
Receiver Disabled
VID < –0.9 V
L
Active Bit Received
–0.9 V < VID < –0.5
?
Indeterminate bus
–0.5 V < VID < 0.5 V
H
Passive Bit Received
0.5 V < VID < 0.9 V
?
Indeterminate bus
0.9 V < VID
L
Active Bit Received
Open, Short, Idle
H
Failsafe Condition
H
RECEIVER
RE
H or OPEN
L
4
VOD
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SN65HVD96
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SLLSE35 – JUNE 2010
DEVICE INFORMATION
DE Input
D and /RE Input
Vcc
Vcc
4.3 k ?
4.3 k ?
Input
Input
6V
6V
140 k?
A and B Outputs
A and B Input
Vcc
Vcc / 2
39 k?
3k ?
Input
36 k ?
B
A
40 V
40 V
3.3 V
40 V
R Output
15 ?
Output
6V
Figure 1. Equivalent Input and Output Schematic Diagrams
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5
SN65HVD96
SLLSE35 – JUNE 2010
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APPLICATION INFORMATION
Sympol™ States
Using Sympol to Achieve Immunity to Crossed Bus Wire
Many applications which use RS-422 or RS-485 are wired on-site by third-party installers. This opens the door to
the possibility of miss-wiring, especially for far-flung networks with many stations (or nodes). Neither RS-422 nor
RS-485 allows correct communications when the bus wires (typically a twisted-pair) are swapped.
The existing solutions for this case require active intervention, either by the installer or maintenance technician,
or by an automated controller. Sympol offers a way to replace RS-422 or RS-485 networks with communication
over the same bus lines. Due to the innovative nature of Sympol signalling levels, a Sympol network is immune
to communication errors caused by crossed bus wires.
Signaling levels are similar to RS-422 and RS-485, so signalling rates, cable lengths, and noise immunity will be
comparable.
Sympol is NOT interoperable with RS-422 or RS-485; that is, designers may not mix Sympol nodes with existing
RS-485 nodes.
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100kbps, 50% duty-cycle, transition times less than 6 ns for all figures.
Figure 2. Measurement of Driver Differential Output Voltage With Common-Mode Load
6
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SN65HVD96
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SLLSE35 – JUNE 2010
PARAMETER MEASUREMENT INFORMATION (continued)
3V
D
50 %
0V
B
D
Generator
RL
CL
tpAP
VOD
tpPA
90 %
A
90 %
VOD
DE
50 %
10 %
VCC
trise
tfall
Figure 3. Measurements of Driver Differential Output Rise and Fall Times and Propagation delays
3V
DE
B
GND
D
50%
RL
CL
VOD
0V
tpZA
tpAZ
A
Signal
Generator
VOD
DE
50%
Figure 4. Measurements of Driver Enable and Disable Times With Active Output
1.5 V
700 mV
V
ID
A/B
0V
R
V ID
tpLH
B/A
RE
tpHL
CL
V OH
90%
R
1.5 V
10%
tr
V OL
tf
Figure 5. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
3V
3 .3 V
50%
RE
A/B
1 kW
R
0V
t pZL
t pLZ
3.3V
V ID
B/A
RE
C L = 15 pF
(includes probe and
jig capacitance)
Signal
Generator
R
|V ID|=1.5V
50%
VOL +0.5V
t pZH
R
|V ID|=0V
VOH -0.5V
50%
t pHZ
VOL
VOH
0V
Figure 6. Measurement of Receiver Enable Times With Driver Disabled
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7
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
SN65HVD96D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
SN65HVD96DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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