SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 Two Channel SATA 3-Gbps Redriver FEATURES 1 • • • • • • • • Data Rates up to 3.0 Gbps SATA Gen 2.6, eSATA Compliant SATA Hot-Plug Capable Supports Common-Mode Biasing for OOB Signaling with Fast Turn-On Channel Selectable Pre-Emphasis Fixed Receiver Equalization Integrated Termination Low Power • • – <200 mW Typ – <5 mW (in sleep mode) Excellent Jitter and Loss Compensation Capability to Over 20 Inch FR4 Trace 20-Pin 4 × 4 QFN Package APPLICATIONS • Notebooks, Desktops, Docking Stations, Servers, Workstations DESCRIPTION The SN75LVCP412 is a dual channel, single lane SATA redriver and signal conditioner supporting data rates up to 3.0 Gbps. The device complies with SATA specification revision 2.6 and eSATA requirements. The SN75LVCP412 operates from a single 3.3-V supply and has 100-Ω line termination with self-biasing feature making the device suitable for AC coupling. The inputs incorporate an OOB detector, which automatically squelches the output while maintaining a stable output common-mode voltage compliant to SATA link. The device is also designed to handle SSC transmission per the SATA specification. The SN75LVCP412 handles interconnect losses at both its input and output. The built-in transmitter pre-emphasis feature is capable of applying 0 dB or 2.5 dB of relative amplification at higher frequencies to counter the expected interconnect loss. On the receive side the device applies a fixed equalization of 7 dB to boost input frequencies near 1.5 GHz. Collectively, the input equalization and output pre-emphasis features of the device work to fully restore SATA signal integrity over extended cable and backplane pathways. The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal. (1) Requires use of AC coupling capacitors at differential inputs and outputs. ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75LVCP412RTJR LVCP412 20-Pin RTJ Reel (large) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION PC Motherboard ICH HDD R R = SN75LVCP412 eSATA connector SATA Cable (2m) In Notebook and Desktop Motherboard HDD Dock Connector R = SN75LVCP412 ICH Notebook R eSATA connector SATA Cable (2m) Dock In Notebook Dock 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 GND [3, 13, 17-19] VCMRX = 1.6 V RT TX_OP [15] RT Driver Equalizer RX_0P [1] TX_ON [14] OOB Detect RX_0N [2] VCMRX SN75LVCP412 RT RX_1N [12] Driver Equalizer TX_1N [4] RX_1P [11] OOB Detect TX_1P [5] RT CTRL D1 [8] EN [7] D0 [9] VCC [6, 10, 16, 20] Figure 1. Data Flow Block Diagram Table 1. Control Logic EN D0 D1 FUNCTION 0 X X Low power mode 1 0 0 Normal SATA output (default state); CH 0 and CH 1 → 0 dB 1 1 0 CH 0 → 2.5 dB pre-emphasis; CH 1 → 0 dB 1 0 1 CH 1→ 2.5 dB pre-emphasis; CH 0 → 0 dB 1 1 1 CH 0 and CH 1 → 2.5 dB pre-emphasis Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 3 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com PIN ASSIGNMENT TOP VIEW 13 12 11 RX_1N RX_1P RX_1N RX_1P 11 10 VCC 7 EN GND 17 9 D0 8 D1 GND 18 9 D0 10 VCC 8 D1 GND 19 7 EN VCC 20 6 VCC LVCP412RTJ 1 2 3 4 5 TX_1P 14 12 RX_0P 15 GND VCC 16 TX_0N GND 17 TX_0P GND 18 13 VCC 16 LVCP412RTJ Thermal Pad should be soldered to PCB GND plane for efficient thermal performance 14 6 VCC VCC 20 GND 19 15 TX_1N 5 GND TX_1P 4 GND TX_1N 3 TX_0N GND 2 RX_0N RX_0N 1 TX_0P RX_0P BOTTOM VIEW TERMINAL FUNCTIONS (1) (2) 4 PIN NAME DESCRIPTION PIN NAME DESCRIPTION 1 RX_0P Input 0, non-inverting 11 RX_1P Input 1, non-inverting 2 RX_0N Input 0, inverting 12 RX_1N Input 1, inverting 3 GND Ground 13 GND 4 TX_1N Output 1, inverting 14 TX_0N Ground Output 0, inverting 5 TX_1P Output 1, non-inverting 15 TX_0P Output 0, non-inverting 6 VCC Power 16 VCC Power 7 EN (1) Enable 17 GND Ground 8 D1 (2) Pre-emphasis_1 18 GND Ground 9 D0 (2) Pre-emphasis _0 19 GND Ground 10 VCC Power 20 VCC Power EN tied to VCC via internal PU resistor D0 and D1 are tied to GND via internal PD resistor Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 TYPICAL DEVICE IMPLEMENTATION 3.3 V 18 17 16 RX_0P TX_0P 2 RX_0N TX_0N 3 TX_1N RX_1N 12 5 TX_1P RX_1P 11 10 nF 7 9 8 10 10 nF 4.7K D0 4.7K D1 EN GPIO 10 nF 10 nF 4 6 10 nF 14 13 LVCP412 RTJ 10 nF 15 eSATA Connector 1 0.01 mF SATA Host 10 nF 19 0.1 mF 1 mF 20 10 nF Note: 1) Place supply caps close to device pin 2) EN can be left open or tied to supply when no external control is implemented 3) Output pre-emphasis (D1, D0) is shown enabled. Setting will depend on device placement relative to eSATA connector DETAILED DESCRIPTION INPUT EQUALIZATION Each differential input of the SN75LVCP412 has 7 dB of fixed equalization in its front stage. The equalization amplifies high frequency signals to correct for loss from the transmission channel. The input equalizer is designed to recover a signal even when no eye is present at the receiver and effectively supports FR4 trace at the input anywhere from <4 inches to 20 inches or <10 cm to >50 cm. OUTPUT PRE-EMPHASIS The SN75LVCP412 provides single step pre-emphasis from 0 dB to 2.5 dB at each of its differential outputs. Pre-emphasis is controlled independently for each channel and is set by the control pins D0 and D1 as shown in Table 1. The pre-emphasis duration is 0.4 UI or 133 ps (typ) at SATA 3-Gbps speed. LOW POWER MODE Two low power modes are supported by the SN75LVCP412: • Sleep Mode (triggered by EN pin, EN = 0V) – Low power mode is controlled by enable (EN) pin. In its default state this pin is internally pulled high. Pulling this pin LOW will put the device in sleep mode within 2µs (max). In this mode all active components of the device are driven to their quiescent level and differential outputs are driven to Hi-Z (open). Max power dissipation in this mode is 5 mW. Exiting from this mode to normal operation requires a maximum latency of 20 µs. • Auto Low Power Mode (triggered when a given channel is in electrical idle state; EN = VCC) – The device enters and exits low power mode by actively monitoring input signal (VIDp-p) level on each of its channel independently. When input signal on either or both channel is in the electrical idle state, i.e. VIDp-p <50 mV and stays in this state for ≥3 µS the associated channel(s) enters into the low power state. In this Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 5 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com state, output of the associated channel(s) is driven to VCM and device selectively shuts off some circuitry to lower power by up to 20% of its normal operating power. Exit time from auto low power mode is less than 50 ns. – As an example, if under normal operating conditions device is consuming typical power of 200 mW. When device enters this mode, i.e. condition for auto-low power mode is met, power consumption can drop down to 160 mW. The device enters normal operation within 50 ns of signal activity detection. OUT-OF-BAND (OOB) SUPPORT The squelch detector circuit within the device enables full detection of OOB signaling as specified in SATA specification 2.6. Differential signal amplitude at the receiver input of 50 mVp-p or less is not detected as an activity and hence is not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity and therefore passed to the output indicating activity. Squelch circuit on/off time is 5 ns max. While in squelch mode outputs are held to VCM. DEVICE POWER The SN75LVCL412 is designed to operate from a single 3.3-V supply. Always practice proper power supply sequencing procedures. Apply VCC first before any input signals are applied to the device. The power down sequence is in reverse order. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range (2) VCC Voltage range Differential I/O V V Human body model (3) ±8000 V Charged-device model (4) ±1000 V ±200 V Machine model (2) (3) (4) (5) V –0.5 to 4 (5) Continuous power dissipation (1) UNIT –0.5 to VCC + 0.5 Control I/O Electrostatic discharge VALUE –0.5 to 6 See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. DISSIPATION RATINGS PACKAGE 20-pin QFN (RTJ) (1) PCB JEDEC STANDARD TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C Low-K 1176 mW 11.76 mW/°C 470 mW High-K 2631 mW 26.3 mW/°C 1052 mW TA = 85°C POWER RATING This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX (1) UNIT RθJB Junction-to-board thermal resistance 10 °C/W RθJC Junction-to-case thermal resistance 60 °C/W RθJP Junction-to-pad thermal resistance 15.2 °C/W (1) 6 The maximum rating is simulated under 3.6-V VCC. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 THERMAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN PD Device power dissipation, active mode EN = 3.3 V, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.6 V PSD Device power dissipation, sleep mode EN = 0 V, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.6 V TYP MAX (1) UNIT 300 mW 5 mW RECOMMENDED OPERATING CONDITIONS with typical values measured at VCC = 3.3 V, TA = 25°C; all temperature limits are assured by design PARAMETER VCC Supply voltage CCOUPLING Coupling capacitor TA Operating free-air temperature CONDITIONS MIN TYP MAX 3 3.3 3.6 12 0 UNITS V nF 85 °C ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX 55 70 UNITS DEVICE PARAMETERS ICC Supply current, active mode EN = 3.3 V, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.3 V ICCSLEEP Shutdown current, sleep mode EN = 0V 1 Maximum data rate 320 mA mA 3.0 Gbps 400 ps µs tPDelay Propagation delay Measured using K28.5 pattern, See Figure 2 tENB Device enable time ENB = L → H 20 tDIS Device disable time ENB = H → L 2 VOOB Input OOB threshold See Figure 3 tOOB1 OOB mode enter See Figure 3 3 5 ns tOOB2 OOB mode exit See Figure 3 3 5 ns 50 150 µs mVp-p CONTROL LOGIC VIH High-level input voltage 1.4 V VIL Low-level input voltage VINHYS Input hysteresis IIH High-level input current 10 µA IIL Low-level input current 10 µA 115 Ω 0.5 115 V mV RECEIVER AC/DC ZDiffRX Differential input impedance 85 ZSERX Single-ended input impedance 40 VCMRX Common-mode voltage RLDiffRX Differential mode return loss RLCMRX Common-mode return loss 100 Ω 1.6 f = 150 MHz–300 MHz 18 f = 300 MHz–600 MHz 14 f = 600 MHz–1.2 GHz 10 f = 1.2 GHz–2.4 GHz 8 f = 2.4 GHz–3.0 GHz 3 f = 150 MHz–300 MHz 5 f = 300 MHz–600 MHz 5 f = 600 MHz–1.2 GHz 2 f = 1.2 GHz–2.4 GHz 1 f = 2.4 GHz–3.0 GHz 1 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 V dB dB 7 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER CONDITIONS MIN VDiffRX Differential input voltage PP f = 150 MHz–300 MHz 200 IBRX Impedance balance f = 150 MHz–300 MHz 30 f = 300 MHz–600 MHz 30 f = 600 MHz–1.2 GHz 20 f = 1.2 GHz–2.4 GHz 10 f = 2.4 GHz–3.0 GHz TYP MAX UNITS 2000 mV/ppd dB 4 T20-80RX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal TskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising/falling edge, and the single-ended mid-point of the RX– signal falling/rising edge 67 136 ps 50 ps 115 Ω TRANSMITTER AC/DC ZDiffTX Pair differential Impedance 85 ZSETX Single-ended input impedance 40 RLDiffTX RLCMTX Output pre-emphasis At 1.5 GHz when enabled Differential mode return loss f = 150 MHz–300 MHz 14 f = 300 MHz–600 MHz 8 f = 600 MHz–1.2 GHz 6 f = 1.2 GHz–2.4 GHz 6 f = 2.4 GHz–3.0 GHz 3 f = 150 MHz–300 MHz 5 f = 300 MHz–600 MHz 5 f = 600 MHz–1.2 GHz 2 f = 1.2 GHz–2.4 GHz 1 Common-mode return loss f = 2.4 GHz–3.0 GHz IBTX Impedance balance Ω 2.5 dB dB dB 1 f = 150 MHz–300 MHz 30 f = 300 MHz–600 MHz 20 f = 600 MHz–1.2 GHz 10 f = 1.2 GHz–2.4 GHz 10 f = 2.4 GHz–3.0 GHz dB 4 DiffVppTX Differential output voltage PP f = 1.5 GHz, D0/D1 = 0 400 525 600 mV/ppd DiffVppTX_PE Differential output voltage PP f = 1.5 GHz, D0/D1 = 1 600 700 800 mV/ppd tDE Pre-emphasis width See Figure 4 VCMTX Common-mode voltage T20-80TX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal, D1, D0 = 0 V TskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX– signal falling/rising edge, D1, D0 = VCC TJTX Total jitter (1) UI = 333 ps, +K28.5 control character DJTX Deterministic jitter (1) UI = 333 ps, +K28.5 control character RJTX Random jitter (1) UI = 333 ps, +K28.7 control character 2.0 (1) 8 0.4 UI 1.97 67 100 V 136 ps 20 ps 0.2 0.3 Uip-p 0.13 0.2 Uip-p 2.15 ps/rms TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. TJ measurement is at the SATA connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown in Figure 2. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 SATA compliance measurement point LVCP412 CH 0 Host 6" FR4 10" FR4 Device CH 1 Lossless Signal Source SATA compliance measurement point Lossless Signal Source Jitter Measurement Setup Figure 2. Jitter Measurement Test Condition IN tPDelay tPDelay OUT Figure 3. Propagation Delay Timing Diagram IN+ Vcm 50 mV INtOOB2 tOOB1 OUT+ Vcm OUT- Figure 4. OOB Enter and Exit Timing Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 9 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com 1-bit tDE 2.5 dB 1 to N bits 1-bit 1 to N bits 0dB Vcm DiffVPPTX DiffVPPTX_PE 0dB tDE 2.5 dB Figure 5. TX Differential Output with 2.5 dB Pre-Emphasis Step BENCH TEST DATA Differential Output Voltage – DiffVppTX, 2 inches from Device Pin, VCC = 3.3 V, TA = 25°C, Pattern = K28.5, Bit Rate = 3 Gbps PARAMETER DiffVppTX DiffVppTXDE TEST CONDITIONS VCC = 3.3 V, TA = 25°C, Pattern = K28.5, Bit rate = 3 Gbps CHANNEL INPUT VID DO/D1 MIN MEAN MAXIMUM CH0 700 mV 0 524.87mV 524.87mV 525.72mV CH1 700 mV 0 515.68mV 516.72mV 518.85mV CH0 700 mV 1 665.07mV 666.48mV 668.07mV CH1 700 mV 1 656.32mV 658.34mV 660.40mV EYE DIAGRAM Eye Pattern Measurement Setup X (inch) Y (inch) Data Generator 12 nF CH0/1 LVCP412 12 nF Scope Test Condition • • • • • • 10 Vcc = 3.3 V Temp = 25°C Rx input voltage = 700 mVp-p Input pattern K28.5+ @3 Gbps D1/D0/ENB = Vcc Trace Width = 4 mil on PCB Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 Figure 6. Eye Pattern Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 11 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com X=5.7”, Y =5.7” (Eye Height/Width) Eye Height Eye Width Figure 7. Eye Pattern 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 SN75LVCP412 www.ti.com............................................................................................................................................................................................ SLLS912 – NOVEMBER 2008 Figure 8. Eye Pattern Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 13 SN75LVCP412 SLLS912 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com Figure 9. Eye Pattern 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP412 PACKAGE OPTION ADDENDUM www.ti.com 1-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN75LVCP412RTJR ACTIVE QFN RTJ 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LVCP412RTJT ACTIVE QFN RTJ 20 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75LVCP412RTJR QFN RTJ 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 SN75LVCP412RTJT QFN RTJ 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVCP412RTJR QFN RTJ 20 3000 346.0 346.0 29.0 SN75LVCP412RTJT QFN RTJ 20 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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