STK15C88 32K x 8 AutoStore™ nvSRAM High Performance CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • Nonvolatile Storage Without Battery Problems • Directly Replaces 32K x 8 static RAM, Battery Backed RAM or EEPROM • 25ns, 35ns and 45ns Access Times • Store to EEPROM Initiated by Software or AutoStore™ on Power Down • Recall to SRAM by Software or Power Restore • 15mA ICC at 200ns Cycle Time • Unlimited Read, Write and Recall Cycles • 1,000,000 Store Cycles to EEPROM • 100 Year Data Retention Over Full Industrial Temperature Range • Commercial and Industrial Temp. Ranges • 28 Pin 600 or 300 mil PDIP and 350 mil SOIC The Simtek STK15C88 is a fast static RAM with a nonvolatile, electrically-erasable PROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. PIN CONFIGURATIONS BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE STATIC RAM ARRAY 256 x 1024 RECALL STORE/ RECALL CONTROL POWER CONTROL 28 V CC 2 3 27 26 W A 13 A6 A5 4 5 25 24 A8 A9 A4 A3 6 7 23 22 A 11 G A2 A1 8 9 21 20 A 10 E A0 DQ 0 10 11 19 18 DQ 7 DQ 6 DQ 1 DQ 2 12 13 17 16 DQ 5 DQ 4 V SS 14 15 DQ 3 28 - 300 PDIP 28 - 600 PDIP 28 - 350 SOIC 28 - 300 SOIC A0 A13 COLUMN I/O COLUMN DEC PIN NAMES A0 A1 A2 A3 A4 A5 A10 G E W August 1998 1 A 12 A7 VCC SOFTWARE DETECT INPUT BUFFERS A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER EEPROM ARRAY 256 x 1024 A 14 5-35 A0 - A14 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+5V) VSS Ground STK15C88 ABSOLUTE MAXIMUM RATINGSa Note a: Voltage on input relative to VSS . . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Stresses greater than those listed under “Absolute Maxmum Ratings” may cause permanent damage to the device. This a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (Vcc = 5.0V ± 10%) DC CHARACTERISTICS SYMBOL COMMERCIAL INDUSTRIAL MIN MIN PARAMETER UNITS MAX NOTES MAX ICC1b Average Current 95 75 65 100 80 70 mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns ICC2c Average Current During STORE 6 7 mA All inputs Don’t Care ICC3b Average VCC Current at tAVAV = 200ns 15 15 mA W ≥ (V CC – 0.2V) All others cycling, CMOS levels ICC4c Average Current During AutoStore™ Cycle 4 4 mA ISB1d Average Current (Standby, Cycling TTL Input Levels) 29 24 20 30 25 21 mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH ISB2d Standby Current (Standby, Stable CMOS Input Levels) 3 3 mA E ≥ (V CC – 0.2V) All others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 µA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 µA VCC = max VIN = VSS to VCC, E or G ≥ VIH 2.2 VCC + .5 V All inputs VSS – .5 0.8 V All inputs V IOUT = – 4mA 0.4 V IOUT = 8mA 85 °C SRAM READ CYCLES #1 & SRAM2.2READ VIH Input Logic “1” Voltage VCC + .5 VIL Input Logic “0” Voltage VOH Output Logic “1” Voltage VOL Output Logic “0” Voltage TA Operating Temperature VSS – .5 0.8 2.4 2.4 0.4 0 70 -40 All inputs Don’t Care Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS 5.0V Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL PARAMETER (TA = 25°C, f = 1.0MHz) MAX UNITS CONDITIONS CIN Input capacitance 5 pF ∆V = 0 to 3V COUT Output capacitance 7 pF ∆V = 0 to 3V Note e: These parameters are guaranteed but not tested. August 1998 5-36 480 Ohms Output 255 Ohms Figure 1: AC Output Loading 30pF INCLUDING SCOPE AND FIXTURE STK15C88 (Vcc = 5.0V ± 10%) SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK15C88-25 STK15C88-35 STK15C88-45 PARAMETER #1, #2 UNITS Alt. MIN MAX MIN MAX MIN MAX 1 tELQV tACS Chip Enable Access Time 2 tAVAVf tRC Read Cycle Time 3 tAVQVg tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 15 20 ns 5 tAXQXg tOH Output Hold After Address Change 3 3 3 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 5 ns 7 tEHQZh tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive 10 tELICCHe tPA Chip Enable to Power Active 11 tEHICCLd, e tPS Chip Disable to Power Standby 25 25 35 45 35 45 10 0 13 0 10 0 13 0 0 25 35 2 tAVAV ADDRESS 3 tAVQV DQ(Data Out) DATA VALID SRAM READ CYCLE #2 (E Controlled)f 2 tAVAV ADDRESS 1 11 tELQV E tEHICCL 6 tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQV tGLQX DQ(Data Out) DATA VALID 10 tELICCH ICC August 1998 ACTIVE STANDBY 5-37 ns ns 45 SRAM READ CYCLE #1 (Address Controlled)f, g ns ns 15 Note f: W must be high during SRAM read cycles and low during SRAM write cycles. Note g: I/O state assumes E, G, < VIL and W > VIH; device is continuously selected Note h: Measured + 200mV from steady state output voltage 5 tAXQX ns 15 0 ns ns STK15C88 (Vcc = 5.0V ± 10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS STK15C88-25 NO. STK15C88-35 STK15C88-45 PARAMETER UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active After End of Write Note i: Note j: 10 5 13 5 5 If W is low when E goes low the outputs remain in the high impedance state. E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W CONTROLLEDj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 16 tDVWH DATA IN tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDENCE PREVIOUS DATA SRAM WRITE CYCLE #2: E CONTROLLEDj 12 tAVAV ADDRESS 18 19 14 tAVEL tEHAX tELEH E 17 tAVEH 13 W tWLEH 15 16 tDVEH DATA IN DATA OUT August 1998 tEHDX DATA VALID HIGH IMPEDENCE 5-38 15 ns ns STK15C88 (Vcc = 5.0V ± 10%) AutoStore™ / POWER-UP RECALL SYMBOLS STK15C88 NO. PARAMETER UNITS NOTES Standard MIN MAX 22 tRESTORE Power Up RECALL Duration 550 µs k 23 tSTORE STORE Cycle Duration 10 ms g 24 tDELAY Time allowed to Complete SRAM Cycle µs g 25 VSWITCH Low Voltage Trigger Level 26 VRESET Low Voltage Reset Level 1 4.0 4.5 V 3.9 V Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStore™ / POWER UP RECALL V CC 5V 25 VSWITCH 26 VRESET AUTOSTORE TM 23 t STORE POWER UP RECALL 22 t RESTORE 24 t DELAY W DQ (Data Out) POWER-UP RECALL August 1998 BROWN OUT NO STORE DUE TO NO SRAM WRITES BROWN OUT AutoStore™ BROWN OUT AutoStore™ NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN ABOVE VSWITCH 5-39 STK15C88 SOFTWARE MODE SELECTION E L L W A13 - A0 (hex) MODE I/O NOTES H 0E38 31C7 03E0 3C1F 303F 0FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output data Output data Output data Output data Output data Output high Z l,m H 0E38 31C7 03E0 3C1F 303F 0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM NonvolatileRECALL Output data Output data Output data Output data Output data Output high Z l,m Note l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK15C88, only the lower 14 are used to control software modes. (VCC = 5.0V ± 10%) SOFTWARE CYCLES #1 & #2n,o SYMBOLS NO. STK15C88-25 STK15C88-35 STK15C88-45 MIN MIN MIN PARAMETER UNITS #1 MAX MAX MAX 27 tAVAV STORE/RECALL initiation cycle time 28 tELQZg,n End of Sequence to Outputs Inactive 29 tAVELn Address Set-up Time 0 0 0 ns 30 tELEHn Clock Pulse Width 20 25 30 ns 31 tELAXg,n Address Hold Time 20 32 tRECALL Recall Duration 25 35 650 45 650 20 20 ns 650 20 20 ns ns 20 µs Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the SOFTWARE MODE SELECTION Table - (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE CYCLE: E CONTROLLED 27 t AVAV 27 t AVAV ADDRESS #1 ADDRESS 29 t AVEL ADDRESS #6 30 t ELEH E 31 t ELAX 23 32 t STORE t RECALL t ELQZ28 DQ(Data Out) August 1998 DATA VALID DATA VALID 5-40 HIGH IMPEDANCE STK15C88 DEVICE OPERATION The STK15C88 is a versatile memory chip that provides several modes of operation. The STK15C88 can operate as a standard 32K x 8 SRAM. It has a 32K x 8 EEPROM shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode. NOISE CONSIDERATIONS Note that the STK15C88 is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1µF connected between DUT VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK15C88 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. August 1998 SOFTWARE NONVOLATILE STORE The STK15C88 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence is clocked with E controlled reads. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 5-41 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle STK15C88 Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The STK15C88 offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCC < VSWITCH all Software STORE operations will be inhibited. AutoStoreTM OPERATION LOW AVERAGE ACTIVE POWER The STK15C88 uses the intrinsic system capacitance to perform an automatic store on power down. As long as the system power supply takes at least tSTORE to decay from VSWITCH down to 3.6V the STK15C88 will safely and automatically store the SRAM data in EEPROM on power-down. In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. POWER UP RECALL During power up, or after any low power condition (VCC < VRESET) an internal recall request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. HARDWARE PROTECT The STK15C88 draws significantly less current when it is cycled at times longer than 30ns. Figure 2, below, shows the relationship between ICC and READ cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK15C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READ’s to WRITE’s; 5) the operating temperature; 6) the VCC level and; 7) I/O loading. 100 Average Active Current (mA) Average Active Current (mA) 100 80 60 40 20 TTL 80 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 50 200 Cycle Time (ns) 150 200 Cycle Time (ns) Fig 2: Icc (max) Reads August 1998 100 Fig 3: Icc (Max) Writes 5-42 STK15C88 ORDERING INFORMATION STK15C88 - W 25 I Temperature Range blank = Commercial (0 to 70 degrees C) I = Industrial (–40 to 85 degrees C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Package W = Plastic 28 pin 600 mil DIP P = Plastic 28 pin 300 mil DIP S = Plastic 28 pin 350 mil SOIC N = Plastic 28 pin 300 mil SOIC August 1998 5-43