STL60NH3LL N-channel 30 V - 0.0065 Ω - 30 A - PowerFLAT™ (6x5) ultra low gate charge STripFET™ Power MOSFET Features Type VDSS RDS(on) (max) ID STL60NH3LL 30V <0.0085Ω 16A ■ Improved die-to-footprint ratio ■ Very low profile package (1mm max) ■ Very low thermal resistance ■ Very low gate charge ■ Low threshold device PowerFLAT™(6x5) Application ■ Switching applications Figure 1. Internal schematic diagram Description This application specific Power MOSFET is the latest generation of STMicroelectronics unique “STripFET™” technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance. Table 1. Device summary Order code Marking Package Packaging STL60NH3LL L60NH3LL PowerFLAT™ (6 x 5) Tape & reel December 2007 Rev 6 1/13 www.st.com 13 Contents STL60NH3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 9 STL60NH3LL 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 30 V ± 16 V Drain current (continuous) at TC = 25°C 30 A ID (1) Drain current (continuous) at TC = 100°C 30 A ID(2) Drain current (continuous) at TC = 25°C 16 A VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ID (1) (3) Drain current (pulsed) 64 A PTOT(1) Total dissipation at TC = 25°C 60 W PTOT(2) Total dissipation at TC = 25°C 4 W 0.03 W/°C -55 to 150 °C Value Unit 2.08 °C/W 31.3 °C/W Value Unit IDM Derating factor Tj Tstg Operating junction temperature Storage temperature 1. The value is rated according Rthj-C and is limited by wire bonding. 2. This value is according Rthj-pcb 3. Pulse width limited by safe operating area Table 3. Thermal resistance Symbol Rthj-case Parameter Thermal resistance junction-case (drain) Max Rthj-pcb (1) Thermal resistance junction-pcb Max 1. When mounted on FR-4 board of Table 4. Symbol 1inch2, 2 oz. Cu., t<10sec Avalanche data Parameter IAV Not-repetitive avalanche current 7.5 A EAS Single pulse avalanche energy (starting Tj=25°C, Id=Iav) 150 mJ 3/13 Electrical characteristics 2 STL60NH3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. Symbol Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating, VDS = Max rating,@125°C IGSS Gate body leakage current (VDS = 0) VDS = ± 16 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 8 A VGS= 4.5 V, ID= 8 A V(BR)DSS Table 6. Symbol 4/13 On/off states Min. Typ. Max. 30 Unit V 1 10 µA µA ±100 nA 1 V 0.0065 0.0085 0.0075 0.0105 Ω Ω Dynamic Parameter Test conditions Min. Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS=25 V, f = 1 MHz, VGS=0 1810 565 41 Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 15 V, ID = 16 A, VGS = 4.5 V (see Figure 16) 18 4.8 5.3 24 nC nC nC RG Gate input resistance f=1 MHz gate DC bias = 0 test signal level = 20 mV open drain 1.5 3 Ω 0.5 Typ. Max. Unit pF pF pF STL60NH3LL Electrical characteristics Table 7. Symbol Switching times Parameter Test conditions Min. Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD = 15 V, ID = 8 A RG= 4.7 Ω, VGS= 10 V, (see Figure 15) 8 65 ns ns td(off) tf Turn-off delay time Fall time VDD = 15 V, ID = 8 A RG= 4.7 Ω, VGS= 10 V, (see Figure 15) 30 20 ns ns Table 8. Symbol ISD ISDM VSD (1) trr Qrr IRRM Source drain diode Parameter Test conditions Min. Typ. Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 16 A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 16 V, di/dt = 100 A/µs VDD = 20 V, Tj = 25°C (see Figure 17) 22 32 1.9 Max Unit 16 64 A A 1.3 V ns nC A 1. Pulsed: Pulse duration = 300µs, duty cycle 1.5% 5/13 Electrical characteristics STL60NH3LL 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BVDSS vs. temperature Figure 7. Static drain-source on resistance 6/13 STL60NH3LL Figure 8. Electrical characteristics Gate charge vs. gate-source voltage Figure 9. Figure 10. Normalized gate threshold voltage vs. temperature Capacitance variations Figure 11. Normalized on resistance vs. temperature Figure 12. Source-drain diode forward characteristics 7/13 Electrical characteristics STL60NH3LL Figure 13. Allowable Iav vs Time in Avalanche Figure 14. Allowable Iav vs Time in Avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche 8/13 STL60NH3LL 3 Test circuit Test circuit Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform 9/13 Package mechanical data 4 STL60NH3LL Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/13 STL60NH3LL Package mechanical data PowerFLAT™ (6x5) MECHANICAL DATA mm. inch DIM. A MIN. TYP MAX. MIN. 0.80 0.031 0.83 0.93 A1 0.02 0.05 A3 0.20 b 0.35 0.40 TYP. 0.032 0.036 0.0007 0.0019 0.007 0.47 0.013 0.015 D 5.00 0.196 D1 4.75 0.187 D2 4.15 E 4.20 4.25 5.75 3.48 3.53 E4 2.58 2.63 2.68 0.135 1.27 0.70 0.80 0.167 0.226 3.43 e 0.165 0.018 0.236 E2 L 0.163 6.00 E1 MAX. 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 11/13 Revision history 5 STL60NH3LL Revision history Table 9. 12/13 Document revision history Date Revision Changes 10-Jan-2006 1 First release 14-Apr-2006 2 New footprint 03-Jul-2006 3 New Ecopack label 01-Aug-2006 4 Modified Figure 2. and Figure 3. 05-Sep-2006 5 New template, no content change 11-Dec-2007 6 Added Table 4: Avalanche data STL60NH3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. 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