TOSHIBA T6C03

T6C03
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6C03
COLUMN AND ROW DRIVER FOR A DOT MATRIX LCD
The T6C03 is a 160−channel−output column and row driver for
an STN dot matrix LCD.
The T6C03 features a 42−V LCD drive voltage and an 8−MHz
maximum operating frequency. The T6C03 is able to drive LCD
panels with a duty ratio of up to 1 / 480.
Features
l Display duty application
: to 1 / 480
l LCD drive signal
: 160
l Data transfer
: Column: 4 / 8−bit bidirectional
Row: Single / Dual bidirectional
l Operating frequency
: 8 MHz (VDD = 5 V ± 10%)
l LCD drive voltage
: 14 to 42 V
l Power supply voltage
: 2.7 to 5.5 V
l Operating temperature
: −20 to 75°C
l LCD drive output resistance : 1.3 kΩ (max) (20 V, 1 / 13 bias)
l Display−off function
: When / DSPOF is L, all LCD drive outputs (O1 to O160) remain at the V5 level.
l Low power consumption
: Cascade connection and auto enable transfer functions are available.
l EI / LP input
: EI / LP input enables LSI operation.
Connect EIO1 / 2 from the 1st LSI to L.
000707EBE1
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· The information contained herein is subject to change without notice.
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T6C03
Block Diagram
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T6C03
Pin Assignment
Note: The above diagram shows the pin configuration of the LSI Chip, not that of the tape carrier package.
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T6C03
Pin Functions
Pin Name
I/O
O1 to O160
Output
EIO1, EIO2
I/O
Functions
Output for LCD drive signal
V0 to V5
(Column mode)
Input / output for enable signal
DIR selects In or Out.
Connect EIO (IN) of 1st LSI to L.
For a cascade connection, connect EIO (OUT) to EIO (IN) of next LSI.
(Row mode)
Input / output for shift data
DIR = L : EIO1 is output, EIO2 is input
DIR = H : EIO1 is input, EIO2 is output
(Column mode)
Input for data signal
DI1 to DI8
Input
DIR
Input
(Direction)
Input for data flow direction select
/ DSPOF
Input
(Display off)
/ DSPOF = L : Display−off mode, (O1 to O160) remain at the V5 level
/ DSPOF = H : Display−on mode, (O1 to O160) are operational.
DF
Input
(Data format)
Input for data bit select
LP
Input
Level
(Row mode)
DI1 to DI7: Fix to H or L, DI8: when DF = H, use as DIN
VDD to VSS
(Latch pulse)
Display data is latched on falling edges of LP.
When EIO (IN) = L, SCP · LP = H enables the 1st LSI.
(Row mode)
Input for shift clock pulse
FR
Input
(Frame)
Input for frame signal
(Column mode)
Input for shift clock pulse
SCP
Input
TEST
Input
(TEST)
Fix to L
S/C
Input
Input for mode select: H = Column mode, L = Row mode
(Row mode)
Fix to H or L
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T6C03
Pin Name
I/O
Functions
VDD
―
Power supply for internal logic (+5.0 V)
VSS
―
Power supply for internal logic (0 V)
V5L · R
―
Power supply for LCD drive circuit
V3 / 4L · R
―
Power supply for LCD drive circuit
V2 / 1L · R
―
Power supply for LCD drive circuit
V0L · R
―
Power supply for LCD drive circuit
VCCL · R,
VSSL · R
―
Power supply for LCD drive circuit
Level
―
Relation Between FR, Data Input and Output Level
FR
Data Input
/ Dspof
Output Level
(Column Mode)
Output Level
(Row Mode)
L
L
H
V3
V4
L
H
H
V5
V0
H
L
H
V2
V1
H
H
H
V0
V5
(Note)
(Note)
L
V5
V5
Note: Don’t Care
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T6C03
Data Input Format
Column Mode
DIR
DF
BIT Mode
H
Enable Pin
EIO1
EIO2
IN
OUT
L
OUT
IN
H
IN
OUT
OUT
IN
L
H
4−BIT
8−BIT
L
(Note 1)
Input Data Line and Output Buffers
DI3
DI4
DI5
DI6
DI1
DI2
DI7
DI8
L
O160
O159
O158
O157
―
―
―
―
F
O4
O3
O2
O1
―
―
―
―
L
O1
O2
O3
O4
―
―
―
―
F
O157
O158
O159
O160
―
―
―
―
L
O160
O159
O158
O157
O156
O155
O154
O153
F
O8
O7
O6
O5
O4
O3
O2
O1
L
O1
O2
O3
O4
O5
O6
O7
O8
F
O153
O154
O155
O156
O157
O158
O159
O160
Note 1: L: Last Data
F: First Data
Row Mode
DIR
L
H
DF
L
L
H
H
EIO1
Data Input Terminals
EIO2
DIN
O160 → O1
OUT
IN
―
O1 → O160
IN
OUT
―
O160 → O81
O80 → O1
OUT
IN
IN
O1 → O80
O81 → O160
IN
OUT
IN
Data Flow
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Timing Diagram (Column mode)
T6C03
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T6C03
Timing Diagram (Row mode)
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T6C03
Absolute Maximum Ratings
(Ensure that the following conditions are maintained, VCC ≥ V0 ≥ V2 ≥ V3 ≥ V5 ≥ VSS)
Item
Symbol
Pin Name
Rating
Unit
Supply Voltage (1)
VDD
VDD
−0.3 to 7.0
V
Supply Voltage (2)
VCC
VCCL / R
−0.3 to 45.0
V
Supply Voltage (3)
V0, V2
V0L / R V2L / R
−0.3 to VCC + 0.3
V
Supply Voltage (4)
V3, V5
V3L / R V5L / R
−0.3 to 7.0
V
Input Voltage
VIN
(Note 2)
−0.3 to VDD + 0.3
V
Operating Temperature
Topr
―
−20 to 75
°C
Storage Temperature
Tstg
―
−40 to 125
°C
Note 2: SCP, FR, LP, DIR, DF, S / C, EIO1, EIO2, DI1 to 8, / DSPOF, TEST
Electrical Characteristics
DC Characteristics
(Unless otherwise noted, VSS = 0 V, VDD = 2.7 to 5.5 V, Ta = −20 to 75°C)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Supply Voltage 1
VDD
―
―
2.7
5.0
5.5
VDD
Supply Voltage 2
VCC
―
―
14
―
42
VCCL / R
VIH
―
0.8
VDD
―
VDD
0
―
0.2
VDD
VDD
− 0.5
―
VDD
0
―
0.5
Item
H Level
Input
Voltage
Output
Voltage
Output
Resistance
(Note 2)
L Level
VIL
―
H Level
VOH
―
IOH = − 0.5 mA
L Level
VOL
―
IOL = 0.5 mA
H Level
ROH
―
VOUT = V0 − 0.5 V
(Note 3)
―
0.6
1.3
M Level
ROM
―
VOUT = V2 ± 0.5 V
(Note 3)
―
0.6
1.3
―
VOUT = V3 ± 0.5 V
(Note 3)
―
0.6
1.3
L Level
ROL
―
VOUT = V5 + 0.5 V
(Note 3)
―
0.6
1.3
―
VDD = 5.5 V
VCC = 42 V
fLP = 33 kHz
fFR = 8.3 kHz
fscp = 8.0 MHz
Input Data: every bit inverted
VIH = 5.5 V, VIL = 0 V
―
―
4.0
Current
Consumption (Note 4)
IDD
Unit
V
Pin Name
SCP, FR, LP,
DIR, DF, S / C,
EIO1, EIO2,
DI1 to 8,
/ DSPOF,
TEST
EIO1, EIO2
kΩ
O1 to O160
mA
VDD
Note 3: VCC = 20 V, 1 / 13 bias
Note 4: Current consumption while the internal data receiver is operating
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T6C03
AC Electrical Characteristics (Column mode)
Test Conditions (1) (VSS = 0 V, VDD = 5 V ± 10%, VCC = 14 to 42 V, Ta = − 20 to 75°C)
Item
Symbol
Test Condition
Min
Max
Unit
tC
―
125
―
ns
SCP Pulse Width
tCWH, tCWL
―
50
―
ns
Data Set−Up Time
tDSU
―
50
―
ns
Data Hold Time
tDHD
―
50
―
ns
SCP Rise / Fall Time
tr, tf
―
―
(Note 5)
ns
LP Rise Time
tLRP
―
50
―
ns
LP Fall Time
tLFP
―
50
―
ns
LP Pulse Width
tLW
―
45
―
ns
SCP−to−LP Delay Time
tSL
―
40
―
ns
LP−to−SCP Delay Time
tLS
―
40
―
ns
EIO IN Fall Time
tEIFP
―
40
―
ns
EIO IN Pulse Width
tEIW
―
40
―
ns
tSE
―
Clock Cycle
SCP−to−EIO Delay Time
EIO−OUT Delay Time
tEOD
(Note 6)
20
―
ns
―
80
ns
Note 5: tr, tf ≤ (tC − tCWH − tCWL) / 2 and tr, tf ≤ 50 ns
Note 6: CL = 30 pF
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T6C03
Test Conditions (2) (VSS = 0 V, VDD = 2.7 to 4.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C)
Item
Symbol
Test Condition
Min
Max
Unit
tC
―
500
―
ns
SCP Pulse Width
tCWH, tCWL
―
240
―
ns
Data Set−Up Time
tDSU
―
240
―
ns
Data Hold Time
tDHD
―
240
―
ns
SCP Rise / Fall Time
tr, tf
―
―
(Note 7)
ns
LP Rise Time
tLRP
―
220
―
ns
LP Fall Time
tLFP
―
240
―
ns
LP Pulse Width
tLW
―
240
―
ns
SCP−to−LP Delay Time
tSL
―
70
―
ns
LP−to−SCP Delay Time
tLS
―
100
―
ns
EIO IN Fall Time
tEIFP
―
240
―
ns
EIO IN Pulse Width
tEIW
―
240
―
ns
SCP−to−EIO Delay Time
tSE
―
50
―
ns
―
260
ns
Clock Cycle
EIO−OUT Delay Time
tEOD
(Note 8)
Note 7: tr, tf ≤ (tC − tCWH − tCWL) / 2 and tr, tf ≤ 50 ns
Note 8: CL = 30 pF
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T6C03
AC Electrical Characteristics (Row mode)
Test Conditions (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C)
Item
Symbol
Test Condition
Min
Max
Unit
LP Pulse Width H
tCWH
LP
30
―
ns
LP Pulse Width L
tCWL
LP
195
―
ns
SCP Rise / Fall Time
tr, tf
LP, FR, EIO1, EIO2, DIN
―
20
ns
Data Set−up Time
tDSU
EIO1, EIO2, DIN
80
―
ns
Data Hold Time
tDHD
EIO1, EIO2, DIN
0
―
ns
EIO−OUT Delay Time A
(Note 9)
tpdA
EIO1, EIO2, DIN
5
―
ns
EIO−OUT Delay Time A
(Note 9)
tpdB
EIO1, EIO2, DIN
―
150
ns
(Note 10)
tPHL
O1 to O120
―
800
ns
LCD Drive Data Delat Time
Test Conditions (2) (VSS = 0 V, VDD = 2.7 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C)
Item
Symbol
Test Condition
Min
Max
Unit
LP Pulse Width H
tCWH
LP
100
―
ns
LP Pulse Width L
tCWL
LP
400
―
ns
SCP Rise / Fall Time
tr, tf
LP, FR, EIO1, EIO2, DIN
―
20
ns
Data Set−up Time
tDSU
EIO1, EIO2, DIN
100
―
ns
Data Hold Time
tDHD
EIO1, EIO2, DIN
0
―
ns
EIO−OUT Delay Time A
(Note 9)
tpdA
EIO1, EIO2, DIN
5
―
ns
EIO−OUT Delay Time A
(Note 9)
tpdB
EIO1, EIO2, DIN
―
400
ns
(Note 10)
tPHL
O1 to O120
―
1000
ns
LCD Drive Data Delat Time
Note 9: CL = 30 pF
Note 10: CL = 20 pF
Note: Insert the bypass capacitor (0.1 µF) between VDD and VSS, to decrease power supply noise.
Place the bypass capacitor as close to the LSI as possible.
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