ETC TA2024

TECHNICAL INFORMATION
Ω) Class-T™ Digital Audio Amplifier using
Stereo 10W (4Ω
Digital Power Processing™ Technology
TA2024
February 27, 2001 – Preliminary Rev. 1.0
General Description
The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power Amplifier
IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T amplifiers offer
both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
Features
¾Computer/PC Multimedia
¾DVD Players
¾Cable Set-Top Products
¾Televisions
¾Video CD Players
¾Battery Powered Systems
¾Class-T architecture
¾Single Supply Operation
¾“Audiophile” Quality Sound
¾0.04% THD+N @ 9W, 4Ω
¾0.18% IHF-IM @ 1W, 4Ω
¾6W @ 8Ω, 0.1% THD+N
¾11W @ 4Ω, 0.1% THD+N
¾High Power
¾10W @ 8Ω, 10% THD+N
¾15W @ 4Ω, 10% THD+N
¾High Efficiency
¾88% @ 10W, 8Ω
¾81% @ 15W, 4Ω
¾Dynamic Range = 102 dB
¾Mute and Sleep inputs
¾Turn-on & turn-off pop suppression
¾Over-current protection
¾Over-temperature protection
¾Bridged outputs
¾36-pin Power SOP package
Benefits
¾Fully integrated solution with FETs
¾Easier to design-in than Class-D
¾Reduced system cost with no heat sink
¾Dramatically improves efficiency versus
Class-AB
¾Signal fidelity equal to high quality linear
amplifiers
¾High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Typical Performance
THD+N versus Output Power
10
5
VDD = 12V
f = 1kHz
Av = 12
BW = 22Hz - 22kHz
2
THD+N (%)
1
0.5
0.2
RL= 8Ω
0.1
RL= 4Ω
0.05
0.02
0.01
500m
1
2
5
10
20
Output Power (W)
TA2024 Preliminary, Rev. 1.0
Page 1
TECHNICAL INFORMATION
Absolute Maximum Ratings (Note 1)
SYMBOL
PARAMETER
Value
UNITS
VDD
Supply Voltage
16
V
V5
Input Section Supply Voltage
6.0
V
SLEEP
SLEEP Input Voltage
-0.3 to 6.0
V
MUTE
MUTE Input Voltage
-0.3 to V5+0.3
V
ESDHBM
ESD Susceptibility,
Human Body Model (Note2)
2000
1000
V
V
ESDMM
ESD Susceptibility, Machine Model (Note 3)
TSTORE
Storage Temperature Range
TA
Operating Free-air Temperature Range
TJ
Junction Temperature
All pins except pins 1,4
Pins 1, 4
200
V
-40 to 150
°C
0 to 70
°C
150
°C
Note 1 : Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2 : Human Body Model, 100pF discharged through a 1.5kΩ resistor.
Note 3 : Machine Model, 200pF discharged directly to each pin
Note 4 : See Power Dissipation Derating in the Applications Information section.
Operating Conditions (Note 5)
MIN.
TYP.
MAX.
UNITS
VDD
SYMBOL
Supply Voltage
PARAMETER
8.5
12
13.2
V
VIH
High-level Input Voltage (MUTE, SLEEP)
3.5
VIL
Low-level Input Voltage (MUTE, SLEEP)
V
1
V
Note 5: Recommended Operating Conditions indicate conditions for which the device is functional.
See Electrical Characteristics for guaranteed specific performance limits.
Page 2
TA2024 Preliminary, Rev. 1.0
TECHNICAL INFORMATION
Electrical Characteristics
See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement
Bandwidth = 22kHz, RL = 4Ω, TA = 25 °C, Package heat slug soldered to 2.8 square-inch PC pad.
SYMBOL
PO
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
THD+N = 10%
IDD,MUTE
Mute Supply Current
RL = 4Ω
RL = 8Ω
RL = 4Ω
RL = 8Ω
MIN.
TYP.
9
5.5
12
8
11
6
16
10
MUTE = VIH
5.5
MAX.
UNITS
W
W
W
W
7
mA
IDD, SLEEP
Sleep Supply Current
SLEEP = VIH
0.25
2
mA
Iq
Quiescent Current
VIN = 0 V
61
75
mA
THD + N
PO = 9W/Channel
0.04
IHF-IM
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
19kHz, 20kHz, 1:1 (IHF)
0.18
SNR
Signal-to-Noise Ratio
A-Weighted, POUT = 1W, RL = 8Ω
CS
Channel Separation
30kHz Bandwidth
50
55
dB
PSRR
Power Supply Rejection Ratio
Vripple = 100mV.
60
80
dB
η
Power Efficiency
POUT = 10W/Channel, RL = 8Ω
88
%
VOFFSET
Output Offset Voltage
No Load, MUTE = Logic Low
VOH
High-level output voltage
(FAULT & OVERLOAD)
Low-level output voltage
(FAULT & OVERLOAD)
Output Noise Voltage
VOL
eOUT
Note:
%
0.5
89
50
150
3.5
mV
V
1
A-Weighted, input AC grounded
%
dB
100
V
µV
Minimum and maximum limits are guaranteed but may not be 100% tested.
TA2024 Preliminary, Rev. 1.0
Page 3
TECHNICAL INFORMATION
Pin Description
Pin
2, 3
Function
DCAP2, DCAP1
4, 9
5, 8,
17
6
7
10, 14
11, 15
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
VP1, VP2
IN1, IN2
12
MUTE
16
18
BIASCAP
SLEEP
19
FAULT
20, 35
22
24, 27;
31, 28
25, 26,
29, 30
13, 21,
23, 32,
34
33
36
1
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD2
VDD1, VDD1
NC
VDDA
CPUMP
5VGEN
Description
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground
Bridged outputs
Supply pins for high current H-bridges, nominally 12VDC.
Not connected. Not bonded internally.
Analog 12VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
36-pin Power SOP Package
(Top View)
+5VGEN
DCAP2
DCAP1
V5D
AGND1
REF
OVERLOADB
AGND2
V5A
VP1
IN1
MUTE
NC
VP2
IN2
BIASCAP
AGND3
SLEEP
Page 4
1
2
36
3
4
5
34
6
7
8
9
35
33
32
31
30
29
28
CPUMP
PGND1
NC
VDDA
NC
OUTP1
VDD1
VDD1
OUTM1
10
27
11
12
13
14
26
15
16
17
22
20
DGND
NC
PGND2
18
19
FAULT
25
24
23
21
OUTM2
VDD2
VDD2
OUTP2
NC
TA2024 Preliminary, Rev. 1.0
TECHNICAL INFORMATION
Application / Test Circuit
TA2024
CI
2.2uF
+
VDD1
VP1 10
RF
20KΩ
31
IN1 11
RI
20KΩ
CA
0.1uF
DO
BIASCAP
Processing
&
Modulation
16
PGND1
MUTE
12
PGND1
19
RF
20KΩ
7
VP2 14
3
+12V
CD
0.1uF
2
18
PGND2
RL
4Ω or *8Ω
Lo
10uH, 2A
(Pin 20)
(Pin 20)
*Co
0.47uF
CZ
0.47uF
VDD2
DCAP1
27
OUTM2
Lo
10uH, 2A
RZ
*Co
0.47uF 10Ω, 1/2W
CCM
0.1uF
RL
4Ω or *8Ω
DO
DCAP2
(Pin 20)
SLEEP
CPUMP 36
0.1uF
4
CS
0.1uF
To Pin 1
RZ
10Ω, 1/2W
FAULT
OVERLOADB
DO
Processing
&
Modulation
REF
PGND2
1meg Ω
*Co
0.47uF
CCM
0.1uF
DO
(Pin 35)
24 OUTP2
RI
20KΩ
RREF
(Pin 8)
8.25KΩ, 1%
Lo
10uH, 2A
CZ
0.47uF
VDD2
IN2 15
6
*Co
0.47uF
(Pin 35)
28 OUTM1
5V
5V
(Pin 35)
VDD1
(Pin 8)
CI
2.2uF
+
Lo
10uH, 2A
OUTP1
5
9
CS
0.1uF
8
17
33
CP
1uF
22
CS
0.1uF
1
CS
0.1uF
+
5V
V5D
VDDA
AGND1
V5A
DGND
+5VGEN
AGND2
AGND3
VDD1
VDD1
To Pins 4,9
30
29
PGND1 35
13
21
23
32
34
CSW
0.1uF
+
VDD (+12V)
CSW
180uF, 16V
25
VDD2
NC
VDD2
PGND2
26
20
CSW
0.1uF
+
CSW
180uF, 16V
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2024
Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use Co = 0.22µF for 8 Ohm loads
TA2024 Preliminary, Rev. 1.0
Page 5
TECHNICAL INFORMATION
External Components Description (Refer to the Application/Test Circuit)
Components
RI
RF
CI
RREF
CA
CD
CP
CS
CSW
CZ
RZ
DO
LO
CO
CCM
Page 6
Description
Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at
the BIASCAP voltage (approximately 2.4VDC).
Feedback resistor to set AC gain in conjunction with RI; A V = 12(RF / RI ) . Please refer to the
Amplifier Gain paragraph in the Application Information section.
AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at
fC = 1 ( 2πRICI )
Bias resistor. Locate close to pin 6 and ground at pin 8.
BIASCAP decoupling capacitor. Should be located close to pin 16.
Charge pump input capacitor. This capacitor should be connected directly between pins 2
and 3 and located physically close to the TA2024.
Charge pump output capacitor that enables efficient high side gate drive for the internal Hbridges. To maximize performance, this capacitor should be connected directly between
pin 36 (CPUMP) and pin 34 (VDDA). Please observe the polarity shown in the Application/
Test Circuit.
Supply decoupling for the low current power supply pins. For optimum performance, these
components should be located close to the pin and returned to their respective ground as
shown in the Application/Test Circuit.
Supply decoupling for the high current, high frequency H-Bridge supply pins. These
components must be located as close to the device as possible to minimize supply
overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and
bulk capacitor (180uF) should have good high frequency performance including low ESR
and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.
Zobel Capacitor.
Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies.
The combination of RZ and CZ minimizes peaking of the output filter under both no load
conditions or with real world loads, including loudspeakers which usually exhibit a rising
impedance with frequency.
Schottky diodes that minimize undershoots of the outputs with respect to power ground
during switching transitions. For maximum effectiveness, these diodes must be located
close to the output pins and returned to their respective PGND. Please see
Application/Test Circuit for ground return pin.
Output inductor, which in conjunction with CO, demodulates (filters) the switching waveform
into an audio signal. Forms a second order filter with a cutoff frequency of
f C = 1 ( 2 π L O C O ) and a quality factor of Q = R L C O
LOCO .
Output capacitor.
Common Mode Capacitor.
TA2024 Preliminary, Rev. 1.0
TECHNICAL INFORMATION
Typical Performance Characteristics
Frequency Response
Efficiency versus Output Power
+3
100
+2.5
90
RL = 8Ω
80
+2
Efficiency (%)
Output Amplitude (dBr)
+1.5
70
RL = 4Ω
60
50
40
30
VDD = 12V
f = 1kHz
Av = 12
THD+N < 10%
20
10
VDD = 12V
Pout = 1W
RLoad = 4Ω
Av = 12
BW = 22Hz - 22kHz
+1
+0.5
+0
-0.5
-1
-1.5
-2
0
-2.5
0
5
10
15
20
-3
10
Output Power (W)
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Noise Floor
Intermodulation Performance
+0
+0
VDD = 12V
Pout = 1W/Channel
RLoad = 4Ω
0dBr = 12Vrms
19kHz, 20kHz, 1:1
Av = 11.7
BW = 10Hz - 80kHz
-20
FFT (dBr)
-30
VDD = 12V
Pout = 0W
RLoad = 4Ω
Av = 12
BW = 22Hz - 22kHz
A-Weighted Filter
-20
Noise FFT (dBV)
-10
-40
-50
-60
-40
-60
-80
-100
-70
-80
-120
-90
-140
-100
50
1k
2k
5k
10k
20k
30k
20
100
50
Frequency (Hz)
500
1k
2k
5k
10k
20k
Frequency (Hz)
Channel Separation versus Frequency
THD+N versus Frequency
10
+0
VDD = 12V
Pout = 5W/Channel
Av = 12
BW = 22Hz - 22kHz
2
1
0.5
0.2
0.1
RL = 4Ω
0.05
VDD = 12V
Pout = 1W/Channel
RLoad = 4Ω
Av = 12
BW = 22Hz - 22kHz
-10
Channel Separation (dBr)
5
THD+N (%)
200
-20
-30
-40
-50
-60
-70
-80
RL = 8Ω
0.02
-90
0.01
-100
10
20
50
100
200
500
1k
2k
Frequency (Hz)
TA2024 Preliminary, Rev. 1.0
5k
10k
20k
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Page 7
TECHNICAL INFORMATION
Application Information
Layout Recommendations
The TA2024 is a power (high current) amplifier that operates at relatively high switching frequencies.
The outputs of the amplifier switch between the supply voltage and ground at high speeds while
driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to
recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and
speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the
energy in the output inductance. To avoid subjecting the TA2024 to potentially damaging voltage
stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath’s layout
and application circuit be used for all applications and only be deviated from after careful analysis of
the effects of any changes. Please contact Tripath Technology for further information regarding
reference design material regarding the TA2024.
Amplifier Gain
The gain of the TA2024 is set by the ratio of two external resistors, RI and RF, and is given by the
following formula:
VO
R
= 12 F
VI
RI
where VI is the input signal level and VO is the differential output signal level across the speaker.
9 Watts of RMS output power results from an 8.485V RMS signal across an 8Ω speaker load. If
RF = RI, then 9 Watts will be achieved with 0.707V RMS of input signal.
8.485 VRMS = (R L ∗ PO ) = (8Ω ∗ 9 W )
Protection Circuits
The TA2024 is guarded against over-temperature and over-current conditions. When the device
goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state
indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI-STATED,
and will float to 1/2 of VDD.
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately
155°C. The thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically
clear when the junction temperature drops below 110°C.
Page 8
TA2024 Preliminary, Rev. 1.0
TECHNICAL INFORMATION
Over-current Protection
An over-current fault occurs if more than approximately 7 amps of current flows from any of the
amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the
speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if
the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to
the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset
the fault condition.
Overload
The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal
has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal
can be used to control a distortion indicator light or LED through a simple buffer circuit, as the
OVERLOADB cannot drive an LED directly.
Sleep Pin
The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent
current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the
pin to be pulled up through a large valued resistor (1megΩ recommended) to VDD. To disable SLEEP
mode, the sleep pin should be grounded.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These
conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over
current at any output, and junction temperature greater than approximately 155°C. All faults except
overcurrent all reset upon removal of the condition. The FAULT output is capable of directly driving
an LED through a series 200Ω resistor. If the FAULT pin is connected directly to the MUTE input an
automatic reset will occur in the event of an over-current condition.
TA2024 Preliminary, Rev. 1.0
Page 9
TECHNICAL INFORMATION
Power Dissipation Derating
For operating at ambient temperatures above 25°C the device must be derated based on a 150°C
maximum junction temperature, TJMAX as given by the following equation:
PDISS =
(TJMAX − TA )
θ JA
where…
PDISS = maximum power dissipation
TJMAX = maximum junction temperature of TA2024
TA = operating ambient temperature
θJA = junction-to-ambient thermal resistance
Where θJA of the package is determined from the following graph:
Θ JA vs Copper Area
o
JA ( C/W)
50
40
Pdiss - 1.35W
30
Pdiss - 2W
Pdiss - 3.4W
20
10
0
1
2
3
4
5
6
Copper Area (square inches)
In the above graph Copper Area is the size of the copper pad on the PC board to which the heat slug
of the TA2024 is soldered. The heat slug must be soldered to the PCB to increase the maximum
power dissipation capability of the TA2024 package. Soldering will minimize the likelihood of an overtemperature fault occurring during continuous heavy load conditions. The vias used for connecting
the heatslug to the copper area on the PCB should be 0.013” diameter.
Page 10
TA2024 Preliminary, Rev. 1.0
TECHNICAL INFORMATION
Performance Measurements of the TA2024
The TA2024 operates by generating a high frequency switching signal based on the audio input. This
signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified
version of the audio input. The frequency of the switching pattern is spread spectrum and typically
varies between 100kHz and 1.0MHz, which is well above the 20Hz – 20kHz audio band. The pattern
itself does not alter or distort the audio input signal but it does introduce some inaudible components.
The measurements of certain performance parameters, particularly noise related specifications such
as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as
the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off
just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the
inaudible noise components introduced by the Tripath amplifier switching pattern will degrade the
measurement.
One feature of the TA2024 is that it does not require large multi-pole filters to achieve excellent
performance in listening tests, usually a more critical factor than performance measurements.
Though using a multi-pole filter may remove high-frequency noise and improve THD+N type
measurements (when they are made with wide-bandwidth measuring equipment), these same filters
degrade frequency response. The TA2024 Evaluation Board uses the Test/Application Circuit in this
data sheet, which has a simple two-pole output filter and excellent performance in listening tests.
Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in
the measurement instrument.
TA2024 Preliminary, Rev. 1.0
Page 11
TECHNICAL INFORMATION
Package Information
36-Lead Power Small Outline Package (PSOP),
compliant with JEDEC outline MO-166, variation AE:
Package Dimensions for TYPE 1
E2
2 PLACES
E3
E
3.10 REF
1
E1
3 2
36
D1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.80
L
1.60 REF
1.10
Note: All dimensions are in millimeters.
Page 12
c
Max.
0.38
0.32
16.00
9.80
14.50
11.10
2.90
6.20
DETAIL "A"
TA2024 Preliminary, Rev. 1.0
4º +/- 4º
Nom.
----15.90
--14.20
11.00
----0.65 BSC.
0.35 BSC.
---
L1
Min.
0.22
0.23
15.80
9.40
13.90
10.90
--5.80
END VIEW
GAUGE PLANE
SIDE VIEW
Dimension
b
c
D
D1
E
E1
E2
E3
e
L1
L
0.20 +/- 0.10
b
0.15 REF
e
3.15 +/- 0.15
3.35 REF
D
TECHNICAL INFORMATION
Package Dimensions for TYPE 2
2.24
E2
2 PLACES
E3
E
3.10 REF
1
E1
3 2
36
D1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.80
L
1.60 REF
1.10
Note: All dimensions are in millimeters.
TA2024 Preliminary, Rev. 1.0
4º +/- 4º
Max.
0.38
0.32
16.00
13.00
14.50
11.10
2.90
6.20
L1
Nom.
----15.90
--14.20
11.00
----0.65 BSC.
0.35 BSC.
---
GAUGE PLANE
Min.
0.25
0.23
15.80
9.00
13.90
10.90
--5.80
END VIEW
c
SIDE VIEW
Dimension
b
c
D
D1
E
E1
E2
E3
e
L1
L
0.20 +/- 0.10
b
0.15 REF
e
3.15 +/- 0.15
3.35 REF
D
DETAIL "A"
Page 13
TECHNICAL INFORMATION
Tripath, Class T, Combinant Digital, DPP and Digital Power Processing are trademarks of Tripath
Technology Inc. Other trademarks referenced in this document are owned by their respective
companies.
Tripath Technology Inc. reserves the right to make changes without further notice to any products
herein to improve reliability, function or design. Tripath does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under
its patent rights, nor the rights of others.
TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITOUT THE EXPRESS WRITTEN CONSENT OF THE
PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in this labeling, can be reasonably expected
to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system, or to affect
its safety or effectiveness.
For more information on Tripath products, visit our web site at:
www.tripath.com
TRIPATH TECHNOLOGY, INC.
3900 Freedom Circle
Santa Clara, California 95054
408-567-3000
Page 14
TA2024 Preliminary, Rev. 1.0