TOSHIBA TB62726AN, TB62726AF TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC T B 6 2 7 2 6 A N, T B 6 2 7 2 6 A F 16-bit constant current LED driver with operation supply of 3.3V to 5V The TB62726A series are comprised of constant-current drivers designed for LEDs and LED displays. The output current value can be set using an external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates 16-bit constant-current outputs, a 16-bit shift register, a 16-bit latch and 16-bit AND-gate circuit. These drivers have been designed using the Bi-CMOS process. TB62726AN Feature *Output current capability and the number of output: P-SDIP24-300-1.78 90 mA x 16 outputs TB62726AF *Constant current range : 2 to 90 mA *Application output voltage : 0.7V (output current 2 to 80mA) 0.4V (output current 2 to 40mA) *For anode common LED *Input signal voltage level : 3.3V-5.0V CMOS level (schmitt trigger input) P-SSOP24-300-1.00B *Power supply voltage range VDD=3.0 to 5.5V *Muximum output terminal voltage 17V *Serial and parallel data transfer rate 20 MHz (min., Cascade Connection) *Operation temperature range topr = -40 to 85 degrees *Package : AN type - - - P-SDIP-300-1.78 AF type - - - P-SSOP24-300-1.00B *Current accuracy (not used dot-current correction.) Output voltage >= 0.4V >= 0.7V Current accuracy between bits between ICs +/- 4 % +/- 12 % Output current 2 to 40 mA 2 to 90 mA TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 1/16 TOSHIBA TB62726AN, TB62726AF Package and pin layout ( Top view ) GND SERIAL-IN CLOCK LATCH OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 VDD R-EXT SERIAL-OUT ENABLE OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 OUT 10 OUT 9 OUT 8 Warnings : Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals. Block Diagram OUT0 R-EXT OUT1 OUT15 I-REG ENABLE Q Q Q ST D ST D ST D LATCH SERIAL-IN D Q D Q D Q CK CK CK SERIAL-OUT CLOCK Truth Table CLOCK LATCH ENABLE SERIAL-IN OUT0 --- OUT7 --- OUT15 SERIAL-OUT Positive edge H L Dn Dn --- Dn-7 --- Dn-15 Dn-15 Positive edge L L Dn+1 No Change Dn-14 Positive edge H L Dn+2 Dn+2 --- Dn-5 --- Dn-13 Dn-13 Negative edge X L Dn+3 Dn+2 --- Dn-5 --- Dn-13 Dn-13 Negative edge X H Dn+3 Off Dn-13 Note 1: OUT0~OUT15=ON when Dn=H ; OUT0~OUT15=OFF when Dn=L In order to ensure that the level of the power supply voltage is correct, an external resistor have to connected between R-EXT and GND. TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 2/16 TOSHIBA TB62726AN, TB62726AF Timing diagram n=0 1 2 3 4 5 6 7 8 9 101112131415 CLOCK 3.3v/5v 0V SERIAL-IN 3.3v/5v 0V LATCH 3.3v/5v 0V 3.3v/5v 0V ENABLE OUT0 On Off OUT1 On Off OUT3 On Off OUT15 On Off SERIAL-OUT 3.3v/5v 0V Warning : Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2 : The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch circuit doesn’t hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output terminal OUT0~OUT15 respond to the data, and on & off does. And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data. TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 3/16 TOSHIBA TB62726AN, TB62726AF Terminal description Pin No. 1 2 3 Pin Name GND SERIAL-IN CLOCK 4 LATCH 5 ~ 20 Function GND terminal for control logic Input terminal for serial data for data shift register Input terminal for clock for data shift on rising edge Input terminal for data strobe When the LATCH=High-level, data is no latched. When ithe LATCH=Low-level, data is latched. Constant-current output terminals OUT 0 ~ 15 Input terminal for output enable. All outputs (OUT0 ~ OUT15 ) are turned off, when the ENABLE=High-level. And are turned on, when the ENABLE=Low-level. SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3V - 5V supply voltage terminal. 21 ENABLE 22 23 24 Equivalent circuit of inputs and output VDD 2. LATCH Terminal R(UP) VDD 200k 1. ENABLE Terminal LATCH GND GND 3. CLOCK,SERIAL-IN Terminal 4. SERIAL-OUT Terminal VDD VDD CLOCK, SERIAL - IN Internal data GND GND 250k ENABLE R(DOWN) SERIAL - OUT 5. OUT0 ~ 15 Terminal OUT 0 ~ 15 Parasitic Diode GND TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 4/16 TOSHIBA TB62726AN, TB62726AF Absolute maximum ratings Characteristics Supply Voltage Symbol VDD Rating +6 Input Voltage Output Current Output Voltage Operating Temperature VIN IOUT VOUT Pd1 Pd2 Rth(j-a)1 Rth(j-a)2 Topr -0.2 to VDD+0.2 +90 -0.2 to 17 AN type : 1.25(Free air), 1.78(On PCB) AF type : 0.83(Free air), 1.00(On PCB) AN type : 104(Free air), 70(On PCB) AF type : 140(Free air), 120(On PCB) -40 to 85 Storage Temperature Tstg -55 to 150 Power Dissipation Thermal Resistance Unit V mA/ch V W degree/W degree Note 3: AN-type: Powers dissipation is derated by 14.28 mW/degree if device is mounted on PCB and ambient temperature is above 25 degree. FN-type: Powers dissipation is derated by 6.67 mW/degree if device is mounted on PCB and ambient temperature is above 25 degrees. With devide monuted on glass-epoxy PCB of less than 40% Cu and of dimensions 50mm x 50 mm x 1.6mm. Recommended operating condition ( Topr = -40~85 degree, unless otherwise noted. ) Characteristics Supply Voltage Output Voltage Symbol VDD VOUT(On) IOUT Output Current IOH IOL Input Voltage VIH VIL Clock Frequency fCLK LATCH Pulse Width tw LATCH CLOCK Pulse Width tw CLOCK ENABLE Pulse Width When the pulse of the Low level is inputted to the ENABLE terminal held in the H level. Setup Time for CLOCK Terminal Hold Time for CLOCK Terminal Setup Time for /LATCH Terminal Condition Each DC 1 Circuit Min 3 2 Typ 0.7 - Max 5.5 4 80 - - -1 - - 1 0.7VDD - VDD+0.15 -0.15 - 0.3xVDD - - 20 Cascade Connected 50 25 - - Upper IOUT=20mA 2000 - - Lower IOUT=20 mA 3000 - - 10 10 - - 50 - - SERIAL-OUT - Unit V V mA/ch mA V MHz tw ENABLE t SETUP1 t HOLD ns - t SETUP2 Note 4: When the pulse of the “L” level is inputted to the ENABLE terminal held in the “H” level. TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 5/16 TOSHIBA TB62726AN, TB62726AF Electrical characteristics ( VDD=3V to 5.5V, Topr=25degree unless otherwise noted.) Characteristics Supply voltage Output current Output current error between bits Symbol VDD IOUT1 IOUT2 IOUT3 IOUT4 dIOUT1 dIOUT2 Output leakage Current Input voltage IOZ Input voltage VIN SOUT terminal Voltage Output current supply voltage regulation Pull up resistor Pull down resistor Supply current VOL VOH %/VDD R(UP) R(DOWN) IDD(OFF)1 IDD(OFF)2 IDD(OFF)3 IDD(ON)1 IDD(ON)2 Condition Normal operation VOUT=0.4V,VDD=3.3V REXT= VOUT=0.4V,VDD=5V 490 ohm VOUT=0.7V,VDD=3.3V REXT= VOUT=0.7V,VDD=5V 250 ohm VOUT=0.4V, REXT=490 ohm All output ON VOUT=0.4V, REXT=250 ohm Min 3.0 31.96 31.59 63.63 62.75 Typ 36.20 35.90 72.30 71.30 Max 5.5 40.54 40.20 80.97 79.95 Unit V - +/-1 +/-4 % VOUT=15V - - 1 µA IOL=+1 mA, Vdd=3.3V IOL=+1 mA, Vdd=5V IOH=-1 mA, Vdd=3.3V IOH=+1 mA,Vdd=5V 0.7VDD GND . 3 4.7 - VDD 0.3VDD 0.3 0.3 - When VDD is changed 3V to 5.5V - -1 -5 . 115 230 460 .1 .4 0.1 3.5 6 0.5 5 9 - 9 15 - - 20 - 18 25 - - 40 ENABLE terminal LATCH terminal REXT=Open, VOUT=15V REXT=490ohm All output OFF, VOUT=15V REXT=250ohm All output ON, REXT=490ohm VOUT=0.7V Ta= -40degree, Same as the avobe. All output ON, REXT=250ohm VOUT=0.7V Ta= -40 degree, Same as the avobe. mA V V %/V Ohm TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 6/16 TOSHIBA TB62726AN, TB62726AF Switching characterictics (Topr=25degree, unless otherwise noted ) Characteristics Propagation delay Symbol tpLH1 Condition CLK-OUTn, LATCH=”H”, ENABLE=”L” Min - Typ 150 Max 300 tpLH2 LATCH-OUTn, ENABLE=”L” - 140 300 tpLH3 ENABLE-OUTn, LATCH=”H” - 140 300 tpLH CLK-SERIALOUT 3 6 - tpHL1 CLK-OUTn, LATCH=”H”, ENABLE=”L” - 170 340 tpHL2 LATCH-OUTn, ENABLE=”L” - 170 340 tpHL3 ENABLE-OUTn, LATCH=”H” - 170 340 tpLH CLK-SERIAL-OUT 4 7 - tor Voltage waveform 10%~90% 40 85 150 Output rise time Unit ns tof Output fall time Voltage waveform 90%~10% 40 70 150 Maximum CLK 5 tr rise time us When not on PCB Maximum CLK 5 tf fall time Condition : (Refer to test circuit) Topr=25 degree, VDD=VIH=3.3V and 5V, VOUT=0.7V, VIL=0V,REXT=490ohms, VL=3.0V, RL=60ohms,CL=10.5pF Note 5 : If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test circuit IDD V ,V IH IL VDD ENABLE RL OUT0 CLOCK Function Generator C LATCH SERIAL-IN R-EXT Logic input waveform Iref L OUT15 IOL SERIAL-OUT GND CL VL VDD=VIH=3.3V VIL=0V t = t = 10ns r f (10% to 90%) TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 7/16 TOSHIBA TB62726AN, TB62726AF Timing Waveform 1. CLOCK ,SERIAL-IN, SERIAL-OUT CLOCK SERIAL-IN twCLK 50% 50% 50% t SETUP1 50% t HOLD SERIAL-OUT 50% tpLH / tpHL 2. CLOCK, SERIAL-IN , LATCH, ENABLE, OUTn CLOCK 50% SERIAL-IN LATCH ENABLE t SETUP2 50% 50% tw LAT tSETUP3 50% tw ENA OUTn 50% 50% tpLH1 / tpHL1 tpLH2 / tpHL2 3. OUTn 90% tpLH3 / tpHL3 90% OUTn 10% tOf 10% tOr TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 8/16 TOSHIBA TB62726AN, TB62726AF Output current vs duty (LEDs turn on rate) IOUT - Duty On PCB Topr=55 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 90 90 80 80 70 70 60 60 IOUT(mA) IOUT(mA) IOUT - Duty On PCB Topr=25 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 50 40 30 30 20 20 TB62726AF 10 0 0 TB62726AN 20 40 60 80 DUTY - Turn On Rate (%) 0 100 90 90 70 80 60 70 Topr=+25(degree) 40 30 IOUT(mA) 80 20 40 60 80 DUTY - Turn On Rate (%) 100 60 50 40 30 20 20 10 10 1000 REXT(ohm) 10000 TB62726AF TB62726AN 0 0 20 40 60 80 DUTY - Turn On Rate (%) 100 Pd - Ta 2 1.8 1.6 Power dissipation P D (W/IC) 0 100 0 TB62726AN IOUT - Duty On PCB Topr=85 degree VDD=3.3~5.0 V, Vce=1 V, Tj=120 degree max 100 Vce=0.7 V 50 TB62726AF 10 REXT - IOUT (Topr) IOUT (mA) 50 40 1.4 1.2 1 0.8 0.6 0.4 1: AF(OnPCB) 0.2 2: AN(On PCB) 0 0 10 20 30 40 50 60 70 80 Ambient Temperature Ta (degree) 90 TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 9/16 C.U. TB62726A N/F r2 S-OUT Out 15 Constant Sink Current Drivers 16-BIT SIPO,Latches & r1=100 ohm(min) CLK LAT ENA S-IN Out 0 SCAN TB62726A N/F S-OUT Out 15 Constant Sink Current Drivers 16-BIT SIPO,Latches & r1=100 ohm(min) CLK LAT ENA S-IN Out 0 VLED Example ) TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting. More than VLED(V) >= Vf(total max.) +0.7 is recommended with the following application circuit with the LED power supply VLED. r1:The setup resistance for the setup of output current of every IC. r2:The variable resistance for the brightness control of every LED module. Application circuit (example 1) : The general composition in static lighting of LED. TOSHIBA TB62726AN, TB62726AF TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 10/16 C.U. SCAN r2 CLK LAT ENA S-IN TB62726A N/F Constant Sink Current Drivers 16-BIT SIPO,Latches & r1=100 ohm(min) Out 0 S-OUT Out 15 CLK LAT ENA S-IN TB62726A N/F Constant Sink Current Drivers 16-BIT SIPO,Latches & r1=100 ohm(min) Out 0 VLED S-OUT Out 15 TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting. Example ) The unnecessary voltage is one effective technique as to making the voltage descend with the zenor diode. Application circuit (example 2) : When the condition of VLED is VLED > 17V. TOSHIBA TB62726AN, TB62726AF TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 11/16 C.U. r2 SCAN CLK LAT ENA S-IN TB62726A N/F Constant Sink Current Drivers 16-BIT SIPO,Latches & r1=100 ohm(min) Out 0 Though the resistance parts increase, the fixed constant current performance is kept. r3 can make a calculation to the formula r3 (ohms) = surplus VOUT / IOUT. It is the one way of being effective to build in the r3 in this problem. Surplus VOUT causes an IC fever and the useless consumption electric power. VOUT=VLED-Vf=0.7~1.0V is the most suitable for VOUT. S-OUT Out 15 CLK LAT ENA S-IN r1=100 ohm(min) TB62726A N/F Constant Sink Current Drivers 16-BIT SIPO,Latches & Example ) TD62M8600F : 8bit Multi-Chip PNP Tr-Array. It is unnecessary at the time of static lighting. VLED=15V S-OUT Application circuit (example 3) : When the condition of VLED is Vf+0.7<VLED<17V. TOSHIBA TB62726AN, TB62726AF TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 12/16 TOSHIBA TB62726AN, TB62726AF Note: Operating is likely to become unstable due to the electromagnetic guidance of wiring and so on. Recommend that it adjoins it and it is arranged so far as device and LED are possible. Damage by the over-voltage is likely to be suffered in LED and the output by over-voltage's occurring due to the inductance between LEDs from the output terminal. There is only one GND terminal in this device. When the inductance of the GND line, resistance element, and so on are big, it is likely to operate faultily by the GND noise when output switchings by the circuit board pattern and wiring. And, it is necessary for the REXT terminal to connect it in the GND line which became stable through the resistor. Vibration is likely to occur for the output wave form when GND was unstable and capacity (beyond 50pF) was added. Therefore, be fully careful of the circuit board pattern layout and wiring from the controller. This application circuit is a reference example, and it doesn't assure operating in all the conditions. Be sure to carry out operating confirmation. Thisdevice doesn't build in the protection circuit of over-voltage, over-current and over-temperature. Carry it out on the control side when protection is necessary. Device is likely to destroy it when it short-circuits between the output terminals to each power supply. Be fully careful of output terminal, each power supply (VDD, VLED) and the design of the GND line. TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 13/16 TOSHIBA TB62726AN, TB62726AF Package dimmension P-SSOP24-150-0.635 TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 14/16 TOSHIBA TB62726AN, TB62726AF TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 15/16 TOSHIBA TB62726AN, TB62726AF The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patens or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within spacified operating ranges as set forth in the most recent products spacifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The products described in the document may include products subject to foreign exchange and foreign trade control laws. (C) 2000-2002 TOSHIBA CORPORATION ALL RIGHT Reserved TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20th page 16/16