TOSHIBA TC9329AFCG

TC9329AFAG/AFCG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9329AFAG, TC9329AFCG
Portable Audio DTS Controller (DTS-21)
The TC9329AFAG/AFCG is a single-chip DTS microcontroller
for portable audio incorporating a 230-MHz prescaler, PLL, and
LCD driver. In addition to a 20-bit IF counter, 6-bit A/D
converter, serial interface, and buzzer function, the device
supports an interrupt function, 8-bit timer/counter, and 8-bit
pulse counter. The LCD driver features built-in 1/4 duty, 1/2 bias
and a 3-V voltage boosting circuit, implementing stable LCD. The
power supply voltage ranges from 0.9 to 1.8 V. Because of its low
current consumption (CPU: 80 µA (max)), the device is suitable
for use in digital tuning systems in portable equipment such as
headphone stereos.
TC9329AFAG
TC9329AFCG
Features
•
CMOS DTS microcontroller LSI with built-in 230 MHz
prescaler, PLL, and LCD driver
• Operating voltage: VDD = 0.9~1.8 V (typ.: 1.5 V)
• Current dissipation:
CPU in operation: IDD = 40 µA typ.
PLL in operation: IDD = 6 mA typ. (VHF mode)
• Operating temperature range: Ta = −10~60°C
Weight
• Program memory (ROM): 16 bits × 4096 steps
LQFP64-P-1010-0.50E : 0.32 g ( typ.)
• Data memory (RAM): 4 bits × 256 words
TQFP64-P-1010-0.50C : 0.26 g ( typ.)
• Instruction execution time: With crystal oscillator: 40 µs
With CR oscillator: 6 µs
(at 1 MHz, VDD = 1.1~1.8 V)
• Crystal oscillator frequency: 75 kHz
• Stack level: 8
• General-purpose IF counter: 20 bit (CMOS input supported)
• A/D converter: 6 bits × 4-channels
• LCD driver: 1/4 duty, 1/2 bias, 72 segments (max)
• I/O port: CMOS I/O ports: 12
N-channel open drain I/O ports: 16 (max)
Output-only port: 1
Input-only ports: 3 (max)
• Timer/counter: 8 bits (as timer clock: INTR1/INTR2; instruction cycle: 1 kHz selectable)
• Pulse counter: 8-bit up/down counter (input via INTR2 pin)
Buzzer:
8 settings, 0.625~3 kHz; 4 built-in modes consisting of continuous, single-shot, 10 Hz intermittent, or
10 Hz intermittent at 1 Hz intervals.
•
Interrupts: 2 external, 2 internal (serial interface, 8-bit timer)
•
Package: QFP-64 (0.5-mm/0.65-mm pitch, 1.4-mm thickness)
Note: Handle with care to prevent devices from deteriorating due to electrostatic discharge.
1
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TC9329AFAG/AFCG
TEST
HOLD (INTR2/PCTRin)
IFin1 (INTR1)
IFin2 (IN2)
GND
OSCin
VDD
DO (OT)
Vreg
P3-0
P3-1 (SI)
P3-2 (SO)
P3-3 (SCK)
P5-0 (ADin1)
P5-1 (ADin2)
P5-2 (ADin3)
Pin Assignment (top view)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P5-3 (ADin4)
49
P2-0
50
P2-1
51
A/D
SIO
PLL
N-channel open drain I/O ports (8)
32
MUTE
31
P4-3
30
P4-2
CMOS I/O ports (4)
CMOS I/O ports (4)
P2-2
52
29
P4-1
P2-3 (PSC)
53
28
P4-0 (BUZR)
RESET
54
27
VDD
XOUT
55
26
P1-3
25
P1-2
24
P1-1
SVFP64/TQFP64
(0.5 mm pitch)
Oscillation circuit
XIN
56
GND
57
VDB
58
23
P1-0
C1
59
22
P9-3 (S18)
21
P9-2 (S17)
20
P9-1 (S16)
19
P9-0 (S15)
18
P8-3 (S14)
17
P8-2 (S13)
2
3
4
5
6
7
8
COM3 (OT3)
COM4 (OT4)
S1 (OT5)
S2 (OT6)
S3 (OT7)
S4 (OT8)
9
S5 (OT9)
1
COM2 (OT2)
64
COM1 (OT1)
VLCD
LCD driver (1/4 duty, 1/2 bias: 72 segments max)
2
10 11 12 13 14 15 16
P8-1 (S12)
63
P8-0 (S11)
C4
S10 (OT14)
62
S9 (OT13)
C3
N-channel open drain/
CMOS I/O ports (8)
Doubler circuit
S8 (OT12)
61
S7 (OT11)
60
S6 (OT10)
C2
VEE
CMOS I/O ports (4)
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TC9329AFAG/AFCG
Block Diagram
Peripheral
CPU
P1-3
XOUT
X’tal
OSC
XIN
CRosc
Port1
P1-0
PSC
R/W Buf.
G-Reg.
P2-3 (PSC)
Vreg (1.5 V)
Vreg
Port2
P2-0
ALU
Phase
Comp.
DO2 (OT)
P4-3
Port4
P4-0 (BUZR)
RAM
(4 × 256 word)
BUZR
PLL
OSCin
IFin1 (INTR1)
IFin2 (IN2)
CRosc
Data Reg
(16 bit)
IF
Counter
CR
OSC
Up/Down
Counter
MUTE
Timer
ROM
Interrupt
Cont.
Instruction
Decoder
(16 × 4096 Step)
MUTE
P8-3 (S18)
Port9
P9-0 (S15)
INTR2
P8-3 (S14)
Port8
P8-0 (S11)
Serial
Interface
LCD
Driver
P3-3 (SCK)
P3-2 (SO)
VLCD
Port3
P3-1 (SI)
HOLD (INTR2)
Program
Counter
P3-0
TEST
Reset
VLCD
VDD
Stack Reg.
(8 Level)
Vreg
VDB
RESET
VDD
GND
VDB
A/D
Conv.
Doubler
C1
C2
VEE
(1.5 V)
P5-3 (ADin4)
P5-2 (ADin3)
Port5
VEE
C3
P5-1 (ADin2)
VLCD
LCD Driver/Output Port
P5-0 (ADin1)
Doubler
C4
3
S9 (OT13)
S10 (OT14)
S8 (OT12)
S7 (OT11)
S6 (OT10)
S2 (OT6)
S1 (OT5)
COM4
VLCD
(OT4)
COM3 (OT3)
COM2 (OT2)
COM1 (OT1)
VLCD
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TC9329AFAG/AFCG
Description of Pin Function
Pin No.
Symbol
1
COM1/OT1
2
COM2/OT2
3
COM3/OT3
4
COM4/OT4
S1/OT5~
5~14
S10/OT14
Pin Name
Function and Operation
Remarks
Outputs common signals to LCD
panels. Through a matrix with pins S1
to S18, a maximum of 72 segments can
be displayed.
LCD common
output/Output port
VLCD
Three levels, VLCD, VEE (1/2 VLCD ),
and GND, are output at 62.5 Hz every 2
ms.
VEE
VEE is output after system reset and
CLOCK STOP are released, and a
common signal is output after the DISP
OFF bit is set to “0”.
These pins can be programmed as
output ports (Note 1).
LCD segment
output/Output port
Segment signal output terminals for
LCD panel. Together with COM1 to
COM4, a matrix is formed that can
display a maximum of 72 segments.
VEE is output after system reset and
CLOCK STOP are released, and a
common signal is output after the DISP
OFF bit is set to “0”.
VLCD
All pins from S1 to S10 can be
programmed as output ports (Note 1),
and all pins from S11 to S18 as I/O
ports, in units of pins.
When the pins function as output ports,
VLCD pin potential and GND potential
are output to them. When the pins
function as I/O ports, drain output is
N-ch open. Because power is supplied
from VLCD for the I/O ports, up to VLCD
voltage (3 V) can be applied.
P8-0/S13~
15~22
P9-3/S18
LCD segment
An instruction increments the data ports
output/ I/O port 8, 9 (OT1 to OT14) by 1 every time data are
accessed. Therefore the ports can be
used for external memory address
signals, facilitating data access.
VLCD
VDD
Input
instruction
Note: After system reset, the output
port pins are set to LCD output,
the I/O port pins to I/O port input.
VDD
The input and output of these 4-bit I/O
ports can be programmed in 1-bit units.
23~26
P1-0~P1-3
I/O port 1
These pins can be programmed to be
pulled up or down. Thus, they can be
used as key input pins.
By altering the input of I/O ports set to
input, the CLOCK STOP mode or the
WAIT mode can be released, and the
MUTE bit of the MUTE pin can be set to
“1”.
VDD
RIN1
VDD
Note 1: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore
disconnect the voltage boosting capacitor and connect the VLCD pin to the VDD pin.
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TC9329AFAG/AFCG
Pin No.
Symbol
50~52
P2-0~P2-2
53
P2-3/PSC
Pin Name
I/O port 2
I/O port 2
/Prescaler
/PSC output
Function and Operation
Remarks
VLCD
The input and output of these 4-bit I/O
ports can be programmed in 1-bit units.
The P2-3 pin is also used as a PLL
prescaler PSC signal output pin. A PLL
can be configured using an external
prescaler. In such a case, set the pin to
I/O port output.
VDD
Input
instruction
4-bit I/O ports, allowing input and output
to be programmed in 1-bit units. The
I/O ports are N-ch open drain.
Up to 3.6 V can be input. Even at low
voltage, N-ch high output current (2 mA
typ.) can be obtained.
These pins also function as serial
interface circuit (SIO) input/output pins.
P3-0
P3-1/SI
42~45
I/O port 3
/Serial data input
P3-2/SO
/Serial data output
P3-3/SCK
/Serial clock I/O
There are two types of serial interface
circuit: SIO1 allows 4 or 8-bit
input/output and SIO2 allows 26-bit
serial data input. SIO1 inputs data of SI
pin serially with the edge of the clock of
SCK pin, and outputs it to SO pin.
Input
instruction
(P3-0)
Internal (SCK = 37.5 kHz), external, or
rising/falling shift can be selected as the
clock (SCK) for serial operation. The
SO pin can be switched to serial input
(SI), facilitating LSI control and
communication between controllers.
Setting “1” in the SIO2 bit sets the SCK
pin to the SIO2 clock input and the
SI/SO pin to SIO2 data input. A
synchronization circuit is built-in for
SIO2.
When SIO interrupts are enabled, an
interrupt is generated after SIO
execution or by SIO2 operating clock
input and the program jumps to address
4.
All SIO inputs use built-in Schmitt
circuits.
Input instruction + SIOon
(P3-1~P3-3)
SIO and all controls are programmable.
4-bit I/O ports, allowing input and output
to be programmed in 1-bit units.
28
29~31
P4-0/BUZR
P4-1~P4-3
I/O port 4
/Buzzer output
I/O port 4
VDD
The P4-0 pin is also used for buzzer
output.
The buzzer output can select 8 kinds of
0.625 to 3-kHz frequencies with 4
modes: continuous output, single-shot
output, 10 Hz intermittent output, and
10 Hz intermittent at 1 Hz intervals
output.
Input
instruction
SIO, buzzer, and all associated controls
can be programmed.
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TC9329AFAG/AFCG
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
4-bit I/O ports, allowing input and output
to be programmed in 1-bit units.
Pins P5-0 to P5-3 can also be used for
analog input to the built-in 6 bit,
4-channel AD converter.
46~49
P5-0/ADin1~
P5-3/ADin4
The conversion time of the built-in AD
converter using the successive
I/O port 5
comparison method is 280 µs. The
/AD analog voltage necessary pin can be programmed to
input
AD analog input in 1-bit units. Up to the
doubled voltage VDB (VDD × 2) can be
input as the AD input voltage.
I/O ports are N-ch open drain output.
Up to the VDB voltage can be applied to
the AD input pins.
To AD converter
VDD
Input
instruction
The AD converter and all associated
controls are performed via sortware.
1-bit output port, normally used for
muting control signal output.
32
MUTE
Muting output port
VDD
This pin can set the internal MUTE bit
to “1” according to change in the input
of I/O port 1 and HOLD . The MUTE bit
output logic can be changed.
The internal CR oscillator clock can be
output depending on the contents of the
test port.
Input pin used for controlling TEST
mode.
33
TEST
Test mode control
input
VDD
“H” (high) level indicates TEST mode,
while “L” (low) indicates normal
operation.
The pin is normally used at low level or
in NC (no connection) state.
(A pull-down resistor is built in.)
6
RIN2
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TC9329AFAG/AFCG
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
Input pin for request/release hold mode.
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
Hold mode includes CLOCK STOP
mode (stops crystal oscillation) and
WAIT mode (halts CPU). Setting is
implemented with the CKSTP
instruction or the WAIT instruction.
Hold mode control
input
HOLD
34
/INTR2
/PCTRin
/External interrupt
input
/Plus count input
To request Clock Stop mode, either
L-level detection on the HOLD pin or
forced execution can be programmed.
The mode is released by H-level
detection on the HOLD pin or input
change, respectively. Executing the
CKSTP instruction stops the clock
generator and the CPU, resulting in
entry to memory backup state. In
memory backup state, current
dissipation becomes low (1 µA or less)
and the display output/CMOS output
ports automatically become L level and
N-ch open drain output is set toOff.
VDD
Regardless of this input state, Wait
mode is executed in order to lower
power dissipation. Either operation of
the crystal oscillator only or CPU
suspension can be programmed. For
operation of the crystal oscillator only,
all displays are at L level and other pins
are in hold state. For CPU suspension,
the CPU stops and all others retain
their states. Wait mode is released by
changing HOLD input.
The P34 pin is also used for external
interrupt input. When interrupts are
enabled and a 13.3 to 26.7-µA pulse or
longer is input to the pin, interrupt
INTR1/2 is generated and the program
jumps to address 1/2. Input logic or
rising/falling edge can be selected for
each input interrupt.
The internal 8-bit timer clock input can
be selected as input to the pins. When
the count value reaches the specified
value, an interrupt is generated
(address 4).
The pin is also used for input of an 8-bit
pulse counter. Input rising/falling or
upcount/downcount can be selected for
the counter.
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TC9329AFAG/AFCG
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
IF signal input pin for the IF counter to
count the IF signals of the FM and AM
bands and to detect the automatic stop
position.
The input frequency is between 0.3 to
12 MHz. A built-in input amp. and C
coupling allow operation at low-level
input.
35
IFin1/INTR1
36
IFin2/IN2
IF signal 1 input
/External interrupt
input
IF signal 2 input
/Input port
The IF counter is a 20-bit counter with
optional gate times of 1, 4, 16 and 64
ms. 20 bits of data can be readily
stored in memory. In Manual mode,
gate On/Off or CR oscillator clock
frequency count can be performed
using an instruction.
The input pin can be programmed for
use as an input port (IN port). In this
case, the pins are CMOS input. They
can count input clocks using the IF
counter.
RfIN2
VDD
IFin1 also functions as an external
interrupt input pin. When interrupts are
enabled and a 13.3 to 26.7-µA pulse or
longer is input to IFin1, an interrupt is
generated and the program jumps to
address 1. Input logic or rising/falling
edge can be selected for the input
interrupt. The internal 8-bit timer clock
input can be selected as input to the
pin. When the count value reaches the
specified value, an interrupt is
generated (address 4).
Note: When a pin is set to IF input, the
input is at high impedance in PLL
Off mode or if the pins are not
used for input.
Pins to which power is applied.
Normally, VDD = 0.9~1.8 V is applied.
27, 39
VDD
Power-supply pins
37, 57
GND
VDD
In backup state (at execution of the
CKSTP instruction), current dissipation
drops (1 µA or less) and the power
supply voltage can be reduced to 0.75
V.
Note: To operate the power on reset,
the power supply should start up
in 10~100 ms.
8
GND
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TC9329AFAG/AFCG
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
For FM input, mode can be switched
between 1/2 + Pulse Swallow VHF and
FM mode. For AM input, mode can be
switched between Pulse Swallow (HF)
and Direct Dividing (LF) mode.
38
OSCin
local oscillation
signal input
Normally, local oscillation output
(Voltage-Controlled Oscillator: VCO
output) of 80 to 230 MHz is input in
VHF mode; 60 to 130 MHz in FM mode;
1 to 30 MHz in HF mode; 0.5 to 8 MHz
in LF mode.
RfIN1
VDD
A PLL can be configured using an
external prescaler. In such a case, set
the pin to LF, and connect the prescaler
divider output to the OSCin input pin
and the PSC input to the P2-3 (PSC)
output pin.
With an input amp incorporated,
capacitive-coupling, small-amplitude
operation is supported.
Note: The input is at high impedance in
PLL Off mode.
PLL phase comparator output pins.
40
DO/OT
Phase comparator
output/output port
Tristate output. When the program
counter divider output is higher than the
reference frequency, H level is output;
when lower, L level; and when they
match, high impedance. For the phase
comparator power supply, a 1.5-V
constant voltage supply (Vreg pin) is
used. Even if the power supply voltage
drops, a stable PLL can be configured.
Vreg
The DO/OT pin can be programmed to
high impedance or as an output port
(OT).
Note: For tristate output, the H-level
output uses a constant voltage
supply. When H-level output
current is required, Toshiba
recommend using an external
power supply.
Phase comparator constant voltage
supply.
41
Vreg
Phase comparator
constant voltage
supply
When the phase comparator output is
tristate output, a constant voltage
supply of 1.5 V (typ.) is output to the
pin. For this output, connect a
stabilizing capacitor (0.47 µF typ.).
Constant voltage On/Off can be
programmed.
Vreg
Because half the voltage potential can
be switched to AD converter A/D input,
it can be used to detect how much
battery remains.
At PLL operation, the constant voltage
is used for H level phase comparator
output. Thus, when H level output
current is required, Toshiba
recommend using an external power
supply. Externally apply 1.8 to 3.6 V to
the pin.
Input pin for system reset signals.
54
RESET
Reset input
RESET takes place at low level; at
high level, the program starts from
address “0”.
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TC9329AFAG/AFCG
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
Crystal oscillator pins.
55
A reference 75 kHz crystal resonator is
connected to the XIN and XOUT pins.
XOUT
The oscillator stops oscillating during
CKSTP instruction execution.
Crystal oscillator
pin
56
XIN
58
VDB
59
C1
60
C2
61
VEE
62
C3
63
C4
64
VLCD
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.47 µF typ.) is connected.
ROUT
XOUT
RfXT
VDD
XIN
Usually, the clock of a crystal oscillator
is used for the clock for peripheral
equipment. Through programming, the
built-in VCO can be changed to CPU
and CPU only operation can be
accelerated.
Voltage doubler boosting output pins.
The VDB pin doubles the VDD pin
voltage using the voltage doubler
boosting capacitor between C1 and C2.
The doubled voltage is used for the AD
converter and constant voltage circuit
(Vreg, VEE) power supply.
Voltage doubler
boosting output
pins
The VEE pin supplies a constant
voltage of 1.5 V from the VDB voltage.
The voltage is doubled (to 3 V) using
the voltage doubler boosting capacitor
between C3 and C4. The doubled
voltage is then supplied to the VLCD
pin. The VEE potential and the VLCD
potential are used to drive the LCD.
VLCD
Connect a stabilizing capacitor between
the VDB pin and GND (0.1 µF, 10 µF
typ.), and between the VLCD pin and
GND (0.1 µF typ.). Connect a voltage
doubler boosting capacitor (0.1 µF typ.)
between C1 and C2, and between C3
and C4. (Note)
Note: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore
disconnect the voltage boosting capacitor and connect the VLCD pin to the VDD pin.
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TC9329AFAG/AFCG
Description of Operations
○
CPU
The CPU consists of a program counter, a stack register, an ALU, a program memory, a data memory, a
G-register, a data register, a DAL address register, a carry F/F, a judgment circuit, and an interruption
circuit.
1. Program Counter (PC)
The program counter consists of a 14-bit binary up-counter and addresses the program memory (ROM).
The counter is cleared when the system is reset and the programs start from the 0 address.
Under normal conditions, the counter is increased in increments of one whenever an instruction is
executed, but the address specified in the instruction operand is loaded when a JUMP instruction or CALL
instruction is executed.
Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS instructions,
etc.) is executed, and the result of this includes a skip condition, the program counter is increased in
increments of two and the subsequent instruction is skipped. Furthermore, if interruption is received, the
vector address corresponding to each interruption is loaded.
Note: Addresses 0000H-0FFFH are reserved for the program memory. For this reason, access to addresses
outside this range is prohibited.
Contens of Program Counter (PC)
Instruction
PC13 PC12 PC11 PC10
Power on reset
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Operand of instruction (ADDR1)
JUMP ADDR1
JUMP ADDR2
PC9
0
0
0
0
0
0
Operand of instruction (ADDR2)
0
Operand of
instruction (ADDR3)
0
RESET by reset pin
Contents of general
register (r)
DAL (DA)
DAL address register (DA)
(DAL bit = 1)
RN, RNS, RNI
Contents of stack register
At the time of an
interruption reception
Power on reset
Vector address of each interruption
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET by reset pin
Priority
Interruption Factor
Vector Address
1
INTR1 pin
0001H
2
INTR2 pin
0002H
3
Serial inter face
0003H
4
Timer counter
0004H
2. Stack Register
A register consisting of 8 × 14 bits which stores the contents of the program counter +1 (the return
address) when a sub-routine call instruction is executed. The contents of the stack register are loaded into
the program counter when the return instruction (RN, RNS, RNI instruction) is executed.
There are eight stack levels available and nesting occurs with both levels.
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TC9329AFAG/AFCG
3. ALU
ALU is equipped with binary 4-bit parallel add/subtract functions, logical operation, comparison and
multiple bit judgment functions. This CPU is not equipped with an accumulator, and all operations are
handled directly within the data memory.
4. Program Memory (ROM)
The program memory consists of 16 bits × 4096 steps and is used for storing programs. The usable
address range consists of 4096 steps between address 0000H ~ 0FFFH.
The program memory is divided into 4096 separate steps and consists of page 0 ~ 3. The JUMP
instruction and CALL instruction can be freely used throughout all 4096 steps.
In case of setting DAL bit (it arranges on I/O map) “0” (DAL ADDR3, (r) command), the program memory
address 0000H ~ 03FFH (page 0) are used as data area and setting DAL bit “1” (DAL (DA) command), the
program memory address 0000H to 0FFFH (page 0 ~ 3) are used as data area. The 16 bit contents of this
can be loaded into the data register by executing the DAL instruction.
Note: An address outside of the program lop must be set when establishing a data area within the program
memory.
ROM
16 bit
0800H
Page 2
*2
0C00H
Page 3
0001H
CALL instruction specification area
Page 1
DAL instruction area
0400H
*1
0002H
0003H
0004H
JUMP address at initialization
Interruption
vector address
0000H
Page 0
(1 k step)
JUMP instruction specification area
0000H
INTR1
INTR2
Serial interface
8 bit timer
0FFFH
*1:
DAL bit = DAL access area at setting “0”
*2:
DAL bit = DAL access area at setting “1”
Note: DAL bit is arranged on I/O map.
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TC9329AFAG/AFCG
5. Data Memory (RAM)
The data memory consists of 4 bit × 256 words and is used for storing data. These 256 words are
expressed in row addresses (4 bits) and column addresses (4 bits). 192 words (row address = address 004H
~ 00FH) within the data memory are addressed indirectly by the G-register. Owing to this, it is necessary
to specify the row address with the G-register before the data in this area can be processed.
The address 00H ~ 0FH within the data memory are known as general registers, and these can be used
simply by specifying the relevant column address (4 bit). These sixteen general registers can be used for
operations and transfers with the data memory, and may also be used as normal data memories.
Note: The column address (4 bit) that specifies the general register is the register number of the general
register.
Note: All row address (addresses 0H ~ FH) can be specified indirectly with the G-register.
Note: The data memory is 256 words and 2 bits of the 6-bit higher ranks of G-register row address are used “0”
(00H ~ 0FH address).
Note: By using LD and ST instructionss, it can be addressed directly in 256 words (row address = 00H ~ 0FH)
in a data memory.
COLMUN ADDRESS: DC
ROW ADDRESS: DR
0
*
1 2
3
4
5
6 7
8 9 A B C D E F
General register
(one from among addresses
00H ~ 0fH)
0
1
2
3
4
5
6
7
Indirect specification of
row addresses (4H ~
FH) with the G-register
8
9
A
* The indirect
specification of row
address = 0H ~ FH
is also possible
B
LD and ST instructions allow low
addresses (0H ~ FH) to be
directly
C
D
E
F
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TC9329AFAG/AFCG
6. G-Register (G-REG)
The G-register is a 4 bits register used for addressing the row addresses (DR = 4H ~ FH addresses) of the
data memory’s 192 words.
The contents of this register are validated when the MVGD instruction or MVGS instruction are
executed, and not affected through the execution of any other instructions. This register is used as one of
the ports, and the contents are set when the OUT1 instruction from among the I/O instructions is executed.
The 6-bit contents can be directly set by execution of STIG instruction.
(→Refer to the Register Port section.)
7. Data Register (DATA REG)
The data register consists of 1 16 bits and stores 16 bits of optional address data. This register is used
as one of the ports, and the contents are loaded into the data memory in units of 4 bits when an IN1
instruction from among the I/O instructions is executed. ( Refer to the Register Port section.)
Moreover, this register supports writing from the data memory and is used for evacuation/return
processing of the data at the time of interruption.
8. DAL Address Register (DA)
The data register consists of 1 × 14 bits.
If a DAL instruction is executed when the DAL bit is set to “1”, 16 bits of the data of the free addresses in
the program memory specified by this DAL address register are loaded. By the setting (DATA) → DA bit to
“1”, the contents of data register (DATA REG) can be transmitted to DAL address register (DA).
This register and a control bit are treated as a port, and are accessed by IN3/OUT3 instruction of an
input-and-output instruction. (→ Refer to section in Register port item)
9. Carry F/F (Ca Flag)
This is set when either Carry or Borrow are issued in the result of calculation instruction execution and
is reset if neither of these are issued.
The contents of carry F/F can only be amended through the execution addition, subtraction, CLT, CLTC
instructions and are not affected by the execution of any other instruction.
The carry F/F can be accessed by the IN1/OUT1 instruction of an input-and-output instruction. For this
reason, an input-and-output command performs the evacuation and the return at the time of interruption
between data memories. (→ Refer to the Register Port section.)
10. Judgment Circuit (J)
This circuit judges the skip conditions when an instruction equipped with the skip function is executed.
The program counter is increased in increments of two when the skip conditions are satisfied, and the
subsequent instruction is skipped.
There are 15 instructions equipped with a wide variety of skip functions available. (→ Refer to the items
marked with a “*” symbol in the Table Instruction Functions and Operational Instructions)
11. Interruption Circuit
An interruption circuit branches to each vector address by the demand from circumference hardware,
and performs each interruption processing. (→Refer to the interruption function section.)
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TC9329AFAG/AFCG
12. Instruction Set Table
A total of 57 instruction sets are available, and all of these are single-word instructions.
These instructions are expressed with 6-bit instruction codes.
High order 2 bit
Low order 4 bit
00
01
10
11
0
1
2
3
0000
0
AI
M, I
TMTR
r, M
SLTI
M, I
0001
1
AIC
M, I
TMFR
r, M
SGEI
M, I
0010
2
SI
M, I
SEQ
r, M
SEQI
M, I
0011
3
SIB
M, I
SNE
r, M
SNEI
M, I
0100
4
ORIM
M, I
TMTN
M, N
0101
5
ANIM
M, I
TMT
M, N
0110
6
XORIM
M, I
TMFN
M, N
0111
7
MVIM
M, I
TMF
M, N
1000
8
AD
r, M
IN1
M, C
1001
9
AC
r, M
IN2
M, C
IN3
M, C
LD
ST
1010
r, M*
JUMP ADDR1
M*, r
A
SU
r, M
1011
B
SB
r, M
OUT1
M, C
1100
C
ORR
r, M
CLT
r, M
OUT2
M, C
1101
D
ANDR
r, M
CLTC
r, M
OUT3
M, C
1110
E
XORR
r, M
MVGD
r, M
DAL
ADDR3, r
SHRC
M
RORC
M
STIG
I*
CAL ADDR2
1111
F
MVSR
M1, M2
MVGS
M, r
SKP, SKPN
RN, RNS
WAIT
P
CKSTP
XCH
M
DI, EI, RNI
NOOP
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2006-03-02
TC9329AFAG/AFCG
13. Table of Instruction Functions and Operational Instructions
(Description of the symbols used in the table)
M
: Data memory address.
Generally one of the addresses from among addresses 00H to 3FH in the data memory.
M*
: Data memory address (256 words)
One of the addresses from among addresses 000H to 0FFH in the data memory.
(Effective only at the time of ST and LD instruction execution)
r
: General register
One of the addresses from among addresses 00H to 00FH in the data memory.
PC
: Program Counter (14 bits)
STACK
: Stack register (14 bits)
G
: G-register (6 bits)
DATA
: Data register (16 bits)
I
: Immediate data (4 bits)
I*
: Immediate data (6 bits, effective only at the time of STIG instruction execution)
N
: Bit position (4 bits)
: ALL “0”
C
: Port code No. (4 bits)
CN
: Port code No. (4 bits)
RN
: General register No. (4 bits)
ADDR1
: Program memory address (14 bits)
ADDR2
: Program memory address within page 0 to 3 (12 bits)
ADDR3
: High order 6 bits of the program memory address within page 0.
DA
: DAL address register
(14 bits, effective only DAL instruction at the time of DAL bits is set to “1”)
Ca
: Carry
CY
: Carry flag
P
: Wait condition
b
: Borrow
IN1~IN3
: The ports used during the execution of instructions IN1 to IN3
OUT1~OUT3 : The ports used during the execution of instructions OUT1 to OUT3
()
: Contents of the register or data memory
[]C
: Contents of the port indicating code No. C (4 bits)
[]
: Contents of the data memory indicating the contents of the register or data memory
[]P
: Contents of the program memory (16 bits)
IC
: Instruction code (6 bits)
*
: Commands equipped with the skip function
DC
: Data memory column address (4 bits)
DR
: Data memory row address (2 bits)
DR*
: Data memory row address
(4 bits, effective only at the time of ST and LD instruction execution)
(M) b0~(M) b3 : Bits data of the contents of a data memory (1 bit)
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2006-03-02
TC9329AFAG/AFCG
Comparison Instructions
Subtraction Instructions
Addition Instructions
Instruc
-tion
Group
Mnemonic
Skip
Function
Machine Language (16 bits)
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
000000
DR
DC
I
AI
M, I
Add immediate data
to memory
AIC
M, I
Add immediate data
M ← (M) + I + ca
to memory with carry
000001
DR
DC
I
AD
r, M
Add memory to
general register
r ← (r) + (M)
001000
DR
DC
RN
AC
r, M
Add memory to
general register with
carry
r ← (r) + (M) + ca
001001
DR
DC
RN
SI
M, I
Subtract immediate
data from memory
M ← (M) − I
000010
DR
DC
I
SIB
M, I
Subtract immediate
data from memory
with borrow
M ← (M) − I − b
000011
DR
DC
I
SU
r, M
Subtract memory
from general register
r ← (r) − (M)
001010
DR
DC
RN
SB
r, M
Subtract memory
from general register
with borrow
r ← (r) − (M) − b
001011
DR
DC
RN
SLTI
M, I
*
Skip if memory is
less than immediate
data
Skip if (M) < I
110000
DR
DC
I
SGEI
M, I
*
Skip if memory is
greater than or equal Skip if (M) >
=I
to immediate data
110001
DR
DC
I
SEQI
M, I
*
Skip if memory is
equal to immediate
data
Skip if (M) = I
110010
DR
DC
I
SNEI
M, I
*
Skip if memory is not
equal to immediate
Skip if (M) ≠ I
data
110011
DR
DC
I
SEQ
r, M
*
Skip if general
register is equal to
memory
Skip if (r) = (M)
010010
DR
DC
RN
SNE
r, M
*
Skip if general
register is not equal
to memory
Skip if (r) ≠ (M)
010011
DR
DC
RN
CLT
r, M
Set carry flag if
general register is
(CY) ← 1 if (r) < (M) or
less than memory, or (CY) ← 0 if (r) >
= (M)
reset if not
011100
DR
DC
RN
r, M
Set carry flag if
general register is
less than memory
with carry or reset if
not
011101
DR
DC
RN
CLTC
M ← (M) + I
(CY) ← 1 if (r) < (M) + (ca)
or
(CY) ← 0 if (r) >
= (M) + (Ca)
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TC9329AFAG/AFCG
Logical Poeration Instructions
I/O Instructions
Transfer Instructions
Instruc
-tion
Group
Mnemonic
Skip
Function
Machine Language (16 bits)
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
LD
r, M*
Load memory to
general register
r ← (M*)
0101
DR*
(4 bits)
DC
RN
ST
M*, r
Store memory to
general register
M* ← (r)
0110
DR*
(4 bits)
DC
RN
MVSR M1, M2
Move memory to
(DR, DC1) ← (DR, DC2)
memory in same row
001111
DR
DC1
DC2
MVIM
Move immediate data
M←I
to memory
000111
DR
DC
I
MVGD r, M
Move memory to
destination memory
[(G), (r)] ← (M)
referring to G-register
and general register
011110
DR
DC
RN
MVGS M, r
Move source
memory referring to
G-register and
(M) ← [(G), (r)]
general register to
memory
(Note)
011111
DR
DC
RN
M, I
STIG
I*
Move immediate data
G ← I*
to G-register
111111
IN1
M, C
Input IN1 port data to
M ← [IN1] C
memory
111000
DR
DC
CN
OUT1
M, C
Output contents of
memory to OUT1
port
111011
DR
DC
CN
IN2
M, C
Input IN2 port data to
M ← [IN2] C
memory
111001
DR
DC
CN
OUT2
M, C
Output contents of
memory to OUT2
port
111100
DR
DC
CN
IN3
M, C
Input IN3 port data to
M ← [IN3] C
memory
111010
DR
DC
CN
OUT3
M, C
Output contents of
memory to OUT3
port
[OUT3] C ← (M)
111101
DR
DC
CN
ORR
r, M
Logical OR of
general register and
memory
r ← (r) ∨ (M)
001100
DR
DC
RN
ANDR
r, M
Logical AND of
general register and
memory
r ← (r) ∧ (M)
001101
DR
DC
RN
ORIM
M, I
Logical OR of
memory and
immediate data
M ← (M) ∨ I
000100
DR
DC
I
ANIM
M, I
Logical AND of
memory and
immediate data
M ← (M) ∧ I
000101
DR
DC
I
XORIM M, I
Logical exclusive OR
of memory and
M ← (M) ∀ I
immediate data
000110
DR
DC
I
XORR
Logical exclusive OR
of general register
r ← (r) ∀ (M)
and memory
001110
DR
DC
RN
r, M
[OUT1] C ← (M)
[OUT2] C ← (M)
I*
0010
Note: The execution time for the MVGS instruction is two machine cycles.
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2006-03-02
TC9329AFAG/AFCG
Bit Judgement Instruction
Instruc
-tion
Group
Mnemonic
SUB = Routne
Instructions
JUMP Instructions
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
TMTR
r, M
*
Test general register
bits by memory bits,
then skip if all bits
specified are true
Skip if r [N (M)] = all “1”
010000
DR
DC
RN
TMFR
r, M
*
Test general register
bits by memory bits,
then skip if all bits
specified are false
Skip if r [N (M)] = all “0”
010001
DR
DC
RN
TMT
M, N
*
Test memory bits,
then skip if all bits
specified are true
Skip if M (N) = all “1”
110101
DR
DC
N
TMF
M, N
*
Test memory bits,
then not skip if all bits Skip if M (N) = all “0”
specified are false
110111
DR
DC
N
TMTN
M, N
*
Test memory bits,
then not skip if all bits Skip if M (N) = not all “1”
specified are true
110100
DR
DC
N
TMFN
M, N
*
Test memory bits,
then not skip if all bits Skip if M (N) = not all “0”
specified are false
110110
DR
DC
N
SKP
*
Skip if carry flag is
true
Skip if (CY) = 1
111111
00
⎯
0011
SKPN
*
Skip if carry flag is
false
Skip if (CY) = 0
111111
01
⎯
0011
Call subroutine
STACK ← (PC) + 1 and
PC ← ADDR2
1011
RN
Return to main
routine
PC ← (STACK)
111111
10
⎯
0011
RNS
Return to main
routine and skip
unconditionally
PC ← (STACK) and skip
111111
11
⎯
0011
Jump to address
specified
PC ← ADDR1
10
ADDR1 (14 bits)
CAL
JUMP
ADDR2
ADDR1
ADDR2 (12 bits)
Reset IMF
(Note) IMF ← 0
111111
00
⎯
0111
EI
Set IMF
(Note) IMF ← 1
111111
01
⎯
0111
RNI
Return to main
PC ← (STACK)
routine and set IMF
(Note) IMF ← 1
111111
11
⎯
0111
DI
Intruption
Instruction
Machine Language (16 bits)
Skip
Function
Note: The IMF bit is an interruption master permission flag and is arranged on I/O map.
(→ Refer to the interruption function section.)
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2006-03-02
TC9329AFAG/AFCG
Instruc
-tion
Group
Mnemonic
Other Instructions
SHRC
M
Skip
Function
Function
Description
Shift memory bits to
right direction with
carry
RORC M
Rotate memory bits
to right direction with
carry
XCH
Exchange memory
bits mutually
DAL
M
ADDR3, r
WAIT
P
Operation
Description
A
(2 bits)
B
(4 bits)
C
(4 bits)
0 → (M) b3 → (M) b2 →
(M) b1 → (M) b0→ (CY)
111111
DR
DC
0000
(M) b3 → (M) b2 →
(M) b1→ (M) b0 →
(CY)
111111
DR
DC
0001
111111
DR
DC
0110
(M) b3 ↔ (M) b0,
(M) b2 ↔ (M) b1
IF DAL bit = 0 then
load program in page
0 to DATA register
IF DAL bit = 1 then
DATA ← [ADDR3 + (r)] p
load program
in page 0
memory referring to
DAL address register
to DATA register
(Note)
At P = “0” H, the
condition is CPU
waiting
(soft wait mode)
At P = “1” H, expect
for clock generator,
all function is waiting
(hard wait mode)
CKSTP
Clock generator stop
NOOP
No operation
Machine Language (16 bits)
IC
(6 bits)
111110
ADDR3 (6 bits)
RN
Wait at condition P
111111
P
⎯
0100
Stop clock generator to
MODE condition
111111
⎯
⎯
0101
111111
⎯
⎯
1111
⎯
Note: The four low order bits of the program memory’s 10-bit address specified with the DAL instruction are
addressed indirectly with the contents of the general registerer.
Note: The excution time for the DALinstruction is two machine cycles.
Note: DALbitsand DAL address register (DA) are arrenged on the I/O map.
(→ Refer to the Register Port section)
Note: When “1” is set to DAL bit and the DAL instruction is executed, all the operand part becomes invalid and the
reference addresses are used for the DAL address register.
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2006-03-02
TC9329AFAG/AFCG
I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
φL1
φL2
φL3
φK1
φK2
OUT1
OUT2
OUT3
IN1
IN2
I/O
Code
Y1
Y2
Y4
Y8
Y1
Y2
Power control
0
HF
Y4
Y8
Y1
Y2
I/O port 1 pull-down
Y4
Y8
Y1
I/O port 1
Y2
Y4
Y8
PW1
IN3
Y2
IF monitor
Y4
Y8
Y1
Y2
A/D data
FM
PW0
Y1
φK3
Y4
Y8
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
I/O port 1
0
PD0
K1
Programmable counter 1
PD2
PD3
-0
-1
A/D control
-2
-3
BUSY
MANUAL
I/O port 2
OVER
AD0
AD1
IF data 1
AD2
AD3
-0
-1
A/D data
I/O port 2
1
P0
P1
P2
P16
AD SEL0
Programmable counter 2
AD SEL1
AD SEL2
STA
-0
-1
Serial interface control 1
-2
-3
F0
F1
I/O port 3
F2
F3
AD4
AD5
BUSY
0
-0
-1
IF data 2
I/O port 3
2
P4
P5
P6
P7
SCK - INV
edge
Programmable counter 3
SCK - I/O
SIO-ON
-0
-1
Serial interface control 2
-2
-3
F4
F5
I/O port 4
F6
F7
-0
IF data 3
-1
Serial interface monitor
I/O port 4
3
0
P8
P9
P10
P11
SO - I/ O
STA
Programmable counter 4
8/ 4 bit
SIO Select
-0
-1
Serial interface output data 1
-2
-3
F8
F9
I/O port 5
F10
F11
BUSY
IF data 4
COUNT
SIO F/F
-0
-1
Serial interface input data 1
I/O port 5
4
P12
P13
P14
5
R0
P15
SO0
SO1
Programmable
counter
Reference select
R1
R2
P16
IF counter control 1
SO4
SO5
Timer reset
6
IF1/2
PW
IF1/INTR1
IF2/IN2
2 Hz F/F
IF counter control 2
MANIAL
G0
G1
POL1
(INTR1)
MUTE control
8
I/O-1
9
RESET
POL
HOLD
EF1
(INTR1)
DO2 control
PN
M0
-0
M1
Clock
SO6
SO7
F13
FE2
(INTR2)
ILR1
(INTR1)
ILR2
(INTR2)
ILR3
(SIO)
BEN
ID0
POL
ID4
ID1
SI0
F17
SI1
*
F18
F19
SI4
2 Hz F/F
-0
-1
-2
INTR1
ILR4
(Timer)
ID2
INTR2
0
SI3
SI5
SI6
SI7
Interrupt
master flag
10 Hz
100 Hz
0
0
0
0
-0
-1
-0
-1
I/O port 8
IMF
-3
I/O port 9
FE4
(Timer)
SI2
Serial interface input data 2
I/O port 8
IE
FE3
(SIO)
F15
#4
HOLD
POL2
(INTR2)
F14
Timer
MUTE control
Interrupt permission flag
I/O port 9
MUTE
-0
-1
-2
HOLD PLL
off control
IF counter
Split
Prescaller
IN
Timer counter Interrupt detection data1
BUZZR output control 2
F12
F16
DAL
BF2
-3
Test
port 2
CKSTP
mode
A
BF1
-2
IF data 5
Interrupt latch reset
BUZZR output control 1
BF0
-1
Interrupt permission flag
MUTE
UNLOCK
Detection
SO3
Interrupt control
7
STA/ STP
SO2
Serial interface output data 2
ID3
Timer counter Interrupt detection data2
(DATA)
→ DA
OT Count
Up
-3
I/O
POL
Unlock detection
HOLD
EF1
Input port
EF2
EF3
EF4
-0
-1
-2
-3
DAL
0
0
0
DA0
DA1
Interrupt latch
PSC ENA
F/F
ENA
(INTR1)
IN2
IL1
IL2
IL3
IL4
Timer counter data 1
port 1
Pull-up
CT0
DAL address
CT1
CT2
CT3
Timer counter data 2
DAL address
B
BM0
C
CA Flag
BM1
BUZR ON
*
*
ID5
ID6
ID7
DA0
Timer counter control
*
DA1
DA2
DA3
CT4
CK1
G register 1
CT6
CT7
Data register 1
GT
CR
d0
Data select
d1
d2
DA2
DA3
Data register 1
CA flag
CK0
CT5
0
0
0
d3
d0
Data register 2
G register 1
Data select
d1
d2
d3
Data register 2
D
G0
G1
G2
G3
G register 2
SEL1
SEL2
SEL4
SEL8
d4
Segment data 1/ General purpose output data
d5
d6
d7
G0
Data register 3
G1
G2
G3
S1
S2
S3
S4
d4
G register 2
d5
d6
d7
Data register 3
E
G4
*
G5
*
COM1/OT
Test port 1
COM2/OT
COM3/OT
COM4/OT
d8
Segment data2/ Segment IO control
d9
d10
d11
G4
G5
0
0
d8
Data register 4
d9
d10
d11
Data register 4
F
#0
#1
#2
#3
COM1
COM2
COM3
COM4
d12
d13
d14
d15
d12
d13
d14
d15
Refer to next page
21
2006-03-02
TC9329AFAG/AFCG
φKL2D
I/O
Data Select
S1
S2
S4
S8
φL2D
Y1
φL2E
φL2F
φL3B
OUT2
OUT2
OUT3
Y2
Y4
Y8
Y1
Y2
S1/OT1~OT4
0
COM1
/OT1
COM2
/OT2
COM3
/OT3
COM1
/OT5
COM2
/OT6
COM3
/OT7
COM4
/OT4
COM1
COM2
COM1
/OT9
COM2
/OT10
COM3
/OT11
COM4
/OT8
COM1
COM1
/OT13
COM2
/OT14
COM3
COM4
DA0
COM1
COM4
DA4
DA5
COM4
COM1
COM3
COM2
Y1
DA2
DA6
COM4
DA8
DA9
DA10
DA3
DA0
COM3
COM4
DA12
*
DA13
Y4
Y8
DA1
DA2
DA3
DAL address 2
DA7
DA4
DA5
DA6
DA7
DAL address 3
DA11
DA8
DAL address 4
S17
Y2
DAL address 1
DAL address 3
S16
S5
Y8
DAL address 2
COM3
COM2
Y4
DA1
S15
COM4
/OT12
IN3
Y2
DAL address 1
COM3
COM2
S4/OT13~OT14
3
Y1
S14
S3/OT9~OT12
2
Y8
S13
S2/OT5~OT8
1
Y4
φK3B
DA9
DA10
DA11
DAL address 4
*
DA12
Pulse counter control
DA13
0
0
Pulse counter data
4
COM1
COM2
COM3
COM4
COM1
COM2
S6
COM3
COM4
COM2
COM3
COM4
COM1
COM2
COM3
COM4
CTR
RESET
OVER
RESET
Segment/IO select
S7
*
POL
*
PC0
Pulse counter control
5
COM1
DOWN
S18
*
PC1
PC2
PC3
Pulse counter data
*
PC4
OSC control
PC5
PC6
PC7
Pulse counter data
6
COM1
COM2
COM3
COM4
S11
S8
S12
S13
S14
IFin
CPU Select
Segment/IO select
OSC on
Freq Select
OVER
OSC data
0
0
0
SIO2 decode data
7
COM1
COM2
COM3
COM4
S15
S16
S9
S17
S18
OSC0
-3
SIO2
data
select
I/O control 1
8
COM1
COM2
COM3
COM4
-0
-1
S10
-2
OSC1
OSC2
OSC3
DEC0
DEC1
DEC2
DEC3
SIO2 information data 1
*
INF0
I/O control 2
INF1
INF2
INF3
SIO2 information data 2
9
COM1
COM2
COM3
COM4
-0
-1
S11
-2
-3
INF4
I/O control 4
A
Vreg ON
COM1
COM2
COM3
COM4
-0
-1
-2
-3
*
*
INF5
INF6
INF7
SIO2 information data 3
*
INF8
S12
INF9
INF110
INF11
SIO2 information data 4
B
COM1
COM2
COM3
COM4
INF12
0: Offset data
1: Check data
C
INF13
INF14
INF15
SIO2 offset/Check data 1
OFS0
/CHK0
OFS1
/CHK1
OFS2
/CHK2
OFS3
/CHK3
SIO2 offset/Check data 2
D
OFS4
/CHK4
OFS5
/CHK5
OFS6
/CHK6
OFS7
/CHK7
SIO2 offset/Check data 3
E
OFS8
/CHK8
LCD control
LCD OFF
22
0
0
*
F
DISP OFF
OFS9
/CHK9
OTB-UP
2006-03-02
TC9329AFAG/AFCG
○
I/O map
All of the ports within the device are expressed with a matrix of six I/O instructions (OUT 1 ~ 3
instructions and IN 1 ~ 3 instructions) and a 4-bit code number.
The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in
the execution of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port
code numbers indicated on the vertical axis. The G-register, data register and DAL bits are also used as
ports.
The OUT1 ~ 3 instructions are specified as output ports and the IN 1 ~ 3 instructions are specified as input
ports.
Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device.
The contents of other ports and data memories are not affected when data is output to a non-existent
output port with the execution of the output instruction. The data loaded from data memories when a
non-existent input port has been specified with the execution of an input instruction becomes “1”.
Note: The outout ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports
assume the don’t care status.
Note: The Y1 contents of the ports expressed in 4 bits correspond to the data memory’s low order bits and the
Y8 contents correspond to the high order bits.
The ports specified with the six I/O instructions and code No. C are coded in the following manner:
φ [K/L]
m n
(o)
Contents of the selection port (indirectly specified data, 0-F [HEX])
I/O instruction’s operand CN (0~F [HEX])
The six I/O instructions are coded with the digits 1 to 3
I/O Instruction
OUT1
OUT2
OUT3
IN1
IN2
IN3
m
1
2
3
1
2
3
Indicates the input/output port
K: Input port (IN1~IN3 instruction)
L: Output port (OUT1~OUT3 instruciton)
(Example) The setting for the G-register is allocated to code “D” and “E” in the OUT1 instruction.
The encoded expression at this time becomes “φL1D”and “φL1E”.
23
2006-03-02
TC9329AFAG/AFCG
○
Clock Generator
The clock generator generates the standard clock used as the standard of the system clock supplied to a
core-based CPU and circumference hardware.
Through the program, it is possible to switch between an external crystal oscillation circuit and the
built-in CR oscillation circuit as the CPU operation clock.
1. Crystal Oscillation Circuit
75 kHz crystal resonator is connected to the device’s crystal resonator terminal (XN, XOUT) as indicated
below. During normal operation, the oscillation signal is supplied to the clock generator, the reference
frequency divider and other elements, and generates the various CPU timing signals and reference
frequency.
(XOUT)
(XIN)
(GND)
55
56
57
54
R
CO
X'tal
CI
X’tal = 75 kHz
Note: It is necessary to use a crystal resonator with a low CI value and favorable start-up characteristics.
Be sure to adjust and set the external resistance and capacitor constant to the crystal resonator actually
used.
2. CR VCO
Through the use of the built-in CR VCO, it is possible to raise the CPU processing speed. This will be
utilized for high-speed processing in the required system. The OSCon bit controls the ON/OFF operation of
the CR oscillation circuit; and if this bit is set to “1”, the CR VCO starts operating.
If the setting of the CPU Select bits is “0”, the CPU operates on the 75 kHz for the crystal oscillator clock;
if the setting is “1”, the CPU operates on the CR VCO clock. The oscillation frequency of CR VCO (fCR) is 1
MHz (typ.); and a clock that divides this frequency by 1/2 or 1/4 can be used as the CPU operation clock.
The CR VCO frequency serves as a system that can control the resistance of the CR VCO through the
program so that factors, such as power supply voltage and the variations in the built-in capacitor and
resistance can be changed. For this reason, it is possible to calculate the CR oscillation frequency using the
IF counter.
If used for the CPU clock, the frequency of the CR VCO is changed to the CPU operation clock after the
CR VCO resistance is controlled and adjusted to the set-up frequency and the CR oscillation frequency is
calculated using the IF counter. Moreover, the frequency changes with the change in power supply voltage
from −15% to +10% of the set value, VDD = 1.5 V (i.e., from VDD = 1.1 V to VDD = 1.8 V). If a setting
frequency with an accuracy greater than this range is required, be sure always to adjust the CR VCO
frequency using the IF counter. The frequency setting range of CR VCO can be freely set up in the range
0.8 to 1.2 MHz.
The resistance of the CR VCO, which has a standard value of 36 kΩ (1 MHz), can be programmed to 16
levels, from 20 kΩ to 50 kΩ (in 2 kΩ steps) and the value set using the data of 3 bits of OSC0-OSC3. The
Freq Select bit sets the division value of the CR oscillation frequency. The frequency is fCR/2 if this bit is
set to “0”, and fCR/4 if the bit is set to “1”. When the frequency is set to fCR = 1 MHz, the instruction
executing time is compared with the 40 µs for when the crystal oscillator clock is used. The instruction
execution time is accelerated to 3/500 kHz = 6 µs for 1/2 division mode, and to 3/250 kHz = 12 µs for 1/4
division mode. Although the processing speed of the CPU is accelerated, other timing functions (such as
that for the Timer, etc.) operate on the crystal oscillation frequency.
The Ifin bit is a control bit for changing the CR oscillation frequency clock to the IF counter. If “0” is set,
the IF counter starts calculating the IF (etc.); if “1” is set, the CR VCO frequency can be selected as the
clock input of the IF counter. To calculate the CR VCO frequency, it is necessary to set the Prescaler IN bit
to “1”. (→ Refer to IF counter item.)
Moreover, the CR oscillation frequency clock can be output from the MUTE terminal, and used for
external IC clocks and monitoring of the CR oscillation clock monitor. If the Test port 1 (φL1F) is set to
“5H”, the CR VCO clock outputs from MUTE terminal.
The setup and control of the frequency of the CR VCO is set using an OUT3 instruction for which [CN =
6~7H] has been specified in the operand
24
2006-03-02
TC9329AFAG/AFCG
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Y1
φL3B
Y2
Y4
Y8
OSC control
6
IFin
CPU
Freq
select OSC on select
0: fCR/2
1: fCR/4
Change of CR oscillation
dividing frequency
Y1
φL3B
Y2
Y4
Control for CR VCO operation .....
0: CR VCO stop
1: CR VCO operation
Selection of CPU clock ................
0: Used for crystal resonator frequency clock
1: Used for inside oscillation frequency clock
Connection control to IF counter
of CR oscillation clock
0: IF input operation mode
1: Internal oscillate frequency
calculation mode
Y8
OSC data
7
OSC0 OSC1 OSC2 OSC3
Selection of the internal resistance of CR VCO
OSC0 OSC1 OSC2 OSC3
Resistance (Typ.)
Oscillation Frequency (Typ.)
fCR = 1.8 MHz
0
0
0
0
20 kΩ
↓
↓
↓
↓
(2 kΩ interval)
↓
1
0
0
0
36 kΩ
fCR = 1.0 MHz
↓
↓
↓
↓
(2 kΩ interval)
↓
1
1
1
1
50 kΩ
fCR = 0.64 MHz
Note: The oscillation frequency is the frequency of a standard product and this frequency varies with the power
supply voltage and the product. The frequency range in which settings be made is from 0.8~ 1.2 MHz.
3. Composition of a Clock Generator
(Circumference hardware operation clock)
75 kHz
CPU timing clock
XOUT 55
Crystal
oscillation circuit
CPU Timing generator
XIN 56
CPU Select
OSC0~OSC3
CR oscillation
circuit
1/2
1/2
To IF counter and MUTE terminal
Freq Select
OSCon
25
2006-03-02
TC9329AFAG/AFCG
○
System Reset
The device’s system will be reset when the RESET terminal is subject to the “L” level. The program will
start from 0 address after about 100 ms of stand-by time have elapsed following system reset.
Note: The LCD common output and the segment output will be fixed at their “L” level during system reset and
during the subsequent stand-by period.
Note: It is necessary to initialize through the program any of the internal ports shown in the above-mentioned
I/O map that were not initialized after system reset. The
mark on the I/O map after system reset
indicates a port or bit set to “0” after system reset, while the
mark indicates a port or bit set to “1”. A
port or bit with no mark is unfixed..
φL2F
I/O
φL1
I/O
OUT2
φL2D
Y1
Y2
OUT1
Y4
Code
Y8
Y1
I/O control 1
Y2
Y4
8
5
-0
-1
-2
-3
R0
After system reset, this
port is set to “0”.
After system reset, this
port is set to “1”.
(Note)
R1
Y8
Programmable
counter
Reference select
R2
P16
After system reset, this bit
is unfixed.
(Note)
VDD terminal
RESET terminal
GND
Crystal oscillator stops during the
reset from a reset terminal.
XOUT terminal
Internal reset
signal
Stand-by
(about 100 ms)
Reset
CPU operation
Stand-by
(about100 ms)
CPU
operation
CPU
Stand-by
operation
(about100 ms)
<Timing of operation >
Note: If there is a possibility that the power supply voltage will drop to 0.9 V or less, set to clock stop mode or
activate the reset operation.
26
2006-03-02
TC9329AFAG/AFCG
○
Back-up Mode
By executing the CKSTP instruction or WAIT instruction, three kinds of back-up mode can be activated.
1. Clock Stop Mode
Clock stop mode is a function that suspends system operations and maintains the internal status
immediately prior to suspension at a low level of current consumption (under 1 µA). Crystal oscillations
suspended simultaneously and CMOS output ports and output terminals for LCD display purposes are
automatically set at “L” level, and N-channel open-drain terminals are set to off status (high impedances)
automatically. The supply voltage can be reduced to 0.75 V with clock stop mode.
Suspension is activated at the CKSTP instruction execution address when the CKSTP instruction is
executed. The next address is executed after approximately 100 ms of stand-by time when clock stop mode
is cancelled.
(1)
Clock stop mode setting
There are two types of mode setting for clock stop mode. The required setting is selected with the
CKSTP MODE bit. This bit is accessed with the OUT2 instruction for which [CN = 6H] has been
specified in the operand.
Y1
φL26
Y2
Y4
Y8
CKSTP
mode
0: MODE-0
1: MODE-1
①
MODE-0
Wtih this mode set, the clock stop mode is assumed if the CKSTP instruction is executed when
the HOLD terminal is at “L” level. The same operations as the NOOP instruction will be
assumed if the CKSTP instruction is executed when the HOLD terminal is at “H” level.
②
MODE-1
With this mode set, the clock stop mode is assumed when the CKSTP instruction is executed
regardless of the HOLD terminal level.
Note: The PLL will assume off status during execution of the CKSTPinstruction.
Note: Before the execution of the clock stop instruction, be sure to access the HOLD input terminal and I/O
port 1 input port and rest the 2 HzF/F. Without execution of this instruction, it may not be possible to enter
clock mode even if clock mode is executed.
(2)
Canceling clock stop mode
①
MODE-0
Clock stop mode is cancelled when specified in this mode by changing the “H” level of the
HOLD terminal or the input status of the I/O port (P1-0~3) specified in the input port.
②
MODE-1
Clock stop mode is cancelled when specified in this mode by changing the HOLD terminal or
the input status of the I/O port (P1-0~3) specified in the input port.
27
2006-03-02
TC9329AFAG/AFCG
(3)
Clock stop mode timing
MODE-0
①
High impedance
XOUT terminal
CPU operation
Clock stop
CPU operation
Stand-by
(about 100 ms)
CKSTP
instruction
NOOP
operation
CKSTP instruction execution
NOOP operation
(The clock stop mode is assumed if the CKSTP instruction is executed when the HOLD input is at “L”
level.)
MODE-1
②
HOLD terminal
High impedance
XOUT terminal
CPU operation
Clock stop
Stand-by
(about 100 ms)
CPU operation
Clock stop
CKSTP
instruction
CKSTP instruction execution
CKSTP instruction execution
(The clock stop mode is assumed whenever the CKSTP instruction is executed.)
HOLD 34
VDD 39
POWER
4700 µF
1 kΩ
POWER
1 kΩ
470 µF
VDD 39
VDD 27
0.1 µF
VDD 27
1 MΩ
0.1 µF
1 MΩ
0.1 µF
HOLD 34
Example of a circuit (example of a MODE-0 circuit)
0.1 µF
(4)
Example of battery back-up
circuit
Example of a condenser back-up
circuit
28
2006-03-02
TC9329AFAG/AFCG
2. Wait Mode
Wait mode suspends system operations, maintains the internal status immediately prior to suspension
and reduces current consumption. There are two types of wait mode: SOFT WAIT mode and HARD WAIT
mode. Operations are suspended at the address where the WAIT instruction was executed when the wait
mode is activated. The next address is executed immediately after the wait mode is cancelled without entry
to stand-by status.
(1)
SOFT WAIT mode
Only the CPU operations within the device are suspended on execution of a WAIT instruction in
which [P = 0H] has been specified in the operand. The crystal resonator and other elements will
continue to operate normally at this time. The SOFT WAIT mode is efficient in reducing current
consumption during clock operations when used in programs that include clock functions.
Note: Current consumption will differ in accordance with execution time of CPU operation.
(2)
HARD WAIT mode
The operations of all elements, with the exception of the crystal resonator, can be suspended by the
execution of a WAIT instruction in which [P = 1H] has been specified in the operand. This enables
even greater levels of current consumption reduction than the SOFT WAIT mode. It suspends the
CPU operation.
Note: The output port is maintained during HARD WAIT mode. All LCD display output terminals are fixed
at “L” level and the voltage doubler circuit (VDB), LCD voltage regulator ciicuit (VEE) and LCD
voltage doubler circuit (VLCD) operate.
(3)
Wait mode setting
The wait status is assumed whenever the WAIT instruction is executed.
Note: The PLL OFF status will be assumed during the wait mode.
(4)
3.
Wait mode cancellation conditions
Wait mode is cancelled when the following conditions are satisfied:
① When the input status of the HOLD terminal changes.
② When the input status of the I/O port specified in the input port (P1-0~3) changes.
③ When the 2 Hz Timer F/F is set as “1” (only with the SOFT WAIT mode)
HOLD Input Port
Y1
φK17
Y2
Y4
Y8
Y1
0
HOLD
PLL
OFF
control
HOLD (INTR1) (INTR2)
φL39
0: Input “L” level
1: Input “H” level
Y2
Y4
Y8
0: Do not control of PLL OFF with a HOLD terminal
1: PLL OFF mode with “L” level of HOLD terminal
The HOLD terminal can be used as an input port. This bit loads into the data memory data input using
the IN1 instruction for which [CN = 7H] has been specified in the operand. It is necessary to access this
port prior to the execution of the CKSTP instruction when clock stop mode or wait mode is set. Note that,
without accessing this port it may not be possible to enter clock stop mode even if this instruction is
executed.
While HOLD PLL off control bit is set to “1”, PLL off mode result if HOLD terminal input goes to “L”
level. Therefore setting to PLL off-mode can be done quickly during battery replacement.
The bit is accessed with the OUT3 instruction for which [CN = 9H] has been specified in the operand. PLL
off mode becomes active even if all reference ports are “1”. (→ Refer to the reference frequency divider
item)
Note: The HOLD input terminal is used as an INTR2 terminal. The same as data is output at the HOLD and
INTR2 input ports.
29
2006-03-02
TC9329AFAG/AFCG
○
Interrupt Function
The peripheral hardware that can use the Interrupt function has an INTR1 terminal, INTR2 terminal,
Timer counter, and Serial interface.
If this peripheral hardware fulfills the conditions, the interrupt request signal from the peripheral
hardware is output, and the interrupt request is issued. On being received, each interrupt branches to a
vector address determined by the interrupt factor, and the processing routine for the interrupt begins.
Pretreatment and post-processing are necessary in the interrupt routine, before and after the normal
Interrupt processing, to restore the same state that was in effect at the time the interrupt occurred. It is
necessary to perform shunting and return of the register and indestructible data memory used by ALU to
the data memory for Interrupt use.. When interrupt processing ends, the program is restored using the
Return command for the Interrupt function.
The INTR1 and INTR2 terminals are serve as IFin1 and HOLD terminals.
1. Interrupt Control Circuit
The Interrupt Control Circuit consists of an interrupt permission flag, an interrupt latch, and an
interrupt priority circuit block. This control performs setup and control through the OUT2/IN2
instructions.
(1)
Interrupt enable flag
The interrupt enable flag has a master permission flag and individual permission flags
corresponding to each interrupt factor. An individual enable flag sets the interrupt
prohibition/permission according to the interrupt factor. A master enable flag is a flag for prohibiting
or permitting all Interrupts. If these enable registers are set to “1”, permission takes effect; if they are
set to “0”, prohibition takes effect..
An individual enable flag is accessed through the OUT2/IN2 instructions for which [CN 8H] has
been specified in the operand. A master enable flag can perform permission/prohibition by execution
of an EI/DI instruction.
Interrupt is prohibited by execution of a DI command, and enabled by execution of an EI command.
At this time, interrupt is enabled during execution of the EI command and DI command in the
program.
If an interrupt request is received, the master enable flag is reset to “0” and all interrupts are
prohibited. On execution of the interrupt return command, the flag is set to “1”. A master enable
flag is read into the data memory using an IN2 command for which [CN = 7H] has been specified.
φLK28
Y1
Y2
Y4
Y8
EF1
EF2
EF3
EF4
An individual enable flag
EF1･･･INTR1 terminal
EF2･･･INTR2 terminal
EF3･･･Serial interface
EF4･･･8 bits timer counter
φK27
Y1
Y2
Y4
Y8
IMF
0
0
0
Master enable flag
“0”･･･Prohibition
“1”･･･Enable
Reset to “0” on receipt of interrupt or execution of DI command.
Set to “1” on execution of the Interrupt Return or EI commands.
30
2006-03-02
TC9329AFAG/AFCG
(2)
φL29
Interrupt latch
If an Interrupt request generates, the interrupt latch is set to “1”.
If Interrupt is enabled, the CPU will be requested to receive the Interrupt, and the process will
branch to the Interrupt routine. If the Interrupt is received at this time, the Interrupt latch is reset
by data “0” automatically.
Interrupt latch data can read by the program and the existence or nonexistence of an Interrupt
occurrence can be determined on an individual basis. In accordance with the Interrupt request, the
Interrupt latch that was set to “1” is reset to “0”; in this way, it is possible to cancel or initialize the
Interrupt request.
Y1
Y2
Y4
Y8
ILR1
ILR2
ILR3
ILR4
Interrupt latch reset
φK29
If set to “1”, interrupt latch is reset to “0”.
Y1
Y2
Y4
Y8
IL1
IL2
IL3
IL4
Interrupt latch data
0: No Interrupt
1: Interrupt existence
On occurrence of Interrupt request, set to “1”; on
receipt of Interrupt, reset to “0”.
IL1･･･INTR1 terminal
IL2･･･INTR2 terminal
IL3･･･Serial interface
IL4･･･8-bits timer counter
(3)
Interrupt priority circuit block
Interrupt priority circuit is a circuit that determines the order in which Interrupts are processed if
Interrupts occur simultaneously or if two or more Interrupts have been permitted.. Vector addresses
for the interrupt routine are also generated in this block.
Priority
Interrupt Factor
Vector Address
1
INTR1 terminal
0001H
2
INTR2 terminal
0002H
3
Serial interface
0003H
4
Timer counter
0004H
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2006-03-02
TC9329AFAG/AFCG
2. Interrupt Reception Processing
The interrupt request is retained until the interrupt is received or the interrupt latch is reset to “0” by
system reset operation or by the program. The interrupt reception operation is as shown below.
① If the interrupt conditions are fulfilled, each item of peripheral hardware outputs each interrupt
request signal and sets the Interrupt latch to “1”.
② The Interrupt latch of the interrupt factor received resets to “0” if the interrupt enable flag
corresponding to each interrupt factor and the master enable flag are set to “1”.
③ The interrupt master enable flag resets to “0” and interrupt is prohibited.
④ The contents of a stack pointer are made -1.
⑤ The contents of the program counter (PC) are shunted to the stack register. In this case, the
contents of the program change to the next address after the point at which the interrupt was
received, or the next address after the point at which the interrupt was permitted.
⑥ The contents of the vector address corresponding to the received interrupt are transferred to the
program counter.
⑦ The contents of the vector address are executed.
Steps ①~⑥ are executed within one instruction cycle. This instruction cycle is called the “Interrupt
Cycle”
Note: The stack pointer is a pointer for which an 8-level stack register is specified.
Interrupt enable period
Instruction
EI
Instruc
-tion
Set “1” to
individual
enable
flag
Interrup
-tion
cycle
IMF
(Master enable flag)
Interrupt signal
Interrupt signal
IL
(Interrupt latch)
EF
(Individual enable flag)
One instruction cycle
Interrupt enable period
Interrupt processing
routine
Interrupt reception
Interrupt holed period
Instruction
Set “1” to
individual
enable
flag
EI
instruction
Interrupt
cycle
IMF
(Master enable flag)
Interrupt signal
Interrupt signal
IL
(Interrupt latch)
EF
(Individual enable flag)
Interrupt reservation period
32
Interrupt processing
routine
Interrupt reception
2006-03-02
TC9329AFAG/AFCG
3. Return Processing from Interrupt Processing Routine
A special command, the RNI instruction, is used to return to the processing state that was in effect before
the interrupt was received.
With execution of the RNI instruction, the following processing is executed step-by-step automatically.
① The contents of the address stack, specified by the stack pointer, are returned to the program
counter.
② Set the Interrupt Master Enable Flag to “1” to activate the enable state.
③ +1 is applied to the contents to the stack pointer.
The above-mentioned RNI instruction processing is performed in one instruction cycle.
4. Interrupt Processing Routine
The interruption is received regardless of the program being run when the interrupt request is issued if
this is the program area where the interrupt is enabled. Therefore, to restore the base program after the
interrupt processing is completed, it is necessary to return to the state in which interrupt processing was
not being performed. For this reason, it is necessary to perform the shunting and return operations
within the interrupt processing routine, at least for those items such as the register and data memory that
can be operated within the interrupt processing routine.
(1)
Shunting processing
In the execution of the shunting processing, it is essential that a carry flag be shunted. If
interruption is received during the execution of arithmetic or similar operations, the contents of the
carry flag (CY), etc., will change, resulting in the program making incorrect decisions. For this reason,
the contents of the carry flag are shunted in the data memory once through the IN1 instruction in the
data of the carry flag of the I/O map.
The contents of the data memory used by the interruption processing routine and the contents of a
general register are also made to shunt if needed. Furthermore, when MVGD, MVGS or DAL
instruction is used in the interrupt routine, it is necessary to shunt the contents of the G-register or
the DAL address register.
(2) Return processing
Return processing should do the opposite to the above-mentioned shunting processing.
Since, when the interrupt is received, the interrupt master enable flag is reset to “0”, it follows that
before receiving the interrupt, the interrupt master enable flag must have been “1”.
For this reason, the RNI instruction is executed and a master enable flag is returned.
5. Multiplex Interrupt
Multiplex Interrupt is a method of processing others interrupt during interrupt processing.
As shown in the figure, the other interrupt factor C or D is processed during the interrupt processing of
interrupt factors A and B. In this process, the depth of the interrupt is called the interrupt level.
Main
routine
Interrupt
level 1
Interrupt
level 2
MAIN
B
D
A
B
Interrupt
level 3
Interrupt
level 4
C
D
C
The example of multiplex interrupt
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Caution is required for the following points when using multiplex interrupt.
① The priority of interrupt factors
② Restriction of the address stack level used at the time of interrupt request issue
③ Shunting processing of the carry flag, the data memory, etc.
(1)
Priority of interrupt factor
In this priority ranking, the processing of interrupt C must be given priority even if the interrupt
processing of A or B is in progress; and the processing of D must be given priority even if the interrupt
processing of C is in progress.
The necessity of determining priority in the handling of multiple interruptions can be illustrated as
follows. Suppose, for example, there are the interruption factors A and B. For factor A, a request is
generated about every 10 ms and the interrupt processing time is 4 ms; for factor B, a request is
generated about every 2 ms and the interrupt processing time is 1 ms. If no priority were applied to
A and B, then a request for interrupt A that came in during the processing of interrupt B could lead to
interrupt A being processed, resulting in the processing of interrupt B being repeatedly stopped. Such
a case requires a program that establishes the priority A B, not only prohibiting interrupt A during
the processing of interrupt B but also enabling the reception of interrupt B during the processing of
interrupt A.
As explained in the item on the interrupt priority circuit block, when all individual enable flags are
set to “1” (enable state), the priority of the hardware can be changed by manipulating the individual
enable flags in the program.
As a rule, received interrupts and low-priority interrupts are prohibited, and high-priority
interrupts are enabled in the interrupt processing routine.
(2)
Restriction of address stack level
As explained in the item on interrupt reception processing, when an interrupt request is issued, the
return address is shunted automatically to the address stack. As explained in the item on registers,
an address stack is also used for execution of sub-routine call instructions on eight levels. For this
reason, if the interrupt level and sub routine call level exceed eight levels, the contents of the return
address recorded from the first address stack are destroyed. Therefore restriction is necessary.
(3)
Shunting processing
When using the Multiplex Interrupt function, it is necessary to secure a shunting area for shunting
processing separately for each interrupt factor.
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○
External Interrupt and Timer Counter Function
There are two types of external interrupt: that using the INTR1 terminal and that using the INTR2
terminal. Interrupt requests are issued by the rising or falling edge of a signal applied to these terminals.
The timer counter is an 8-bit binary counter and has the function of timer and external clock timer. The
input of the external clock timer function is used as an external interrupt terminal (INTR1, INTR2).
1. External Interrupt Function
There are two input terminals for external interrupt, INTR1 and INTR2; and an interrupt request is
issued on detection of the edge of these inputs. There is a noise canceller for the input: a noise removal
clock uses a frequency of 75 kHz, and any pulse under this frequency is removed as noise. The IE bit is an
enable bit which permits 8-bit timer counter operation, and interrupt and external interrupt requests. It is
possible to select either the rising or falling edge as the input edge for each terminal. Usually, this bit is set
to “1”.
These controls are accessed using an OUT2 instruction for which [CN
7H] has been specified in the
operand. The program will branch to address 0001H on receipt of an INTR1 interrupt, and to address
0002H on receipt of an INTR2 interrupt.
These terminals are used as input ports and the input status can be read into the data memory by
execution of an IN2 instruction for which [CN 7H] has been specified in the operand.
Y1
φL27
Y2
POL1 POL2
INTR1 INTR2
Edge select
Y4
Y8
IE
*
8-bitsTimer and control external interrupt
operation enable control
“0”: Prohibition
“1”: Enable
Usually, the bit is set “1”.
Pulse less than 13.3 µs eliminated
more than 40 µs regarded as a signal
1: Rising edge
0: Falling edge
Note: The edge of the external clock of the timer counter is also controlled. No noise cancel
function is used for the input to the timer counter. Therefore, even if no interrupt occurs,
caution is necessary regarding the input of a clock pulse of less than 40 s into the clock
pulse counter.
Select edge of timer counter
Y1
φK17
Y2
( HOLD ) INTR1
Y4
Y8
INTR2
O
The input state of each
1: Count by rising edge
0: Count by falling edge
0: Input “L” level
1: Input “H” level
Note: An interrupt request may be issued if an edge is changed using POL bits. For this reason, when changing
an edge, be sure to prohibit interruption beforehand. After making the change, reset the interrupt latch
and return to normal operation.
Note: The INTR1 terminal and INTR2 terminal are used as IFin1 terminal and HOLD terminal respectively.
If using only the INTR1 terminal be sure to set IF1/INTR bits (φL16) to “0”. Also, the same data is output
at the HOLD input and INTR2 input port.
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2. Timer Counter Function
Timer counter are consists of 8-bit binary counter, counter coincidence register, digital comparator and
controlled the control circuit.
If timer counter is coincided with the contents of counter coincidence register, timer counter is outputted
a coincidence signal pulse and interrupt request is done by inputting timer clock to 8-bit binary counter
timer clock. Reset of Timer counter is possible with a coincidence pulse and a program, and it can perform
enable and prohibition of reset by the coincidence pulse. As a clock of timer, it can be selected INTR1/2
input and an instruction cycle and 1 kHz.
(1)
Timer counter register configuration
The timer counter register consists of a counter data, coincidence register and a control register.
φL2A
φL2B
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Timer counter coincidence data
φK2A
φK2B
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Timer counter data
φL2C
A coincidence pulse will be output if in agreement with the
timer counter.
Y1
Y2
Y4
Y8
CK0
CK1
GT
CR
Select of timer clock
Timer counter data is read into data memory as binary data.
Timer counter reset･･･“Whenever sets “1”, counter is reset.
Enable counter reset by coincidence pulse.
CK1
CK0
0
0
INTR1 terminal input
0
1
INTR2 terminal input
1
0
Instruction cycle clock (40 µs)
1
1
1 kHz
0: Enable
1: Prohibition
Timer clock
Select clock edge by POL bit
0: Count by raising edge
1: Count by falling edge
Note: To use the timer counter, it is necessary to set the IE bit to “1”.
Note: Set
the IF1/INTR bits (φL16)
to “0” when the INTR1 terminal is used as a timer clock.
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(2)
Timer mode
Timer mode is detected fixed time. Interrupt request is done and reset to counter whenever it
detects fixed time. At this time, control bit is set to 1 kHz or an instruction as timer clock, “0” to GT
bit and “0” (it does not reset) to CR bit.
Timer coincidence data is
Timer time = IDn (coincidence data) × Timer clock cycle
It sets up the data which corresponding to time.
In addition, although an external terminal can be used for Timer clock, a clock frequency should use
the frequency below 25 kHz. If GT bit is setup “1”, it can be also be integrated of an external clock.
It is used by inputting more than 40 µs cycle at the time of an external clock input.
Timer clock
Timer data
IDn
00H
01H
02H
03H
ID (N − 1)
IDn
00H
01H
02H
03H
Coincidence pulse
Request for interrupt and
reset timer counter.
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○
Internal Interrupt and Interrupt Function
Interrupt has two types of timer counter and serial interface.
1. Interrupt of Timer Counter
If timer counter value is same as coincidence register value, interrupt of timer counter is occurred
interruption. Refer to the item of timer counter function in detail.
2. Interrupt of Serial Interface
Interrupt of serial interface is occurred interruption at the time of finishing operation of serial interface.
Refer to the item of serial interface function in detail.
3. Interruption Block Configuration
Serial interface interrupt
HOLD
75 kHz
ILR1
INTR1
35
(IFin1)
ILR3
ILR4
Noise canceller
POL1
INTR2
34
( HOLD )
S
INTR2
INTR1
R
S
IL1
Noise canceller
1 kHz
Instruction cycle clock
CK0
CK1
ILR2
EF1
POL2
R
S
IL2
R
IL3
EF2
S
R
IL4
EF3
EF4
Decoder
Priority determination•Vector address generate circuit
La
Interrupt
receiving
signal
Selector
CT0~CT7
CR
EI instruction
S
Vector
address
IMF
R
8 bits binary counter R
DI instruction
Coincidence pulse
RNI instruction
Coincidence register (ID0~ID7)
GT
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○
Programmable Counter
The programmable counter consists of two modulus prescalers, a 4-bit + 13 bit programmable counter
and a port to control these elements.
The programmable counter controls the ON/OFF functions for the contents of the reference port and
HOLD input status. By using external prescaler (TD6134AF/TD7101/04F) or 1 chip tuner IC that is
built-in for 1/16 prescaler (TA2142FN), it’s possible to reduce the emission from the tuner portion and
consumption current.
1. Programmable Counter Control Port
This port is controlling for division frequency, division method and operating current and gain of
prescaler.
φL10
Y1
Y2
Y4
Y8
HF
PW0
PW1
FM
Power control
Division method setting
φL11
φL12
φL13
φL14
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11
LSB
Y8
Y1
φL15
Y2
Y4
Y8
P12 P13 P14 P15
Setting the number of divisions of the programmable counter
Y1
Y2
Y4
Y8
P16
MSB
The division method and power control of the prescaler are accessed using an OUT1 instruction for which
[CN = 0H] has been specified in the operand.
The division frequency setting is accessed using an OUT1 instruction for which [CN = 1~5H] has been
specified and the setting is made by writing in the P16 bits (φL15). All data between P0 to P16 are updated
when P16 is set. It is therefore necessary to access P16 without fail even when updating only certain items
of data and to perform setting as the final process.
Y1
φL39
Y2
Y4
Y8
Prescaller
PSC
ENA
IN
PSC output permission setup
0: PSC output prohibition
1: PSC output permission
Pre-scaler IF counter input setup
0: Regular PLL composition
1: Pre-scaler division output is input to IF counter.
PSC output permission setup is used at the time of connection of external prescaler.
In the setup to prescaler IF input, if the bit is set to “1”, a programmable counter stops and prescaler 1/15
and 16 are fixed to 16 division. Usually, consisting of PLL, the bit is set to “0”.
(→ Refer to the IF counter item)
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2. Division Method Setting
The pulse swallow method or direct method are selected using the HF and FM bit.
The power control bits (PW0/1) control the gain of the amplifier and prescaler (1/2  1/15•16). Although
the power bit in each mode has five methods, set it up as shown in a table.
By using the single-chip tuner IC that is built-in for the 1/16 prescaler (TA2142FN), set the LF mode and
set the division value after the 1/16 division frequency.
Mode
HF
PW0
PW1
FM
Division Method
Example of Receiving
Band
Operation Frequency
Range
LF
0
1
0
0
Direct division method
MW/LW
0.5~8 MHz
HF1
1
1
0
0
Pulse swallow method
(1/15•16)
HF2
1
0
1
0
FM
1
1
0
1
VHF
1
0
1
1
n
3~30 MHz
SW
Division
Number
(Note)
1~10 MHz
FM
Pulse swallow method
60~130 MHz
2•n
TV
(1/2 + 1/15•16)
80~230 MHz
(1 ch~12 ch)
Note: “n” represents the number of divisions programmed.
Note:
Do not perform a setup except for the above-mentioned power control setup.
There are not normal operation such as flowing over-current or unlocked PLL etc..
Note: A local oscillation input is common to each mode, and is altogether input into OSCin terminal.
3. Frequency Division Number Setting
The frequency division number for the programmable counter is set in bits P0 to P16 in binary.
• Pulse swallow method (17 bit)
MSB
LSB
P16 P15 P14 P13 P12 P11 P10
2
P9
P8
P7
P6
P5
P4
P3
P2
P1
16
P0
0
2
The range of frequency division number setting (n = 210H~1FFFFH (528~131071)
• Direct division method (13 bit)
MSB
LSB
P16 P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
12
P5
P4
P3
P2
P1
P0
0
2
2
The range of frequency division number setting (n = 10H~1FFFH (16~8191)
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4. PSC Output Permission Setting
In case of using the external pre-sccaler (TD6134AF/TD7101/04F), PSC output permission bit is setup to
“1”. At this time, a swallow counter will be operating and prescaler will be in a stop state, and PSC output
is outpu P2-3 terminal. A division method is set as LF mode, and AM VCO input and an external prescaler
output are changed and input into AMin input terminal. P3 terminal is used by setting it as an output port.
TC9329AFAG/AFCG
TD6134AF
PSC 53
7 PSC
0.01 µF
5 OUT
OSCin 38
0.001 µF
2 FMin
0.001 µF
3 VHFin
AM VCO
FM/TV VCO
The example of an external pre-scaler connection circuit
5. Programmable Counter Circuit Configuration
• Pulse swallow method circuit configuration
This circuit consists of amplifier, two 1/15•16 modulus prescalers, the 4-bit swallow counter and a
13-bit binary programmable counter. A 1/2 frequency divider is added to the front stage of the prescaler
when in the VHF/FM mode.
P0~P3
PW0/1
OSCin
0.01 µF
38
1/16
Amplifier
1/2
1/15•16
1/15
4 bit
swallow counter
Pre-set
13 bit
programmable counter
To the phase
comparator
P4~P16
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• Direct division method circuit configuration
The prescaler is not required if this is selected; instead, the13-bit programmable counter is used.
Pre-set
PW0/1
Amplifier
OSCin 38
13-bit
programmable counter
To the phase comparator
P4~P16
Note: OSCin terminal has been fitted into the amplifier, and small amplitue possible by linking them to a
condenser. The input is high impedance when PLL is in the off mode. VCO input serves as each of
operation mode common terminal.
Note: If it becomes PLL off-mode, all programmable counter parts will be stopped. The contents of each control
port are held at this time.
○
Reference Frequency Divider
The reference frequency divider divides the oscillation frequency of the external 75 kHz crystal and
generates the following seven types of PLL reference frequency signals; 1 kHz, 3 kHz, 3.125 kHz, 5 kHz,
6.25 kHz, 12.5 kHz and 25 kHz. These signals are selected with reference port data.
The selected signal is supplied as a reference frequency for the phase comparator as described below. Also,
the PLL is switched on and off with the contents of the reference port.
1. Reference Port
The reference port is an internal port for selecting the seven reference frequency signals. This port is
accessed using an OUT1 instruction for which [CN
5H] has been specified in the operand ( L15).
Operations for the programmable counter, the IF counter and reference counter are suspended; and the
PLL assumes the off mode when the contents of the reference port are all “1”. As the frequency division
setting data for the programmable counter is updated when the reference port is set, it is necessary to set
the frequency division number of the programmable counter prior to setting the reference port.
φL15
Y1
Y2
Y4
R0
R1
R2
Y8
Reference frequency selection code
42
R2
R1
R0
0
0
0
0
0
0
1
1
3 kHz
0
1
0
2
3.125 kHz
0
1
1
3
5 kHz
1
0
0
4
6.25 kHz
1
0
1
5
12.5 kHz
1
1
0
6
25 kHz
1
1
1
7
PLL off mode
Reference Frequency
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○
Phase Comparator and Lock Detection Port
The phase comparator compares the difference in phasing between the reference frequency signal
supplied from the reference frequency divider and frequency division output of the programmable counter
and outputs the result. It then controls the VCO (voltage control oscillator) via a low pass filter in order to
ensure that the two frequency signals and the phase difference match.
In order to use a phase comparator and a charge pump output are constant voltage Vreg potential (1.5 V),
it is possible to stabilized phase comparison even if VDD potential was set to 0.9 V.
The DO terminal can also be used as a general-purpose output with the Do control port.
1. Do control Port and the Unlock Detection Port
Y1
φL19
Y2
UNLOCK
RESET
Y4
Y8
DO control
PN
M0
M1
Set up DO output
M1
M0
DO Output Status
0
0
Do output
0
1
“L” level
1
0
“H” level
1
1
“HZ”
DO terminal output state Setup → set to “0”
Unlock F/F and unlock enable are reset whenever the data is set at “1”.
Y1
Y2
UNLOCK
φK19
F/F
Y4
Y8
(INTR1)
IN2
0: Input terminal “L” level
1: Input terminal “H” level
ENA
Input port
φL2D
Note: An input state is read for IF counter input combination
terminal from this port at the time of an input port setup.
INTR1 data turns into the same data as INTR1 port of an
interruption item.1
Unlock enable
0: PLL unlock detection stand-by
1: PLL unlock detection enabled
Unlock detection bit
0: PLL lock status
1: PLL unlock status
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
φL3B
A
Y1
Y2
Y4
Y8
Vreg
ON
*
*
*
0: Constant voltage OFF
1: Constant voltage ON
1.5 V constant voltage operation
control of Vreg terminal output
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M0 and M1 bit of DO control ports are perform a general-purpose output port setup of DO output, and a
setup of high impedance.
The power supply of a phase comparison and a charge pump output circuit is using Vreg terminal. The
Vreg terminal is output constant voltage of 1.5 V and “H” level of charge pump output is output Vreg
terminal. For a reason, phase comparison operation power supply voltage was stabilized by 0.9 V is
possible. The operation control of Vreg Constant voltage is controlled by Vreg ON bit (φL3BA), if the bit is
set “0”, the Vreg terminal potential is output VDD level and set “1”, it becomes 1.5 V Constant voltage potential
For this reason, it is set “1” at the time of PLL on mode and set “0” at the time of PLL off-mode. Unlock F/F
detects the phase difference of a programmable counter division output and reference frequency to the
timing from which about 180 degrees of phases shifted. When a phase does not suit at this time (that is
unlock status), unlock F/F is set. The unlock F/F status is reset whenever the UNLOCK RESET bit is set
as “1”.
It is necessary to access to UNLOCK F/F after establishing more time than is required for the reference
frequency cycle after the unlock F/F has been reset in order to detect the phase difference with the
reference frequency cycle. It is for this purpose that the enable bit has been made available, but the unlock
F/F must not be accessed until after it has been confirmed that the unlock enable has been set at “1”.
Note: When PLL off mode is set during the DO output setup, the output of this terminal becomes as high
impedance. In DO terminal, when PLL off-mode or the clock stop mode is set up at the time of a
general-purpose output port setup, this output state is held.
2. Phase Comparator and Unlock Port timing
Reference frequency
Programmable
counter output
High impedance
Do output
“H” level (Vreg)
“L” level (GND)
Phase difference
Lock detection
strobe
Unlock reset
execution
Unlock F/F
Unlock enable
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3. Phase Comparator and the Unlock Port Circuit Configuration
Vreg
Decoder
Reference
frequency
Phase comparator
Programmable
counter output
40 DO/OT
M1, M0 bit
UNLOCK
ENABLE
UNLOCK
F/F
UNLOCK
RESET
VDB
(VDD × 2 doubler
power supply)
41 Vreg
Constant voltage circuit
VregON
Note: At the time of PLL on mode, VregON bit is setup “1” and PLL off mode, set up “0”.
DC-DC
converter
DO/OT 40
R1
100 kΩ
C1 R2
FN/VHF/AM
VCO
0.01 µF
LPF
0.47 µF (Typ.)
To the VCO
variable
capacitor
Example of low pass filter circuit
(for reference)
10 kΩ
1 µF
4.7 kΩ
4.7 kΩ
40 DO/OT
0.1 µF
Vreg 41
Example of an active low pass filter
circuit (for reference)
Note: The filter circuits illustrated in the above diagrams are for reference purposes only. Be sure to design the
actual circuits taking into account the band configuration of the system and required characteristics.
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○
IF Counter
The IF counter is a 20-bit general-purpose IF counter that calculates Fm and AM intermediate
frequencies (IF) during auto-tuning and can be used for detecting auto-stop signals, etc. The VCO of an
analog tuner is measured, and detection of the received frequency and detection of the CR oscillation
frequency can be performed.
1. IF Counter Control Port and Data Port
φL16
Y1
Y2
Y4
Y8
IF1/ 2
PW
IF1/INTR1
IF2/IN2
0: Set input port
1: Set IF input port
Selection of IF input
/Input port
Set IF amplifier gain → set up “0”
0: Set IFin2 input
1: Set IFin1 input
Selection IF input
Note: At the time of an input port setup, the terminal becomes CMOS input type and be able to detect
frequency by IF counter.
φL17
Y1
Y2
Y4
Y8
STA/ STP
MANUAL
G0
G1
Selection of the gate time for frequency
measurements (measurement time)
G1
G0
Gate Time
0
0
1 ms
0
1
4 ms
1
0
16 ms
1
1
64 ms
Frequency measurements automatic/manual mode switching bit
0: Automatic mode (measurement is performed with the
above-mentioned gate time when in automatic mode)
1: Manual mode (starts/stops measurements with the STA/ STP bits)
IF counter start/stop control bit
0: Counter stop
1: Counter start
Y1
φL39
Y2
Y4
IF
counter
Split
Prescaller
IN
Y8
OSCin pre-scaler input setups at IF counter
0: Set IFin terminal input
1: Set OSCin terminal input
IF counter division operation setup
0: IF counter 20 bit operation
1: Inputs into 8 bits of IF counter higher ranks from INTR2 terminal.
Note: When a prescaler input is set as IF counter input, at the time of a setup of a pulse-swallow system,
prescsler;1/15•16 are fixed to 16 division, and this frequency is input into IF counter.
Note: When a division operation setup of the IF counter is carried out, the counter of 8 bits of higher ranks is
input from INTR2 terminal. However, only 8 bits of this higher rank cannot perform a gate setup by the
auto mode. Reset of this counter is reset by setting up “1” to STA/ STP bit.
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φK10
Y1
Y2
Y4
Y8
BUSY
MANUAL
OVER
0
20
0: IF counter calculation value <
=2 −1
20
1: IF counter calculation value >
= 2 (overflow status)
Overflow detection
0: IF counter automatic mode
1: IF counter manual mode
Operation mode
0: IF counter calculation ended
Operation monitor 1: IF counter calculation in progress
φK11
φK12
φK13
φK14
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10 F11
Y8
Y1
φK15
Y2
Y4
Y8
F12 F13 F14 F15
Y1
Y2
Y4
Y8
F16 F17 F18 F19
20
219
LSB
IF counter data
MSB
Note: When it is set as IF input, in PLL off-mode, IF input amplifier is turned off in PLL-off mode. In using IF
counter in PLL off-mode, it sets it as an input port (CMOS input).
Note: The input amplifier un-chosen by IF1/ 2 bit. If input amplifier turns off, this input will serve as high
impedance.
(3)
IF counter automatic mode
A setup in the auto mode of IF counter is set “0” to MANUAL bit and gate time is set up according
to the frequency band to measure. If the STA/ STP is set “1”, operation of IF counter will be started
and the set-up clock in gate time will be input, and this number of input pulses is counted and it ends.
An end of the calculation of IF counter can be judged by referring to BUSY bit. When more 220 pulses
are input for a total numerical value, OVER bit is set to “1”. BUSY bit and OVER bit are judged “0”
and the frequency input can be measured by taking in IF data of F0-F19.
(4)
IF counter manual mode
By internal time base (10 Hz etc.), it is used when gate time is controlled and it measures frequency.
The manual mode is set “1” to MANUAL bit. At this time, a gate time setup serves as don't care. In
STA/ STP bit is set to “1”, it starts calculation. In STA/ STP bit is set to “0”, it will end and
calculation will take in data by the binary.
(5) An input setup and division setup of IF counter
Usually, intermediate frequency (IF) Measurement is input into IFin1 or IFin2 terminal input, and
measures this frequency. These terminals contain input amplifier and small-size width operation is
possible. In addition, the following setup is possible to the input to IF counter, and use it for it according to
specification.
IF
Prescaller
Ifin
counter
IN
(φL3B6:Y1)
Split
IF1/ 2
IF1/INTR1
IF2/IN2
1
1
*
0
0
0
IFin1 input (amplifier operation)
1
0
*
0
0
0
INTR1 (IFin1) input (CMOS input)
0
*
1
0
0
0
IFin2 input (amplifier operation)
0
*
0
0
0
0
IN2 (IFin2) input (CMOS input)
IF Input Setup
VHF mode (32 divided frequency)
*
*
*
0
1
0
(Note)
OSCin FM mode (32 divided frequency)
(Note)
input
HF1/2 mode (16divided frequency)
(Note)
LF mode (input frequency)
(Note)
*
*
*
0
1
1
CR Oscillation frequency (fCR)
*
*
*
1
*
*
Input from PCTRin (HOLD ) terminal only 8 bits only of higher
ranks.
Note: Refer to the programmable counter item for the input frequency range at the time of prescaler input setup.
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2. IF Counter Circuit Configuration
The IF counter circuit consists of an input amplifier, a gate time control circuit and a 12  8 bit binary
counter.
The OSCin prescaler and CR oscillation clocks can be input as IF counters.
PW0/1
amplifier
OSCin
0.01 µF
1/2
38
To programmable counter
1/15•16
PSC
PW
IFin1
0.01 µF
0.01 µF
CR oscillation circuit
IF1/INTR1
35
IFin2
Prescaller
IN
fCR
PrescallerIN, IFin
IF counter
Split
F0~F11
F12~F19
OVER
8 bit binary counter
OVER
IF2/IN2
12 bit binary counter
36
Gate
IF1/ 2
IN2 IN1
1 kHz
Gate time
control circuit
Manual
G0
G1
STA/ STP
PCTRin
34
HOLD
Note: All the binary counters of the IF counter operate in a standup.
Note: During input of the OSCin into the IF counter, the 1/15･16 of the prescaler is fixed to a dividing frequency
of 1/16.
This dividing frequency becomes 1/32 in VHF/FM mode and 1/16 in HF mode. In LF mode, the OSC frequency
can be input directly.
IF counter input
“1”
Data set to STA/ STP bit
BUSY bit
1 kHz
Gate
Binary counter input
An example of IF counter auto mode operation timing
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○
LCD Driver
The LCD driver uses a 1/4 duty and 1/2 bias drive method (62.5 Hz frame frequency).
The common output outputs the VLCD, VLCD/2 (VEE) and the GND electrical potential, and the segment
output outputs the VLCD and GND electrical potential.
A combination of four common outputs and 18 segment outputs enables a maximum of 72 segments to be
illuminated. The S11 to S18 segment output pins for the LCD driver can also be used as I/O ports on being
set to function as I/O ports after system reset. The I/O port and segment output can be changed using bit
units. All LCD output pins (COM1-S14) can be changed to output ports. The LCD driver is incorporates a
constant voltage circuit (VEE = 1.5 V) for display purposes and a voltage doubler circuit (VLCD = 3.0 V).
The voltage doubler (VDB), which raises the power supply voltage to twice its level, is used for the constant
voltage circuit for the display (VEE). For this reason, it is even possible to stabilize the LCD display at a
power supply voltage of 0.9 V.
1. LCD Driver Port
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Segment-1 data
Y1
φL2E
Y2
Y4
Segment-2 data
Y8
Y1 COM2
Y2 COM3
Y4 COM4
Y8
COM1
Y1
Y2
Y4
Y8
0
S1
1
Y1
φL2F
S2
2
Y2
1
S3
Y8
S14
2
Segment data
0: Extinguished
1: Illuminated
S15
COM1 COM2 COM3 COM4
B
Y4
Y1 COM2
Y2 COM3
Y4 COM4
Y8
COM1
Y1
Y2
Y4
Y8
0
S13
COM1 COM2 COM3 COM4
S12
5
Change for segment and I/O port
6
0: I/O port
1: Segment output
7
Y1
Y2S18
Y4
Y8
S11
S12
S13
S14
Y1Segment
Y2 /IO select
Y4
Y8
S15
S18
S16
S17
Segment /IO select
LCD display off control bit
0: All LCD display illuminated
1: All LCD display extinguished
F
DISP
OFF
LCD
OFF
OTB
-UP
*
LCD off control bit
0: LCD output setting
1: Output port setting
Note: If the DISP off-bit is set to “1”, common output and a segment output.are output at “L” level.
Note: The segment data controls the illumination and extinguishing of segment lighting corresponding to the
common output and segment output..
Note: During clock stop mode and about 100 ms after system reset, all the common and segment outputs are
fixed at “L” level..
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The LCD driver control port consists of the segment data selection port and the segment data port. These
ports are accessed using an OUT2 instruction for which [CN = DH~FH] has been specified in the operand.
The segment data for the LCD driver is set through the segment data ports (φL2E, φL2F). The LCD display
will be extinguished when the segment data port is set to “0”, and will be illuminated when the port is set
at “1”. Also, the segment-2 data (φL2FF) specified with FH in the segment selection port becomes the DISP
OFF bit and LCD OFF bit without setting of the segment data.
It is possible to extinguish the entire LCD display using the DISP OFF bit without setting the segment
data. If this bit is set to “1”, the common output and segment output are fixed to “L” level and the entire
LCD display is extinguished. The segment data is retained at this point, and the previous display appears
on the LCD if the DISP off bit is set to “0”. In addition, rewriting of segment data is possible during DISP
OFF. Moreover, after reset and CKSTP instruction execution, the DISP off bit is set to “1”.
The LCD off bit can set all LCD output terminals to serve as output ports. For the LCD display, this bit is
set “0”.
(→ Refer to the output port item)
The terminals S11 to S18 terminal are used as I/O Ports. This control is done a segment/IO port select
port (φL2F6, φL2F7).
Set to “1”, the port will become segment output port and set to “0”, it will become an I/O Port.
(→ Refer to the output port item)
These data is divided and undirected setting by data selects port (φL2D). The data of a specification port to
set a segment data port to beforehand is set, and the data port corresponding to it is accessed.
A data select port is +1 increment whenever accessing data port (φL2E, φL2F). For this reason, after
setting up a data selection port, it can set up continuously.
Note: The data select port is +1 increment automatically by accessing φL2E, φL2F, φL3B, φK3B on I/O map.
DIPS OFF
COM1/OT1
COM2/OT2
COM3/OT3
COM4/OT4
S1/OT5
S2/OT6
S3/OT7
S10/OT14
P8-0/S11
P8-1/S12
P9-2/S17
P9-3/S18
2. LCD Driver Circuit Configuration
1
2
3
4
5
6
7
14
15
16
21
22
Segment driver
Common output
circuit
500 Hz
Segment data
I/O-8•9 Port
VLCD OFF
61
62
63
0.1 µF
75 kHz/2
VLCD
C4
C3
VEE
VDB
58
Voltage doubler
circuit (VEE × 2)
64
0.1 µF
0.1 µF
Constant voltage
circuit
(VEE = 1.5 V)
0.47 µF
59
10 µF
60
0.1 µF
To A/D converter
Constant voltage
circuit (Vreg)
C1
VDD
Power supply voltage
Double voltage circuit
(VDD × 2)
C2
75 kHz/2
Note: If set to serve as an I/O port, this output port is Nch open drain.
Note: In case of setting segment output as output port in setup “1” to VLCD OFF bit ,“H” level of all output
becomses VLCD potential output. When “H” output is made into VDD remove the capacitor between
C3/C4, and connect VLCD and VDD.
Note: During clock stop mode and reset, the potential of VLCD/VEE/VDB becomes as VDD level.
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Example of segment data
COM1
Segment data -1 (φL2E)
Y1
COM2
S1
Y4
Y8
COM1 COM2 COM3 COM4
0
(S1)
COM3
Y2
1
0
1
0
Y1
Y2
Y4
Y8
COM4
COM1 COM2 COM3 COM4
1
S2
(S2)
1
1
0
1
Segment data selection (φL2D)
DISP OFF
16 ms (62.5 Hz)
2 ms
VLCD
COM1
VEE
GND
VLCD
COM2
VEE
GND
VLCD
COM3
VEE
GND
VLCD
COM
VEE
GND
VLCD
S1
GND
VLCD
S2
GND
VLCD
COM1-S1
(ON waveform)
GND
−VLCD
VLCD
COM2-S1
(OFF waveform)
GND
−VLCD
The potential of the LCD driver waveform outputs the potential of the VLCD and GND, and the middle
potential level that is 1/2 these values.
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○
Serial Interface (SIO1/2)
There are two kinds of serial interface: SIO1 and SIO2. SIO1 is the serial I/O port, which transmits and
receives data (4 bits or 8 bits) in synchronization with an internal or external serial clock. The SI, SO, and
SCK terminals transmit and receive together with the extension LSI and microcomputer, etc. Interruption
is issued when the serial interface stops operating. All outputs are Nch open drain outputs.
SIO2 inputs 26-bit data serially in synchronization with an external serial clock.
SIO2 has a function for decoding the input serial data, and interruption is issued for every input serial
clock edge.
1.
Control Port and Data Port of the Serial Interface
Y1
φL22
edge
Y2
Y4
Y8
SCK-INV SCK - I/ O SIO-ON
Selection of the I/O port-3 and serial interface
0: I/O port-3 selection (P3-1~P3-3)
1: Serial interface SIO1 or SIO2 function selection
SCK clock external/internal selection
0: External clock output
1: Internal clock output
Inversion of the SCK clock signal
0: SCK clock output from “HZ” level
1: SCK clock output from “L” level
Logical selection of serial data shift operation
(SIO1/2 common)
0: Shift at the SCK rising edge
1: Shift at the SCK falling edge
φL23
Y1
Y2
Y4
Y8
STA
SO - I/ O
8/ 4 bit
SIO
Select
Permission operation of the serial interface 2 (SIO2)
0: SIO2 mode stop
(Interrupts on end of SIO1 serial operation end.)
1: SIO2 mode operation (interrupt on SCK clock edge)
Selection of the data length of serial data
0: 4 bit data
1: 8 bit data
Selection of input and output of SO terminal
0: SO output
1: SI input
Serial operation start and internal port reset
0: Don’t care
1: Reset COUNT, SIO F/F and the serial output data in
the shift register. Serial operation is started when the
internal SCK clock is selected.
Reset SIO2 shift register data (26 bits)
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φL24
φL25
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
Serial output data: The data set in these ports is output in serial format
φK24
φK25
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
Serial input data: It is possible to load data input in serial format into data memory
Y1
φK23
Y2
BUSY COUNT
Y4
Y8
SIO
F/F
0
SIO start flag
0: SIO operations performed
1: SIO operations not performed
SCK clock count detection
0: Clock count normal (SCK clock count is in multiple of four)
1: Clock count abnormal (SCK clock count is not in multiple of four)
SIO operation monitor
0: SIO operations ended
1: SIO operation in progress
Serial interface control and data are accessed with an OUT2 and IN2 instruction for which [CN =
2H~5H] has been specified in the operand.
The serial interface terminal is used together with the I/O-3 P3-1, P3-2, and P3-3 terminals, and each of
the I/O port-3 terminals are switched to operate as SI, SO and SCK terminals by setting the SIO ON bit to
“1”.
Note: All the serial interface inputs incorporate Schmidt circuits.
Note: Since the SI (P3-1) terminal can be used as an I/O port even when the serial interface function is
selected, it can be used for the SIO strobe signal, etc.
If this terminal is used for serial input, be sure to enter “1” for the setting of the P3-1 output data and
change it to the input state.
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①
edge, SCK-INV, SCK-I/O bits
The edge bit is setup the edge of a shift and the SCK-INV bit set up the input-and-output waveform
of a shift clock. Serial clock (SCK) shift operation is performed on the rising edge if the edge bit is set
to “0”, and on the falling edge if the edge bit is set to “1”. SCK-INV bit is set the bit of serial clock
output from “H” or L”. In case of setting "0", it starts shift operation from “H” output, and setting “1”,
it starts shift operation from “L” output. These bits perform serial operation in accordance with the
settings as shown in the following table. Make the settings in accordance with the controlling serial
format.
SCK-I/O bit is setup the input-output of serial clock. Usually, when this product is used as a master,
t “1” to SCK-I/O bit and then it used as serial clock output and in the case of a slave, set to “0” and
then it used as serial input.
SCK-INV = 0
SCKINV = 1
STA bit set as “1”
STA bit set as “1”
1
edge = 0
SCK terminal
SO terminal
2
SO0
SI terminal
3
SO1
SI0
SO2
SI1
SCK terminal
4
SI terminal
SI3
edge = 1
1
2
SO terminal
BUSY
SO0
SI0
4
SO1
SI1
SO2
Interrupt
SI0
STA bit set as “1”
3
SO0
4
SO1
SI1
SO3
SI3
SI2
Interrupt
STA bit set as “1”
SI terminal
3
BUSY
BUSY
SCK terminal
2
SO terminal
SO3
SI2
1
SCK terminal
SO2
SI2
SO3
SO terminal
SI3
SI terminal
BUSY
Interrupt
1
2
SO0
3
SO1
SI0
4
SO2
SI1
SO3
SI2
SI3
Interrupt
Note: The “H” level of the SCK/SO terminal indicates its pull-up status. In this period this status will be “HZ”.
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8/4 bit
②
The 8/4 bit selects the length of the serial data. The length of the serial data is set at 4 bits when this bit is
“0” and at 8 bits when this bit is “1”. If SIO is started when a serial clock is set as an internal clock, a
clock (4 bits or 8 bits) will be continuously output by the state of this bit.
STA bit set as “1”
SCK terminal
1
2
3
SO0
SO terminal
SO1
SI0
SI terminal
4
5
SO2
SI1
6
SO3
SI2
SI3
7
SO4
SI4
8
SO5
SI5
SO6
SI6
BUSY
SO7
SI7
Interrupt
Example of serial operation for an 8 bit setting
③
SO - I/ O bit
This bit sets the serial I/O for the SO terminal.
The SO terminal outputs serial data when the bit is set at “0”, and is used for serial data input
when this bit is set at “1”. This control is used as a serial bus system for outputting and inputting
serial data through one terminal.
Changing edge
SCK terminal
1
SO terminal
2
SO0
Set STA bit to “1”
Set SO-I/O bit to “0”
3
SO1
1
4
SO2
SO3
SI0
2
SI1
3
SI2
4
SI3
Set STA bit to “1”
Set SO-I/O bit to “1”
Example for serial input-output operation
④
Serial interface operation monitor
The operational status of the serial interface is determined by referencing the BUSY, COUNT, and
SIO F/F bits.
As the BUSY bit becomes “1” during SIO operations, control data switching and serial data access
is performed when the BUSY bit is “0”. It interrupts in falling of BUSY bit and a demand is
published.
The COUNT bit determines whether the sending/receiving of data has been performed in multiples
of four. The bit is set to “0” if shift operation was performed in multiples of four, and to “1” if not. .
The SIO F/F bit is set to “1” when the SCK terminal starts shift operation.
Both COUNT bb it and SIO F/F bits are reset to “0” when “1” is set in the STA bit. These two bits
are mostly used when the SCK terminal sets external clocks (slave mode). An external clock is input
and it can be judged to be the information that serial data was transmitted and received whether
operation was performed normally.
Usually, since interruption is published, interruption processing performs a serial interface end.
⑤
STA bit
STA bit is used to start serial interface operation. Serial operation is started whenever the STA bit is
set to “1”. If the STA bit is set to “1”, serial output data will be transmitted to a shift register, and the
COUNT bit and SIO F/F bit will be reset. A serial clock is output for an internal SCK setting; and a
state of waiting for the serial clock input will take effect in the case of an external setting.
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2. Composition of the Serial Interface 1 (SIO1)
STA
SCK - I/ O
Interrupt requirement
SCK-INV
COUNT
Control circuit
BUSY
45 SCK (P3-3)
SIO F/F
SO - I/ O
edge
44 SO (P3-2)
8/ 4 bit
4 bit shift register
4 bit shift register
SO0 SO1 SO2 SO3
SO4 SO5 SO6 SO7
-3
Serial output data
SI0~SI3
43 SI (P3-1)
SI4~SI7
-2
-1
-0
I/O port-3
I/O control data
Serial input data
-3
-2
-1
-0
I/O port-3 data
Srial interface 1 consists of a control circuit, a shift register, and an I/O Port.
Note: The erminal can be used as I/O Port -3 (P3-1).
Note: The shift memory contents for the data and serial input data are stored by the data memory.
For this reason, the contents of the data set to serial output data and those of the serial input data are not in
agreement.
Note: All serial input terminals are the Schmitt input type.
Note: The output of the SO terminal and the serial clock output of SCK terminal are Nch open drain outputs.
For this reason, connect pull-up resistance. In addition, be sure to use a pull-up potential of 3.6 V or less.
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3. Serial Interface Timing of SIO1 Circuit
The clock frequency output from the SCK terminal when the SCK clock is set as an internal clock is 37.5
kHz (Duty. = 50%). When the SCK clock is as an external input, a clock of a maximum of 200 kHz can be
input.
External clock: Tcyc = 5 µs min, Th = 2.5 µs min, TPLH/TPLL = 2 µs max
Internal clock: Tcyc = 26.6 µs typ., Th = 13.3 µs typ., TPLH/TPLL = 2 µs max
Tcyc
Th
SCK terminal
At internal
clock
26.6 µs
TPLH/TPLL
SO terminal
SO0
SI terminal
a
Y8
Serial input
Data port (φK24)
Y4
Y2
Y1
STA bit
SO1
×
×
×
×
SO2
c
b
a
SO3
d
SO3
a
b
c
SO2
SO3
a
b
d
c
SO1
SO2
SO3
a
b
SO0
SO1
SO2
SO3
a
×: Unfixed
Set “1”
Set “1”
BUSY bit
Interrupt
COUNT bit
SIO F/F bit
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4. Serial Interface 2 (SIO2) control and Data Ports
0 0 0 1 0 0 0 OFS9 = (INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1)
∀CHK8
1 0 1 1 1 1 0 OFS8 = (INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1 ∀ INF0)
∀CHK8
1 0 1 0 0 1 1 OFS7 = (INF14 ∀ INF13 ∀ INF9 ∀ INF8 ∀ INF5 ∀ INF4 ∀ INF0)
∀CHK7
0 0 0 1 1 0 1 OFS6 = (INF15 ∀ INF14 ∀ INF11 ∀ INF10 ∀ INF8 ∀ INF7 ∀ INF5 ∀ INF2∀INF1)
∀CHK6
0 0 1 0 1 0 1 OFS5 = (INF15 ∀ INF14 ∀ INF13 ∀ INF10 ∀ INF9 ∀ INF7 ∀ INF6 ∀ INF4 ∀ INF1 ∀ INF0)
∀CHK5
1 0 1 1 0 1 1 OFS4 = (INF15 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF8 ∀ INF6 ∀ INF4 ∀ INF2 ∀ INF1 ∀ INF0)
∀CHK4
0 0 0 0 1 1 1 OFS3 = (INF13 ∀ INF12 ∀ INF11 ∀ INF9 ∀ INF8 ∀ INF7 ∀ INF4 ∀ INF2 ∀ INF0)
∀CHK3
1 0 1 0 0 0 1 OFS2 = (INF15 ∀ INF14 ∀ INF13 ∀ INF8 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF2)
∀CHK2
0 0 0 0 0 0 0 OFS1 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF1)
∀CHK1
0 0 0 0 0 0 0 OFS0 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF0)
∀CHK0
⎯
194h
000h
1B4h
350h
168h
198h
0FCh
Other data
Note: ∀: EXOR (exclusive logic sum)
0 6 5 4 B 3 2 1
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Y1
φK3B
Y2
Y4
Y8
DEC0 DEC1 DEC2 DEC3
Y1SIO2 Y2
decode Y4
data
7
INF0
INF1
INF2
Y8
INF3
Y1 information
Y2
Y4
SIO2
data 1 Y8
8
INF4
9
INF5
INF6
INF7
Information data
SIO2 information data 2
INF12 INF13 INF14 INF15
Y1 information
Y2
Y4
SIO2
data 4 Y8
B
OFS0/
CHK0
OFS1/
CHK1
OFS3/
CHK3
Y1 offset/Check
Y2
Y4data 1Y8
SIO2
C
OFS4/
CHK4
OFS8/
CHK8
E
Y1
SIO2
Data
8 Select
OFS5/
CHK5
OFS6/
CHK6
OFS7/
CHK7
Y1 Offset/Check
Y2
Y4data 2Y8
SIO2
D
φK3B
OFS2/
CHK2
OFS9/
CHK9
0
Offset/Check data
0
SIO2 Offset/Check data 3
Y2
Y4
Y8
*
*
*
Change of offset/check data
0: Loading of offset data
1: Loading of check data
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The data port of the serial interface 2 (SIO2) is constituted of 16-bit information data (φK3B8~B), 10-bit
check data, 10-bit offset data and 4-bit decoding data (φK3B7). In 26-bit serial data, serial data of 16-bit are
information data and 10-bit are check data. As shown in the above-mentioned table, the data that took the
exclusive logic sum of each bit of 26-bit data turns into offset data. Furthermore, when the offset data is
specialized in the above –mentioned, the data of 1~6h and Bh are output as 4-bit decoding data. Loading
port of check data and offset data (φK3BC~E) are common and selection of loading is SIO2 data Select bit
(φL3B8). If the bit is set to “0”, the offset data will be loaded and set to “1”, the check data will be loaded.
If the data “1” is set to SIOon bit (φL22) and SIO Select bit (φL23), SIO2 will be in a permission state of
operation. If the data “1” is set to STA bit (φL23), 26-bit shift registers are all reset and SI terminal input
state will be serially input one by one by the shift register with the shift clock of SCK terminal clock. If SIO
interruption is permitted at this time, interruption will be published with edge contrary to the shift edge of
a shift clock. SI terminal and SO terminal can be changed to a serial input terminal by the SO-I/O bit, if
the data “0” is set up, SI terminal will serve as a serial data and “1” will be set up, SO terminal will serve
as a serial data input. If SI terminal is selected as a serial input, since SO terminal turns into a SIO1 serial
output terminal, we recommend use of SO terminal to a serial input.
These data is divided and indirect specified set up by the data select port (φL2D). The data of a
specification port to set DAL address port to beforehand is set, and the data port corresponding to it is
accessed. A data selection port is +1 increment by accessing of DAL address port (φKL3B). For this reason,
after setting up a data selection port, it can set up continuously.
Note: The data select port is +1 increment automatically by accessing φL2E, φL2F, φL3B and φK3B on I/O map.
Control and serial data of the serial interface-2 is accessed using an OUT2 instruction for which [CN =
3H] has been specified in the operand.
5. Control and Serial Data of the Serial Interface 2
SIO Interruption
SCK terminal
SI terminal
SI (P3-1) 43
INF15
INF14
CHK3
CHK2
CHK1
CHK0
CHK16
SO - I/ O
Check data
Information data
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SO (P3-2) 44
26 bit shift register
edge
CHK0
CHK1
CHK2
CHK3
CHK4
CHK5
CHK6
CHK7
CHK8
CHK9
INF0
INF1
INF2
INF3
INF4
INF5
INF6
INF7
INF8
INF9
INF10
INF11
INF12
INF13
INF14
INF15
SCK (P3-3) 45
INF16
SIO interruption
EXOR circuit for offset data detection
OFS0~OFS9 (Offset data)
Decode circuit
DEC0~DEC3
(Decode data)
Note: If the SI terminal is used for serial input, the SO terminal will serve as an SIO1 serial output.
When using the SI terminal as a serial input, be sure to set the P3-1 output data to “1” and change it to the
input state.
Note: Serial input is inputt and shifted also SIO1 at the same time.
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○
A/D Converter
The A/D converter is used for measuring the strength of electric fields and the voltage of batteries with
4-channel 6-bit resolution.
1. A/D Converter Control Port and Data Port
φL21
Y1
Y2
Y4
Y8
AD
SEL0
AD
SEL1
AD
SEL2
STA
A/D converter start bit
A/D conversion is performed whenever this bit is set at “1”.
A/D input selection
φK20
SEL2
SEL1
SEL0
ADINPUT
0
0
0
ADin1
0
0
1
ADin2
0
1
0
ADin3
0
1
1
ADin4
1
*
*
Vreg/2
φK21
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
AD0
AD1
AD2
AD3
AD4
AD5
BUSY
0
A/D operation monitor
LSB
A/D Conversion data
MSB
0: A/D conversion ended
1: A/D conversion in progress
A/D converter is the serial comparison systems of 6 bit decomposition ability.
An internal power supply (VDD) is used for the standard voltage of A/D conversion. The voltage dividing
this power supply by 64 and the A/D input voltage are compared, and the data is output to the A/D
conversion data port. The A/D conversion input follows the multiplex method for the four channels of the
external input terminals (ADin1~ADin4 terminal) and the 1/2 potential of the Vreg terminal voltage, and is
selected using bits AD SEL0 to AD SEL2.
The A/D converter performs A/D conversion whenever the STA bit is set at “1”, and this ends after seven
machine cycles (280 µs). The completion of A/D conversion is determined by reference to the BUSY bit, and
the A/D conversion data is loaded into the data memory after conversion has finished.
The result of A/D conversion is obtained through the following calculation.
VDD ×
n − 0.5
64
(63 >
=n>
= 1) <
= A/D input voltage <
= VDD ×
n + 0.5
64
(62 >
=n>
= 0)
(n is the A/D conversion data value. [decimal])
The Vreg/2 to the A/D input is used for battery detection. The Vreg potential is 1.5 V ± 0.15 V and 1/2
potential: 0.75 V ± 0.075 V of Vreg terminal voltage is chosen as A/D input, and VDD potential which is
standard potential can be detected by carrying out A/D conversion of this potential. When VDD potential is
1.5 V, A/D conversion data is set to 20H, and if A/D data goes up and VDD potential serves as 0.75 V as VDD
potential falls, it will serve as 3FH. If this function is used, the VregON bit is set to “1”.
These controls are accessed with an OUT2/IN2 instruction for which [CN = 0H, 1H] has been specified in
the operand.
Note: If the VregON bit is set to “1” , the CPU operating consumption current is increased. The Vreg terminal
also supplies power to the phase comparator.
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2. A/D Converter Circuit Configuration
46 ADin1 (P5-0)
Sample
hold
47 ADin2 (P5-1)
R 3R/2
VDD
Control
circuit
SEL0~2
48 ADin3 (P5-2)
BUSY
R
49 ADin4 (P5-3)
R
STA BUSY
Decoder
AD0
~
AD5
A/D conversion data latch
A/D conversion data
Comparator
R/2
VDB
(VDD × 2 doubler
power supply)
41 Vreg
Constant voltage circuit
BUSY
VregON
To phase comparator
The A/D converter consists of a 6-bit D/A converter, a comparator, an A/D conversion latch and control
circuit. Since the 6-bit D/A converter and comparator part operate only when the BUSY bit is “1”, there is
no A/D converter power when the A/D converter is inoperative. The doubler voltage (twice that of VDD) is
used to drive the A/D converter part.
Note: To the output data of I/O Port -5 (Nch open drain) corresponding to A/D input terminal to use set up “1”
and use it by changing into an input state.
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○
Buzzer Output
The buzzer output can be used to output tones and alarm tones to confirm key operations and the tuning
scan mode. The buzzer type can be selected from a combination of four output modes and eight different
frequencies.
1. Buzzer Control Port
φL1A
Y1
Y2
Y4
Y8
BF0
BF1
BF2
BEN
Buzzer frequency selection data
BF2
BF1
BF0
Buzzer Frequency
Duty
0
0
0
0.625 kHz
1/2
0
0
1
0.75 kHz
1/2
0
1
0
1 kHz
2/3
0
1
1
1.25 kHz
1/2
1
0
0
1.5 kHz
1/2
1
0
1
2.08 kHz
2/3
1
1
0
2.5 kHz
1/2
1
1
1
3 kHz
2/3
Buzzer output enable bit
0: Buzzer output fixed (at POL = “0”, “L” level, POL = “1”, “H” level)
1: Buzzer output enabled
φL1B
Y1
Y2
Y4
Y8
BM0
BM1
BUZR
ON
POL
Buzzer output logic setup
Buzzer output mode setup
0: Positive logic output. Buzzer frequency is output in positive logic from “L” level.
1: Negative logic output. Buzzer output is outputted in negative logic from “H” level.
I/O port-4 and buzzer output selection
0: I/O port-4 (P4-0) selection
1: Buzzer output selection
BM1
BM0
0
0
Continual output
(mode A)
0
1
Staggered output
(mode B)
1
0
10 Hz intermittent output
(mode C)
1
1
10 Hz intermittent output with 1Hz intervals
(mode D)
Buzzer Output Mode
Ports P4-0 I/O are also used for buzzer output. In order to set it as a buzzer output, BUZR ON bit is set
up “1” and it changes to a buzzer output by setting it as an output by the P4-0 I/O control port. After logic
setting up of buzzer frequency, mode setup and a logic setup, buzzer enable bit is set up “1”, it outputs
buzzer. At the time of condition setup, buzzer enable bit is setup “0”.
In continual output mode (mode A), if the buzzer enable bit is set to “1”, the buzzer frequency will be
output continuously; if “0” is set, the buzzer output will stop. In staggered output mode, whenever the
buzzer enable bit is set to “1”, the buzzer is output and stopped at 50-ms intervals.
Under a buzzer output (50 ms), if buzzer enable bit is set to “1” again, the buzzer is extended to 50 ms,
being output for 100 ms.
Given that a further extension of 50 ms to 150 ms is possible, the buzzer time can be set up easily.
In the 10-Hz intermittent output mode (mode C), if the buzzer enable bit is set to “1”, a 50-ms buzzer
output and 50-ms buzzer pause are carried out continuously. A setting of “0” stops the buzzer output.
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10 Hz intermittent output with 1 Hz intervals mode (mode D), if buzzer enable bit is set “1”, 50 ms
buzzer output and 50 ms buzzer pause will carry out 500 ms output, after that 500 ms pause output of 50
ms buzzer output and the 50 ms buzzer pause is carried out again, and this operation is repeated. A set of
“0” stops a buzzer output. At mode B, C, and D, a buzzer is in an output state, even if it sets “0” to buzzer
enable bit and it makes it stop, the buzzer of 50 ms is output and stops. In addition, a buzzer output state
can be judged according to the contents of a timer port. The timer port 10 Hz bit is “0”, buzzer is an output
state and it is in a pause state at the time of “1”.
The control of buzzer is accessed by an OUT 1 instruction for which [CN = AH, BH] has been specified in
the operand.
2. Buzzer Circuit Configuration
10 Hz
Multiplexer
0.625 kHz~3 kHz
1 Hz
Buzzer output circuit
BF0~BF2
28 BUZR (P4-0)
BM0~BM1
BEN
3. Buzzer Output Timing
Buzzer frequency
“1”
“1”
“0”
Data set to BEN bit
10 Hz
Buzzer output (mode A)
Buzzer output (mode B)
During a buzzer output, if “1” is set to BEN bit again, 50 ms extension will be
carried out.
50 ms
Buzzer output (mode C)
Period of buzzer frequency
output
50 ms
Period of non-output
The output state in mode C
Buzzer output (mode D)
500 ms
Period of non-output
500 ms
Period of output
Note: When making the buzzer output function active, be sure to set P4-0 to the input state (by setting the I/O
control port to “1”).
Note: The change of buzzer frequency is updated in modifications of 10 Hz.
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○
Pulse Counter
The pulse counter is an 8-bit up/down counter and detection of the number of clocks can be performed
with PCTRin terminal (CMOS input type) used also HOLD terminal. It can use for the count and detection
of a tape run.
1. Pulse Counter Control Port, Data Port
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
DAL Address data
φL3B
DAL Address data
Y1
Y2
Y4
Y8
Y1
DA0
Y2
DA1
Y4
DA2
Y8
DA3
Y1 Address
Y2 data
Y4 1
DAL
0
Y8
Y1 Address
Y2 data
Y4 2
DAL
1
2
φK3B
Y8
Y8
Y8
DA3
Y1 Address
Y2 data
Y4 1
DAL
CTR OVER
RESET RESET
3
5
DAL Address data 4
*
*
PC0
4
PC1
PC2
PC3
Pulse counter data
*
PC4
PC5
PC6
PC7
Data
5
Pulse counter control
Pulse counter data
OVER
6
•
Y8
DAL Address data 3
Pulse counter control
Control
Y8
Y1 Address
Y2 data
Y4 2
DAL
2
*
DOWN POL
Y4
Y4
DA2
1
DAL Address data 4
4
Y2
Y2
DA1
0
DAL Address data 3
3
Y1
Y1
DA0
0
0
0
Pulse counter control
DOWN bit............................. Set up 8 bit up/down counter
0: Up count action
1: Down count action
•
POL bit................................. Set up input terminal (PCTRin terminal) counter input edge
0: Cont for input fallig edge
1: Count for input rising edge
•
•
CTR RESET bit .................... whenever it set to “1”, a 8-bit rise down counter is reset.
OVER RESET bit ................. whenever it set to “1”, OVER F/F is reset.
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
2
0
LSB
2
MSB
Pulse counter data
OVER
7
OVER F/F bit ................. Detected of overflow
8
0: Counter calculation value <
=2 −1
8
1: Counter calculation value >
=2
(Overflow status)
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The pulse counter measures the number of pulses in the PCTRin input terminal.
POL bit set up the clock edge of input terminal. If “0” is set, it will count in the falling of an input and it
will set to “1”, it will count in the rising of an input. Usually, this bit is used fixed.
DOWN bit sets up a up/down of 8-bit counter. If it sets to “0” and it will set to rise count operation and
“1”, down count operation will be done. A change of a rise/down can be performed freely. However, if a clock
pulse is input during change command execution, since it is canceled, be careful of this count.
When 28 or more pulses are input, OVER F/F bit is set to “1”. When performing count operation of 8-bits
or more, this OVER F/F are detected, and on a data memory, only the number of times of overflow is added
and subtracted, and can correspond. After detection by this bit, and OVER RESET bit is set “1” and OVER
F/F is reset. The CTR RESET bit resets only the 8-bit counter. The counter is reset whenever this bit is set
to “1”.
Counter data loaded data in a data memory by the binary.
The control of pulse counter and data loading is accessed using the OUT3/IN3 instructions for which [CN
= BH] have been specified in the operand and arranges in DAL address register port. This port is set up by
data select port (φL2D), which specified the division. The data of a specification port to set beforehand is set
and the data port corresponding to it can be accessed. The data select port is +1 increments whenever it
accesses DAL address port (φL3B, φK3B). For this reason, after setting up a data selection port, it can set
up continuously.
Note: If POL bit is changed, a clock pulse may enter. Reset data by the reset bit after changing.
Note: If data select port is +1 increments whenever it accesses φL2E, φL2F, φL3B, φK3B on the I/O map.
2. Pulse Counter Circuit Configuration
OVER
RESET
CTR
RESET
To interrupt circuit
DOWN
F/F
34 HOLD (PCTRin)
8-bit up/down counter
POL
OVER
F/F
PC0~PC7
Note: It can be used together as pulse counter and interrupt function ( HOLD terminal input).
3. Example for Pulse Counter Timing
CTR/OVER RESET
execution
Data set to pulse counter
control bit
OVER
RESET execution
DOWN bit
set to “1”
Pulse width 1 µs (min)
DOWN bit
PCTRin input
Counter data
01H
02H
03H
FFH
00H
01H
02H
N
N+1 N−1 N−2
OVER F/F
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○
Input and Output Port (I/O Port)
There are 28 I/O ports available between I/O ports 1~5, 8-9 of which are used to input and output control
signals. Of these 28 I/O ports, 12 I/O ports are CMOS type and 16 I/O ports are Nch open drain type. The
combination function and the functional features of each I/O port are as follows.
I/O Port
Combination and Additional Function
Structure
It is possible to set pull-up/pull-down.
I/O port-1
But, a combination of pull-up pull down is not
available.
CMOS
⎯
P2-0~-2
I/O port-2
P2-3
Prescaller PSC output
⎯
P3-0
I/O port-3*
P3-1~3
Serial interface input/output port
P4-0
Nch open
drain
Buzzer output
I/O port-4
CMOS
P4-1~3
I/O port
6-bit A/D converter analog input
I/O port-5
The potential to VDB (VDD × 2) can be input.
I/O port-8
Nch open
drain
The potential to VLCD (3 V) can be input.
I/O port-9
Note: I/O port-3 terminal of * markis Nch high output buffer output and output-proof is 3.6 V (max).
1. I/O Port Control, I/O Port Data
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Segment-2 data
φL2F
Y1
Y2
Y4
Y8
S11
S12
S13
S14
6
Y1Segment
Y2 /IO select
Y4
Y8
Segment and I/O port changing
S15
7
8
S16
Y8
-0
-3
-1
-0
Y1
-0
A
S18
Y1Segment
Y2 /IO select
Y4
Y1
9
S17
-2
I/OY2
control-1
Y4
-1
-2
I/OY2
control-2
Y4
-1
-2
0: I/O port
1: Segment output
Y8
-3
Y8
-3
I/O control data (Input/output setting)
0: I/O port input
1: I/O port output
I/O control-4
Note: I/O-1, I/O-2, - - - - - is correspond to the name of P1-0~-3, P2-0~-3, - - - - - terminal.
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Y1
φLK30
φLK31
φLK32
φLK33
φLK34
Y2
Y4
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-1
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-2
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-3
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-4
Y8
-0
-1
-3
-2
φL20
Y1
Y2
Y4
Y8
PD0
PD1
PD2
PD3
I/O port pull-down
Control pull-down or pull-up of I/O port-1
0: Pull-up or pull-down off
1: Pull-up or pull-down on
Note: PD0~PD3 is correspond to P1-0~P1-3
I/O port data
Y1
I/O port-5
Y2
φL3A
φLK37
φLK38
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-8
Y8
-0
-1
-3
-2
Y4
Y8
Port 1
Pull up
Control bit of pull-up/pull-down of I/O port-1
0: Set up pull-down
1: Set up pull-up
I/O port-9
CMOS I/O port
0: I/O terminal “L” level
1: I/O terminal “H” level
Nch open drain
I/O port
0: I/O terminal “L” level
1: I/O terminal “H” level
output terminal is high impedance
The I/O port for the I/O ports is set with the contents of the I/O control data port. “0” is set in the I/O
control data port bit which corresponds to the relevant port when setting the input port, and “1” is set when
setting the output port.
I/O control data port is arranged segment-2 data port and set up by data select port (φL2D), which
specified the division. The data of a specification port to set beforehand is set and the data port
corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL
address port (φL2F). For this reason, after setting up a data selection port, it can set up continuously.
The output status of the I/O port is controlled by executing the OUT3 instruction for which corresponds
to each I/O port during output port setting. The contents of the data currently output can also be loaded
into the data memory by executing the IN3 instruction. In addition, the data read by the IN3 command is
not surely in agreement with the data output by the OUT3 instruction and, in order to read the state of a
terminal.
The data input in the I/O port is loaded into the data memory by executing the IN3 instruction which
corresponds to each I/O port during input port setting. The contents of the output latch will have absolutely
no effect on the input data at this point.
Nch open drain I/O ports have not I/O control data. When it makes an input, it is set “1” in I/O data port,
the status becomes high impedance and read the input status into data memory by IN3 instruction. When
output state becomes "L" level, it set “0” in I/O data port by OUT3 command.
The execution of the WAIT instruction and CKSTP instruction is cancelled and CPU operations are
re-started when the status of the I/O port input specified in the input port changes with I/O port-1. Also,
the MUTE port and MUTE bit are forcibly set to “1” during changes in the input status when the MUTE
port’s I/O bit is set at “1”. By control port of I/O port-1 pull-down, it sets up pull-down or pull-up status. It
can set up a pull-down or pull-up for every terminal and if the port is set up “1”, it will become a pull-up or
a pull-down. The pull-up/pull down control bit of I/O Port -1 perform a change of a pull-up and a pull down.
The status is pull-down if the bit is set to “0”, and pull-up if the bit is set to “1”
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Set up the pull-up and pull-down is used for key matrix configuration. I/O Port -1 with a pull down or a
pull-up is considered for a usual I/O Port output as an input as an output of a key matrix, and a key matrix
is constituted. It is able to constitute of the key matrix of a low noise by the following methods. In setting
pull-down to I/O port-1, the output side of a key matrix is usually high impedance (input state), output and
scan to “H” level on key loaded line, detected key input or non by loading input status of I/O port-1. In the
case of a pull-up, “L” level is output and it detected on a key loading line. During executing of CKSTP
instruction and WAIT instruction, the existence of this key input can also be judged and re-started. When
re-starting at the time of CKSTP command execution, I/O Port -1 is used by changing into a pull-up state.
For the clock stop mode, since the outputs of an I/O Port are output all “L” level, I/O Port -1 stands by in
the state of a pull-up, and if a key is input, I/O Port -1 input will change and re-start. In this case, since the
standby time of about 100 ms occurs as time lag after being canceled of a clock stop. Since release of WAIT
instruction holds the output state, re-starting is possible by the method of both a pull-up and a pull down,
and since there is no time lag from release, detection and operation of a key are quickly possible. Using
these backup modes together can reduce consumption current.
Since the input of I/O Port -1 is an inverter input, the usage that serves as middle potential cannot be
done to this input. But, only at the time of execution of the input instruction, since an input will be in an
ON state, even if middle potential is input, as for other I/O Port inputs, unusual consumption current does
not occur. For this reason, use of the pull-up in potential lower than VDD potential, the three value output
of an output level, etc. is possible.
I/O Port -2, -4 terminals are the I/O Ports of CMOS structure, P2-3 terminal is the prescaler PSC output,
P4-0 terminal is the buzzer output and P3-1-3 terminals are the serial interface serve a double purpose,
respectively. I/O port-3, -5, -8~-9 are Nch open drain I/O port.
I/O Port -3 uses VLCD (3 V) for the gate potential of Nch output buffer. For this reason, the output current
by which power supply voltage was stabilized also in the time of low voltage can be obtained. This port can
perform the input and output to 3.6 V.
I/O port-5 is used as 6-bit A/D converter input. This port is able to input VDB potential (the potential to
VDD × 2).
I/O Port -8, -9 are using also LCD driver. VLCD (3 V) is used for the gate potential of an Nch open output
buffer. For this reason, the output current by which power supply voltage was stabilized also in the time of
low voltage can be obtained. These terminals can perform the input and output to VLCD (3 V). These
terminals are set as the input of an I/O Port after reset.
Note: The data select port is +1 increments automatically when it accesses φL2E, φL2F, φL3B, φK3B on the
I/Omap.
VDD
P1-3
26
P1-2 25
The following is an example of key input matrix circuit
configuration. Without key input, it pulled-up and key is
pushed, it input “L” level from souce side(I/O port-9).
It is necessary to take into consideration the shift time to
the pull-up of a key input from “L”. They are all about a key
souce side at the time of WAIT instruction execution and
“L” WAIT instruction can be lifted, whenever a key input
will be pushed, if it stands by on the level.
P1-1 24
P1-3
P1-0 23
P1-2
P9-3
22
P1-1
P9-2 21
P1-0
P9-1 20
Pull-up
Pull-up
Pushing of P9-3 and P1-1 keys
Pull-up
High impedance
P9-3
P9-0 19
P9-2
P9-1
Example for key input matrix circuit
P9-0
I/O port-1
Loaded into data
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TC9329AFAG/AFCG
○
Register Port
The G-register and data register outlined in the explanation on the CPU are also used as a single
internal port.
1. G-register (φKL1D, φKL1E)
This register addresses the data memory’s row addresses (DR = 04H~3FH) during execution of the
MVGD instruction and MVGS instruction. The register is accessed using an OUT1/IN1 instruction for
which [CN = DH~EH] has been specified in the operand. Moreover, if STGI instruction is used, data can be
set to this register using a single instruction.
Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are
executed and are ineffective when any other instruciton is executed. Moreover, this register is not
affected by MVGD instruction and MVGS instruction.
Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 3FH in the
G-register. (DR = 00H~3FH)
Note: For a reason with a RAM capacity of 256 words, this product will become unfixed if 10H-3FH is specified
to be G-register.
Note: Writing and read-out are possible for this register. Please evacuate and return in a data memory if
needed at the time of interruption.
φKL1E
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
G0
G1
G2
G3
G4
G5
*
*
Data memory row address specification
STGI instruction
I0
I1
Transmit
I2
I3
I4
G5
G4
G3
G2
G1
G0
DR
0
0
0
1
0
0
04H
0
0
0
1
0
1
05H
0
0
0
1
1
0
06H
0
1
1
1
1
1
0FH
1
0
0
0
0
0
10H
1
1
1
1
1
0
3EH
1
1
1
1
1
1
3FH
I5
I*
69
Can’t specified in this area
φKL1D
2006-03-02
TC9329AFAG/AFCG
2. Data Register (φKL3C~φKL3F), DAL Address Register (φKL3B0~φKL3B3) and Control
Bit
φL2D
Y1
SEL1
φL/K3A
φL/K3B
Y2
SEL2
Y4
SEL4
Y8
Y1
Y2
Y4
Y8
φY1
L/K3B
Y4
DALY2
address1
SEL8
Y4
Y8
DAL
(data)
→ DA/0
/0
/0
DA4Y1 DAL
DA5Y2
アドレス
DA6Y41DA7Y8
1
Data select
Y2
Y8
アドレス
DA0Y1 DAL
DA1Y2
DA2Y41DA3Y8
0
Y1
2
DA8
DAL
DA9 アドレス
DA10 1DA11
*/0
3 DA12 DA13
0: DAL ADD3, (r) instruction select
1: DAL DA instruction select
*/0
DAL address register
DA13 DA12
DA11 DA10
DA9
MSB
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
LSB
DAL instruction indirect specification
Whenever it sets “1”, the contents of a data register
are transmitted to DAL address register.
φKL3F
φKL3E
φKL3D
φKL3C
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
d15
d14
d13
d12
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
MSB
LSB
Data register 16-bit data
It transmits 16 bits of program memories by DAL instruction
b15
b14
b13
b12
b11
b10
b9
b7
b8
b6
b5
b4
b3
b2
b1
b0
Program memory 16-bit data
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TC9329AFAG/AFCG
The data register is 16-bit register for which load the program memory data when the DAL instruction is
executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of
the OUT1/IN1 instructions for which [CN = CH~FH] has been specified in the operand. This register can be
used for loading LCD segment decoding operations, radio band edge data and the data related to binary to
BCD conversion.
The DAL address register (DA) is 14-bit register for which specified the program memory indirectly when
the DAL instruction is executed. There are 2 kinds of operation methods of DAL instruction. The control
is selected by DAL bit. When DAL bit is set “0”, ADDR3 (6 bit) of the operand and contents of general
register (r) becomes the reference address of program memory and when DAL bit is set “1”, 14 bit of DAL
address register becomes reference address. At the time of setting DAL bit is “0” and execution of DAL
instruction, only program memory area (0000H~03FFH) becomes reference area and DAL bit is set “1” and
execution of DAL instruction, all program memory area (0000H~3FFFH) becomes reference area.
If (DATA) → DA bit is set to “1”, it can transfer from the contents of data register to 14 bit DAL address
register by executing of single instruction.
The contents of DAL address register are accessed the data in 4-bit units with the execution of the
OUT3/IN3 instruction for which [CN = BH] have been specified in the operand. DAL address register port
is setup by data select port (φL2D) for which divides and indirect specified. The data of a specification port
to set beforehand is set and the data port corresponding to it is accessed. Data select port is +1 incremented
whenever is accessed this port(φL3B, φK3B). For this reason, after setting up a data selection port, it can
access continuously.
DAL bit and (DATA) → DA bit are accessed with the execution of OUT3/IN3 instruction for which [CN =
AH] has been specified in the operand.
Note: DAL address register becomes effective only execution of DAL instruction when setting “1” and becomes
unrelated at the time of other instruction execution. It does not have the influence on this register by DAL
instruction.
Note: For this product have 4 k step of ROM Capacity, If 1000H - 3FFFH is specified to be DAL address
register and DAL instructiion is executed, the contents of a data register will become unfixed.
Note: It’s possible to write in and read out for data register and DAL address register. Please evacuate and
return in a data memory if needed at the time of interruption.
Note: It’s no action when (DATA) → DA bit is set “0” . When it accesses to φK3A, it only read out only the DAL
bit. (The other bit is “0”.)
3. Carry F/F (Ca flag, φKL1C)
This is set when either Carry or Borrow are issued in the result of calculation instruction execution and
is reset if neither of these is issued. The carry F/F is accessed with OUT1/IN1 instructions for which [CN =
CH] have been specified. For this reason, evacuation and a return of the carry F/F at the time of
interruption can be performed easily. Carry F/F is written in a data memory by IN1 instruction at the time
of evacuation, it is evacuated, and the data evacuated by OUT1 instruction is transmitted to carry F/F from
a data memory at the time of a return.
φL/K1C
Y1
Y2
Y4
Y8
CA
flag
*/0
*/0
*/0
Carry F/F
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TC9329AFAG/AFCG
○
Timer Port
The timer is equipped with 100 Hz, 10 Hz and 2 Hz F/F bits and is used for counting clock operations and
tuning scan mode, etc.
1. Timer Port
φL26
Y1
Y2
2 Hz
F/F
Timer
Y4
Y8
The 10 Hz, 100 Hz and under 1 kHz bits are reset
whenever “1” is set.
Reset port
The 2 Hz is reset whenever “1” is set.
Y1
φK26
Y2
2 Hz
F/F
Y4
Y8
10 Hz 100 Hz
Timer
The timer ports are accessedusing an OUT2 instruction for which [CN = 6H] has been specified in the
operand.
2. Timer Port Timing
The 2-Hz timer F/F is set with the 2 Hz (500 ms) signal and is reset by setting “1” in the 2-Hz F/F of the
reset port. This bit is usually used as a clock counter.
The 2-Hz timer F/F can only by reset with the 2-Hz F/F of the reset port, and incorrect counts will be
output and correct timers not acquired if not reset within a 500 ms cycle.
2 HzF/F output
2 HzF/F reset execution
t < 500 ms
2 Hz clock
t
500 ms
The 10 Hz and 100 Hz timers are output to 10 Hz and 100 Hz bits will respective cycles of 100 ms and 10
ms and a pulse of duty 50%. Counters at 1 kHz or below will be reset whenever the reset port’s timer bit is
set at “1”.
100 Hz
5 ms
10 ms
10 Hz
50 ms
100 ms
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TC9329AFAG/AFCG
○
Output Port (Both as LCD Driver Terminal)
There are 14-output ports of 14 CMOS type. These output ports are used as LCD driver and changed
output port by VLCD OFF bit. If VLCD OFF bit is set to “1”, this port becomes output port. The output data
to output port is used as segment data port-1 (φL2E). This data is accessed with OUT2 instruction for
which [CN = EH] is specified and is setup by data select port ( φL2D) for which divides and indirect specified
as same as segment data. The data of a specification port to set a segment data port to beforehand is set,
and the data port corresponding to it is accessed. The data select port is +1 incremented whenever is
accessed segment data port-1 (φL2E). For this reason, after setting up a data selection port, it can set up
continuously.
Output data is +1 increment with OT count UP bit by executing one instruction. For this reason, it can be
used as an address signal output when using an external memory etc. Output buffer capability can be
changed at the time of an output setup. If OTB-UP bit is set “0”, it becomes low output buffer (same
performance of LCD output driver) and set “1”, it becomes high output buffer. During output port setup,
this bit is usually set to “1”.
The power supply of this output port is used VLCD doubler potential, when using it as an output port,
remove for the capacitor of VLCD doubler potential (between C3-C4) and connect with VDD terminal and
use VLCD terminal.
Note: Data select port is +1 increment automatically whenever is accessed φL2E, φL2F, φL3B, φK3B on I/O
map.
Note: If set “0” to OT count UP bit, it’s not performed count-up.
Note: Refer to LCD driver item.
φL2D
Y1
SEL1
φL2E
Y2
SEL2
Y4
SEL4
Y8
Y1
SEL8
Y4
2
OT9
Y2
Y4
Y8
OT
count
up
If VLCD off-bit is set “1”, segment output
data will turn into output port data.
OT10
DAL アドレス
OT11 1OT12
3 OT13 OT14
Y1
Y8
アドレス
OT5Y1 DAL
OT6Y2
OT7Y41OT8Y8
1
φL3A
Y8
アドレス
OT1Y1 DAL
OT2Y2
OT3Y41OT4Y8
0
Data select
Y2
φY1
L/K3B
Y2 port data
Y4
Output
*
*
In this bit whenever is set “1”, all the OT1 - OT14 is
count up (+1).
OT1 bit is lower bit; OT14 bit is upper bit and count up
from OT1 bit.
φL2FF
Y1
Y2
Y4
Y8
Control bit for output port (OT) buffer performance
OTB
-UP
0: Low output buffer
1: High output buffer
73
At set up output port, it set to “1”.
2006-03-02
TC9329AFAG/AFCG
○
MUTE Output
This is a dedicated 1-bit CMOS output port for muting control purposes.
1. MUTE Port
φL/K18
Y1
Y2
Y4
Y8
MUTE
I/O
POL
HOLD
Control by change of HOLD input state changing
0: Even if HOLD input status changes, MUTE output does not change.
1: By changing HOLD input status, MUTE bit is set to “1”.
MUTE output polarity control
0: Positive logic: MUTE bit output without modification
1: Negative logic: MUTE bit inversed and output
Control selection by changes in the I/O port-1input status
0: MUTE output not amended when changes in I/O port-1input status exist
1: MUTE bit set at “1” when changes in I/O port-1 input status exist
MUTE output setting
0: MUTE output set at “L” level during positive logic and “H” level during negative logic.
1: MUTE output set at “H” level during positive logic and “L” level during negative logic.
This port is accessed using an OUT1/IN1 instruction for which [CN = 8H] has been specified in the
operand. The MUTE output is used for muting control. This function prevents noise from being generated
during linear circuit switching when band is performed with the I/O port-1 or HOLD input. This control
is set up according to the contents of I/O bit and HOLD bit. POL bit sets up the logic of MUTE output.
Please set up according to specification.
2. Circuit Composition of MUTE Output
MUTE bit
32 MUTE
S
POL bit
HOLD bit
I/O bit
Signal of input change of I/O Port -1
Signal of HOLD input terminal changing
Reset signal
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2006-03-02
TC9329AFAG/AFCG
○
Test Port
Access is performed using an OUT1 instruction for which [CN = FH] has been specified in the operand,
and an OUT2 instruction for which [CN = 6H] has been specified in the operand. “0” is usually set with the
program.
φL1F
φL26
Y1
Y2
Y4
Y8
#0
#1
#2
#3
Y1
Y2
Y4
Y8
#4
Test port
Test
port
If the following data is set as test port from #3 to #0, various signals can be made to output from MUTE
terminal.
○
0
MUTE output
0
0
0
1
1
Programmable counter frequency
0
0
1
0
2
Reference frequency
~
0
Prohibition
0
1
0
1
5
CR VCO frequency
~
0
~
0
~
0
~
MUTE Terminal Output
~
Data
~
#0
~
#1
~
#2
~
#3
1
1
1
1
F
Prohibition
Application to an Emulator Chip
If TEST terminal is supplied “H” level (test mode), the device operates as an emulator chip. Three kinds
of test modes are abailable and can constitute a soft development tool by using three devices.
Radio operation can be checked by the connection between this soft development tool and IC for tuners,
performing soft development.
Please refer to TC932AFAG/AFCG software development tool specifications of a development tool.
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TC9329AFAG/AFCG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Supply voltage
VDD
−0.3~4.0
V
Voltage doubler boosting voltage
VDB
−0.3~4.0
V
Output voltage 1
(N-channel open drain)
VO1 (*)
−0.3~4.0
V
Output voltage 2
(N-channel open drain)
VO2 (*)
−0.3~VDB + 0.3
V
Output voltage 3
(N-channel open drain)
VO3 (*)
−0.3~VLCD + 0.3
V
Input voltage
VIN
−0.3~VDD + 0.3
V
Power dissipation
PD
100
mW
Operating temperature
Topr
−10~60
°C
Storage temperature
Tstg
−65~150
°C
*: VO1: P3-0~P3-3 pin
VO2: P5-0~P5-3 pin
VO3: P8-0~P8-3, P9-0~P9-3 pin
Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = 1.5 V)
Characteristics
Symbol
Test
Circuit
VDD1
⎯
Under CPU operation
VDD2
⎯
Under PLL operation
VHD
Min
Typ.
Max
(*)
0.9
~
1.8
(*)
0.9
~
1.8
⎯
Crystal oscillation stopped
(CKSTP instruction executed)
(*)
0.75
~
1.8
V
IDD1
⎯
PLL operation (VHF mode),
at input FMin = 230 MHz
⎯
6
10
mA
IDD2
⎯
Under CPU operation only
(PLL off, display turned on,
Vreg Off)
⎯
40
80
IDD3
⎯
Under CPU operation only
(PLL off, display turned on,
Vreg On)
⎯
50
⎯
IDD4
⎯
In Hard wait mode,
(PLL off, crystal oscillator
operating only)
⎯
20
40
IDD5
⎯
At Soft wait executed,
(PLL off, CPU stopped)
⎯
30
⎯
IDD6
⎯
Under CPU accelerated
operation, (CR oscillator
operation, PLL off, display on)
⎯
250
500
Memory retention current
IHD
⎯
Crystal oscillation stopped
(CKSTP instruction executed)
⎯
0.1
1.0
µA
Crystal oscillation frequency
fXT
⎯
⎯
75
⎯
kHz
Crystal oscillation start-up time
tst
⎯
Crystal oscillation fXT = 75 kHz
⎯
⎯
1.0
s
⎯
VDD = 1.1~1.8 V,
Ta = −10~60°C
0.8
1.0
1.2
MHz
Range of operating supply voltage
Range of memory retention voltage
Operating current
CR oscillation frequency
*:
fCRW
Test Condition
(*)
Unit
V
µA
Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
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2006-03-02
TC9329AFAG/AFCG
Voltage Doubler Boosting Circuit
Symbol
Test
Circuit
Doubled voltage
VDB
⎯
GND reference (VDB)
Doubled voltage output current
IDB
⎯
Doubled voltage reference voltage
VEE
Constant voltage for phase
comparator
Characteristics
Test Condition
Min
Typ.
Max
Unit
⎯
VDD
×2
⎯
V
VOH = VDB − 0.1 V (VDB)
−50
−200
⎯
µA
⎯
GND reference (VEE)
1.35
1.50
1.65
V
Vreg
⎯
GND reference (Vreg)
1.35
1.50
1.65
V
Constant voltage temperature
characteristic
Dv
⎯
GND reference (VEE)
―
−5
⎯
mV/°C
Power supply output current for phase
comparator
Ireg
⎯
VOH = Vreg − 0.1 V (Vreg)
(Note 1)
−50
−200
⎯
µA
Doubled voltage
VLCD
⎯
GND reference (VLCD)
2.7
3.0
3.3
V
Doubled voltage output current
ILCD
⎯
VOH = VLCD − 0.1 V (VLCD)
(Note 1)
−50
−200
⎯
µA
(*)
*: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
Note 1: The “H” level output current of the pin using the Vreg/VLCD power supply must not exceed the power supply
(doubled voltage: VDB) output current.
Programmable Counter/IF Counter Operating Frequency Range
Symbol
Test
Circuit
OSCin (VHF mode)
f VHF
⎯
OSCin (FM mode)
f FM
⎯
f HF1
⎯
f HF2
⎯
Characteristics
Test Condition
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
f LF
⎯
IFin1, IFin2
f IF
⎯
PSC transfer delay time
tpd
⎯
(*)
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
OSCin (HF mode)
OSCin (LF mode)
(*)
(*)
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
(*)
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
(*)
VIN = 0.1 Vp-p,
VDD = 0.9~1.8 V
(*)
CL = 15 pF,
VDD = 1.1~1.8 V (PSC)
(*)
Min
Typ.
Max
Unit
80
~
230
MHz
60
~
130
MHz
3.0
~
30
1.0
~
10
0.5
~
8
MHz
0.3
~
12
MHz
―
―
400
ns
Min
Typ.
Max
Unit
MHz
*: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
Programmable Counter/IF Counter Input Amplitude Range
Symbol
Test
Circuit
OSCin (VHF mode)
V VHF
―
Same as for f VHF
(*)
0.1
~
0.6
Vp-p
OSCin (FM mode)
V FM
―
Same as for f FM
(*)
0.1
~
0.6
Vp-p
OSCin (HF mode)
V HF
―
Same as for f HF1~2
(*)
0.1
~
0.6
Vp-p
OSCin (LF mode)
V LF
―
Same as for f LF
(*)
0.1
~
0.6
Vp-p
IFin1, IFin2
V IF
―
Same as for f IF
(*)
0.1
~
0.6
Vp-p
Characteristics
Test Condition
*: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
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2006-03-02
TC9329AFAG/AFCG
LCD Common Output/Segment Output (COM1~COM4, S1~S18)
Characteristics
Symbol
Test
Circuit
IOH1
⎯
IOH2
Min
Typ.
Max
VLCD = 3 V,
VOH = VLCD − 0.3 V
(COM1~COM4)
−0.10
−0.20
⎯
⎯
VLCD = 3 V,
VOH = VLCD − 0.3 V (S1~S18)
−0.05
−0.10
⎯
IOL1
⎯
VLCD = 3 V, VOL = 0.3 V
(COM1~COM4)
0.10
0.30
⎯
IOL2
⎯
VLCD = 3 V, VOL = 0.3 V
(S1~S18)
0.05
0.15
⎯
VBS
⎯
No load (COM1~COM4)
1.35
1.5
1.65
V
Min
Typ.
Max
Unit
VLCD = 3 V,
VOH = VLCD − 0.3 V
(Note 2, except I/O port)
−1.5
−3.0
⎯
“H” level
Output current
“L” level
Output voltage 1/2 level
Test Condition
Unit
mA
Output Port, I/O Port (OT1~OT14, P8-0~P8-3, P9-0~P9-3)
Symbol
Test
Circuit
“H” level
IOH3
⎯
“L” level
IOL3
⎯
VLCD = 3 V, VOL = 0.3 V
1.5
3.0
⎯
ILI
⎯
VIH = VLCD, VIL = 0 V
(P8-0~P8-3, P9-0~P9-3)
⎯
⎯
±1.0
“H” level
VIH1
⎯
(P8-0~P8-3, P9-0~P9-3)
VDD
× 0.8
~
VDD
“L” level
VIL1
⎯
(P8-0~P8-3, P9-0~P9-3)
0
~
VDD
× 0.2
Characteristics
Output current
Input leak current
Test Condition
Input voltage
mA
µA
V
Note 2: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using the Vreg/VLCD power supply do not exceed the power supply (doubled voltage:
VDB) output current.
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2006-03-02
TC9329AFAG/AFCG
I/O Port (P1-0~P5-3)
Characteristics
Symbol
Test
Circuit
IOH4
⎯
IOH5
Min
Typ.
Max
VDD = 1.5 V,
VOH = VDD − 0.2 V
(I/O port P2, P4)
−0.4
−0.8
⎯
⎯
VDD = 0.9 V,
VOH = VDD − 0.2 V
(I/O port P2, P4)
−0.04
−0.2
⎯
IOL4
⎯
VDD = 1.5 V, VOL = 0.2 V
(except I/O port P3)
0.5
1.0
⎯
IOL5
⎯
VDD = 0.9 V, VOL = 0.2 V
(except I/O port P3)
0.1
0.3
⎯
IOL6
⎯
VDD = 0.9~1.8 V, VOL = 0.2 V
(I/O port P3)
1.0
2.0
⎯
⎯
VIH = VDD, VIL = 0 V
(I/O port P1, P2, P4)
⎯
⎯
±1.0
⎯
VIH = 3.6 V, VIL = 0 V
(I/O port P3)
⎯
⎯
±1.0
⎯
VIH = VDB, VIL = 0 V
(I/O port P5)
⎯
⎯
±1.0
VIH2
⎯
except I/O port 3
VDD
× 0.8
~
VDD
VIH4
⎯
I/O port 3
VDD
× 0.8
~
3.6
VIL2
⎯
⎯
0
~
VDD
× 0.2
Input pull-down resistor
RIN1
⎯
When P1-0~P1-3 are set to
pull-down or pull-up
30
60
120
kΩ
SCK clock external input frequency
fSIO
⎯
When I/O port P3-3 are set to
serial clock input
⎯
⎯
200
kHz
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
IOH4
⎯
VDD = 1.5 V,
VOH = VDD − 0.2 V
−0.4
−0.8
⎯
IOH5
⎯
VDD = 0.9 V,
VOH = VDD − 0.2 V
−0.04
−0.2
⎯
IOL4
⎯
VDD = 1.5 V, VOL = 0.2 V
0.5
1.0
⎯
IOL5
⎯
VDD = 0.9 V, VOL = 0.2 V
0.1
0.3
⎯
Min
Typ.
Max
Unit
µA
“H” level
Output current
“L” level
Input leak current
ILI
Test Condition
“H” level
Input voltage
“L” level
Unit
mA
µA
V
MUTE Output
Characteristics
“H” level
Output current
“L” level
mA
HOLD , INTR1/2, IN1/2 Input Port, RESET Input
Characteristics
Input leak current
Symbol
Test
Circuit
ILI
⎯
Test Condition
VIH = VDD, VIL = 0 V
⎯
⎯
±1.0
~
VDD
~
VDD
× 0.2
“H” level
VIH3
⎯
⎯
VDD
× 0.8
“L” level
VIL3
⎯
⎯
0
Input voltage
V
Note 2: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB)
output current.
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2006-03-02
TC9329AFAG/AFCG
A/D Converter (ADin1~ADin4)
Characteristics
Analog input voltage range
Resolution
Conversion total error
Analog input leak
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
VAD
⎯
⎯
0
~
VDB
V
VRES
⎯
⎯
⎯
6
⎯
bit
⎯
⎯
⎯
ILI
⎯
Symbol
Test
Circuit
IOH4
⎯
⎯
±0.5
±1.0
LSB
VDD = VDB, VIH = VDB,
VIL = 0 V
⎯
⎯
±1.0
µA
Test Condition
Min
Typ.
Max
Unit
−0.4
−0.8
⎯
DO Output
Characteristics
Output current
“H” level
Vreg = 1.5 V,
VOH = Vreg − 0.2 V
(Note 2)
mA
IOL4
⎯
Vreg = 1.5 V, VOL = 0.2 V
0.5
1.0
⎯
ITL
⎯
VDD = 1.5 V, VTLH = 1.5 V,
VTLL = 0 V
⎯
⎯
±100
nA
Symbol
Test
Circuit
Min
Typ.
Max
Unit
Input pull-down resistance
RIN2
⎯
(TEST)
5
10
30
kΩ
XIN amp. feedback resistance
RfXT
⎯
(XIN-XOUT)
⎯
20
⎯
MΩ
XOUT output resistance
ROUT
⎯
(XOUT)
⎯
4
⎯
kΩ
⎯
VHF mode, FM mode
(OSCin)
100
200
400
⎯
HF mode, LF mode (OSCin)
300
600
1200
⎯
(IFin1, IFin2)
300
600
1200
“L” level
Output off leak current
Others
Characteristics
Input amp. feedback resistance
RfIN1
RfIN2
Test Condition
kΩ
Note 2: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB)
output current.
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2006-03-02
TC9329AFAG/AFCG
Package Dimensions
Weight: 0.32 g (typ.)
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2006-03-02
TC9329AFAG/AFCG
Package Dimensions
Note: Lead type SN-Ag
Weight: 0.26 g (typ.)
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2006-03-02
TC9329AFAG/AFCG
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2006-03-02