TOSHIBA TC9349AFG

TC9349AFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9349AFG
Single-Chip DTS Microcontroller (DTS-21)
The TC9349AFG is a single-chip DTS microcontroller for portable audio
incorporating a 30 MHz prescaler, PLL, and LCD driver. In addition to an
IF counter, serial interface and buzzer function, the device incorporates an
interrupt function, timer counter, pulse counter, electronic volume function
and A/D converter
The device also supports selection of 1/4-duty 1/2 bias or 1/4-duty 1/3
bias for the LCD driver, while a built-in 3 V voltage doubler boosting
circuit implements stable operation of the LCD monitor.
The power supply voltage ranges from 0.9 V to 1.8 V. Due to its
low-current consumption, the device is suitable for use in digital tuning
systems in portable equipment such as headphone stereos.
Weight: 0.32 g (typ.)
Features
•
CMOS DTS microcontroller LSI with built-in prescaler PLL and LCD driver
•
Operating voltage range:
VDD = 0.9 to 1.8 V (typ.: 1.5 V)
•
Current dissipation:
With CPU in operation: IDD = 150 µA (typ.)
With PLL in operation: IDD = 1 mA (typ. At inputting OSCin = 30 MHz)
•
Operating temperature range:
Ta = −10 to 60°C
•
Program memory (ROM):
16-bit × 8192 steps
•
Data memory (RAM):
4-bit × 512 words
•
Oscillator frequency:
Crystal oscillator:
75 kHz (crystal oscillator)
High-speed oscillator: 300 to 600 kHz (ceramic oscillator or crystal oscillator)
•
Instruction execution time:
Crystal oscillator: 40 µs
High-speed oscillator: 5 to 10 µs
•
Interrupt:
External:
2 system (INTR1, INTR2 pin)
Internal:
4 system (serial-interface, timer-port, timer-counter, decreased voltage
detection)
•
Interrupt stack:
4 level × 26 bit G-register, Data select, Carry flag, Data register
•
Address stack:
16 level × 13 bit (program counter)
•
I/O port:
CMOS I/O port: 36 (max)
N-ch open-drain I/O port: 9 (max)
Exclusive output port: 2 (max), exclusive input port: 1 (max)
•
LCD driver:
1/4 duty, 1/2 bias or 1/4 duty, 1/3 bias: 72 segments (max)
•
Serial Interface:
1 system, 2 channel (N-ch open-drain, CMOS I/O port), 3 kinds (3-wired, 2-wired,
UART)
•
Buzzer:
4 kinds of frequency (1 kHz, 1.56 kHz, 2.08 kHz, 3 kHz),
4 modes (continuous, single-shot, 10 Hz intermittent, 10 Hz intermittent 1 Hz interval)
•
Timer counter:
8 bit, 2 kinds of timer clock (25 kHz, 1 kHz),
2 modes (timer counter, pulse width measure (INTR1 pin))
•
Pulse counter:
8 bit up/down counter
•
Electronic volume:
2 channel, 32 step (0 dB to −78 dB, −∞dB)
•
A/D converter:
6 bit, 4 channel, conversion time: 240 µs
•
Amplifier for LPF:
5.5 V output max. (Tout, Tin)
•
DC/DC converter of VT:
2 stage (0.75 V, 1.0 V) voltage detected (VDET)
15 kinds of doubler clock, 2 types of doubler clock output
(CMOS output: DDCK2, N-ch output: DDCK1)
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2006-02-24
TC9349AFG
•
DC/DC converter for CPU:
Charge-pump type
Two kinds of doubler clock: 75 kHz crystal oscillator,
high-speed oscillator clock (300 to 600 kHz),
setting doubler voltage for 3 stages (2.0 V, 2.5 V, 3.0 V)
•
Programmable counter:
16-bit HF mode: 1/15 or 16-pulse swallow-type (1 to 30 MHz, Vin = 0.1Vp-p (min))
LF mode: 12 bit direct divider type (0.5 to 4 MHz, Vin = 0.1Vp-p (min))
•
Reference frequency:
10 kinds (1 kHz, 1.3889 kHz, 1.5625 kHz, 2.7778 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25
kHz, 12.5 kHz, 25 kHz)
•
Phase comparator:
2 (max), setting for “H”/“L” level, High-impedance and built-in output resistor by
program. two units (max); “H”/“L” level-setting, high-impedance setting, and built-in
output resistor setting (0 kΩ, 5 kΩ, 50 kΩ, 100 kΩ) possible through programming
(DO1/DO2); automatic change of output resistor according to phase difference is possible
through programming. (DO2)
•
General-purpose IF counter:
20 bits, 0.03 to 12 MHz, Vin = 0.1Vp-p (min)
•
Backup function:
three modes: clock stop (stoppage of crystal oscillator); hard wait, (crystal oscillator
operation only); soft wait (CPU intermittent operation)
•
Reset function:
Built-in power-on reset circuit
•
Decreased voltage detection function: Voltage detection is possible in 25 mV steps in the range VDD = 0.850 V to 1.225 V.
Decreased voltage detection enables selection of the CPU stop function.
•
Package:
QFP-64 (0.5 mm in pitch, 1.4 mm thick)
•
EEPROM product:
TC93E49FG
Note:
This product is sensitive to electrostatic discharge. Handle with care.
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2006-02-24
TC9349AFG
P16-0/S15
P16-1/S16
P16-2/S17/Xin2
P16-3/S18/Xout2
P3-0/SCK1/RX1 (BRK1)
P3-1/SDIO1/TX1 (BRK2)
P3-2/SI1 (BRK3)
P3-3/PCTRin (BRK4)
P4-0/INTR1 (BRK5)
P4-1/INTR2/INH (BRK6)
P4-2/BUZR (BRK7)
P4-3/VRout1 (BRK8)
P5-0/VRin1
P5-1/VRcom
P5-2/VRin2
P5-3/VRout2
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
54
P9-0/Tout
55
MUTE/P9-1
56
P9-2/DDCK2/TEST
57
P8-0/VDET (BRK13)
58
P8-1/SI2/DDCK1 (BRK14)
59
P8-2/SCK2/RX2 (BRK15)
60
P8-3/SDIO2/TX2 (BRK16)
61
RESET
62
LCD driver (1/4 duty, 1/3 or 1/2 bias: 72 segments max)
53
N-ch open drain
I/O port (1)
SVFP64
(0.5 mm pitch)
Top - view
CMOSI/O port (2)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
VDB
C3
C4
VLCD
VEE
VCPU
A/D (4ch)
C2
Doubler/regular circuit
C1
Xin1
Oscillation
64 circuit
VDD
63
Xout1
GND
N-ch open drain
I/O port (4)
3
32
P15-1/S14
31
P15-0/S13
30
P14-3/S12
29
P14-2/S11
28
P14-1/S10
27
P14-0/S9
26
P13-3/S8
25
P13-2/S7
24
P13-1/S6
23
P13-0/S5
22
P12-3/S4
21
P12-2/S3
20
P12-1/S2
19
P12-0/S1
18
P10-3/COM4
17
P10-2/COM3
P10-1/COM2
DO1/OT1/P
DO2/OT2/N/Tin
P10-0/COM1
52
P6-3/ADin4 (BRK12)
GND (PLL)
CMOS I/O port (34)
P6-2/ADin3 (BRK11)
51
P6-0/ADin1 (BRK9)
OSCin
Pull-up/pull-down
P6-1/ADin2 (BRK10)
50
SIO1
PLL
VPLL
Electronic volume
SIO2
49
N-ch open drain
I/O port (4)
IFin/IN
2006-02-24
TC9349AFG
Block Diagram
VDD
VLCD
P6-3/ADin4 (BRK12)
MUTE
R/WBuf.
G-Reg.
P6-2/ADin3 (BRK11)
Port 6
P6-1/ADin4 (BRK10)
MUTE
VDD
VLCD
P6-0/ADin4 (BRK9)
RAM
(4 × 512 Words)
P8-0/VDET (BRK13)
P8-1/SI2/DDCK1 (BRK14)
P8-2/SCK2/RX2 (BRK15)
P8-3/SDIO2/TX2 (BRK16)
Port 8
Interrupt Stack Reg.
(4 Levels)
DDCK1
VCPU
VEE
Ca
DDCK
Control
VDB
VLCD
VDET
Data
Select
DDCK
DDCK2 MUTE
VEE
VDB
P9-0/Tout
MUTE/P9-1
P9-2/DDCK2/TEST
A/D
Conv.
ALU
VR
Data Reg (16 bits)
Instruction
Decoder
Port 9
P5-3/VRout2
P5-2/VRin2
Port 5
P5-1/VRcom
P5-0/VRin1
ROM
(16 × 8192 Steps)
VDD
BUZR
P4-3/VRout1 (BRK8)
VLCD
P4-2/BUZR (BRL7)
Port 4
IFin/IN
IF
Counter
P4-1/INTR2/ INH (BRK6)
P4-0/INTR1 (BRK5)
Interrupt
Control
VDB
DDCK
VPLL
OSCin
GND
Program
Counter
Timer
VLCD
VDD
VLCD
PLL
Address Stack Reg.
(16 Levels)
DO1/OT1/P
DO2/OT2/NTin
VDD
Up/Down
Counter
P3-3/PCTRin (BRK4)
P3-2/S11 (BRL3)
P3-1/SDIO/TX1 (BRK2)
P3-0/SCK1/RX1 (BRK1)
Port 3
Phase
Comp.
Serial
Interface
VDB
RESET
Reset
Reset
CPU
Clock
OSC
Control
GND
Xin1
Xout1
OSC2
OSC1
VDD
Peripheral
VDD
OSC2
C1
C2
VDB
Doubler
VEE
VEE
(1.5 V)
C3
C4
Doubler
OSC2
VDD
VLCD
LCD
Driver
Port 10 Port 12 Port 13 Port 14 Port 15
Port 16
VLCD
VLCD
4
P16-0/S15
P16-1/S16
P16-2/S17/Xin2
P16-3/S18/Xout2
P15-1/S14
P15-0/S13
P14-0/S9
P14-3/S12
P13-3/S8
P13-0/S5
P12-3/S4
P12-0/S1
P10-3/COM4
: N-ch Open drain
P10-0/COM1
VDB
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TC9349AFG
Description of Pin Functions
PIN No.
Symbol
64
Xin1
Pin Name
Function and Operation
Remarks
Rout1
Xout1
Crystal oscillator pin
1
Crystal oscillator pins.
A reference 75 kHz crystal resonator is
connected to the Xin1 and Xout1 pins.
RfXT1
VDD
Xin1
Xout1
(Xin1, Xout1)
68
GND
Power-supply pins
2
Power supply pin for the crystal oscillator
and doubler circuit for the CPU (VDB).
Normally, VDD = 0.9 to 1.8 V is applied.
VDD potential is detected in the 0.850 V to
1.225 V range in 25 mV steps using the
decreased voltage detection circuit. If VDD
potential falls below the voltage being set,
the CPU can be stopped to prevent
incorrect operation.
Note: After reset, the voltage set for the
decreased voltage detection is VDD
= 0.85 V. CPU stop function is
enabled.
VDD
GND
VDD
Doubler output pins for CPU.
3
4
The doubler system is the charge-pump
system.
When a doubler clamp is permitted, a
voltage of 2.0 V, 2.5 V or 3.0 V can be
selected. A doubler clock can select either
one of 75 kHz, 37.5 kHz or high-speed
oscillator clock.
C1
C2
Doubler output pins for
CPU
Usually, the VDB pin connected to the
capacitor for stabilization (0.1 µF, 10 µF
typ.) supplies voltage for the power supply
of the CPU only ( VCPU). The VDB potential
is supplied to the power supply of the A/D
converter, and a 1.5 V constant-voltage
circuit ( VEE).
The voltage is doubled by the doubler
capacitor between C1 and C2 (0.47 µF
typ.). When the doubler clamp is enabled,
the voltage is doubled below the voltage
being set.
5
⎯
⎯
VDB
VDB
Note: During reset or execution of the
clock stop instruction, the VDB pin is
set to VDD level. The LX pin is L
level for CMOS output, and at high
impedance for open-drain output.
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TC9349AFG
PIN No.
Symbol
6
C3
7
C4
8
VLCD
9
VEE
Pin Name
Doubler output pin for
LCD driver
Function and Operation
Remarks
Doubler output pin for the LCD driver.
The VLCD pin doubles the VEE pin
voltage to 3 V using the voltage doubler
capacitance between C3 and C4.
The doubled VLCD voltage is supplied to
the I/O port, the power supply of the LCD
driver, and the electronic volume power
supply.
Usually, the stabilizing capacitor (0.1 µF
typ.) is connected between the VLCD pin
and GND. The voltage doubler capacitor
(0.1 µF typ.) is connected between C3 and
C4.
⎯
⎯
VLCD
Note: During reset or execution of a clock
stop instruction, the VLCD pin is set
to the VCPU power supply level.
Constant-voltage output pin.
The VEE pin outputs 1.5 V (typ.)
constant-voltage power supply.
The VEE potential is used for the voltage
doubler for the CPU, the clamp function of
Constant-voltage output the DC/DC converter and the reference
voltage of the A/D converter.
pin
The stabilizing capacitor (0.47 µF typ.) is
connected to the VEE pin.
VEE
Note: During reset or execution of the
clock stop instruction, the VEE pin
is at high impedance.
10
VCPU
CPU power supply pin
CPU power supply pin.
Normally, 1.2 to 3.6 V is applied. When
memory backup is required, VDB potential
is applied to this pin and this pin’s potential
is held.
In backup state (at execution of the
CKSTP instruction), current dissipation
drops (0.5 µA or less), and the power
supply voltage can be reduced to 0.75 V.
If voltage is applied to this pin, the device
system is reset and the program starts
from address “0” (power-on reset).
VCPU
Note: To operate the power-on reset, the
power supply should start up in 10
to 100 ms.
Note: To be used with VCPU ≤ VLCD.
P6-0/ADin1
(BRK9)
~
11~14
P6-3/ADin4
(BRK12)
I/O port 6
/AD analog input
4-bit N-ch open-drain I/O ports, allowing
input and output to be programmed in 1-bit
units.
If the ports are set as the input state of an
I/O port, these can be set to break pins.
The backup mode can be released by
changing the input state of the break pin in
the backup mode.
I/O ports are N-ch open-drain output. Up to
the VDB voltage can be applied to the AD
input pins.
Pins P6-0 to P6-3 can also be used for
analog input to the built-in 6-bit, 4-channel
A/D converter.
The conversion time of the built-in A/D
converter using the successive
comparison method is 240 µs.
The necessary pin can be programmed to
A/D analog input in 1-bit units.
Up to the doubled voltage VDB (VDD × 2)
can be input as the A/D input voltage.
6
To A/D
converter
VDD
Input instruction
Release enables
2006-02-24
TC9349AFG
PIN No.
Symbol
Pin Name
Function and Operation
Remarks
22-bit CMOS I/O ports, allowing input and
output to be programmed in 1-bit units.
P10-0/COM1
~
15 ~ 18
P10-3/COM4
I/O port 10
/LCD common output
It can be set as LCD driver output through
programming.
LCD
potential
Through a matrix with pins COM1 to
COM4 and S1 to S18, a maximum of 72
segments can be displayed.
P12-0/S1
~
19 ~ 22
P12-3/S4
I/O port 12
/LCD segment output
VDD
When the LCD OFF bit is set to “0”, all of 8
pins of P10-0 to P12-3 become the LCD
output of COM1 to COM4 and S1 to S4.
Other LCD driver pins (S5 to S18) can be
set to the LCD driver output for every pin.
VDD
P13-0/S6
~
23 ~ 26
P13-3/S8
P14-0/S9
~
27 ~ 30
P14-3/S12
31 ~ 32
P15-0/S13
/
P15-1/S14
P16-0/S15
/Xin2
~
33 ~ 36
P16-3/S18
/Xout2
I/O port 13
/LCD segment output
I/O port 14
/LCD segment output
I/O port 15
/LCD segment output
I/O port 16
/LCD segment output
/High speed oscillator
Either of two drive systems can be
selected: 1/4 duty1/2 bias system (frame
frequency: 62.5 kHz) or 1/4 duty 1/3 bias
system (frame frequency: 125 kHz).
When 1/2 bias system is set, common
output is VLCD, 1/2 VLCD and GND, and
segment output is VLCD and GND. When
1/3 bias system is set, common output and
segment output are VLCD, 1/3 VLCD, 2/3
VLCD and GND.
If “1” is set to DISP OFF bit, common
output is non-selected waveform and LCD
display are all switched off.
Pins P16-2 and P16-3 can be set to the
high-speed oscillation pins Xin2 and Xout2
through programming.
A 300-600 kHz ceramic or crystal oscillator
is connected to Xin2 and Xout2 pins.
This oscillation clock can be changed to
CPU operation clock for high-speed CPU
operation. During execution of the clock
stop instruction, oscillation stops.
Input instruction
Xout2
Rout2
RfXT2
VDD
Xin2
(Xin2, Xout2)
Note: When changing the CPU clock to a
high-speed oscillator clock, do so
100 ms or more after the
high-speed oscillator is enabled.
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TC9349AFG
PIN No.
Symbol
Pin Name
Function and Operation
Remarks
4-bit CMOS I/O Port, allowing input and
output to be programmed in 1-bit units.
When the I/O port is set as input, the
pull-up/pull-down state can be
programmed in 1-bit units.
37
P3-0/SCK1
/RX1
(BRK1)
I/O port 3
/Serial clock input/
output 1/UART input 1
38
P3-1/SDIO1
/TX1
(BRK2)
/Serial data input/
output 1/UART output 1
39
P3-2/SI1
(BRK3)
/Serial data input 1
40
P3-3/PCTin
(BRK4)
/Pulse counter input
If set as the input state of an I/O port and
a backup release enable state, the backup
state can be released by changing input
state in the clock stop and the wait modes.
Pins P3-0 to P3-2 are used as input/output
pins of a serial interface circuit.
VDD
RIN1
VDD
The serial interface circuit corresponds to
2-wired, 3-wired and UART types. Serial
clock edge, serial clock input/output and
clock frequency are selectable, facilitating
the control of various LSIs and
communication between controllers.
When interruption of a serial interface
circuit is permitted, interruption occurs and
a program is jumped to the 3rd address
after the serial interface operation is
completed.
VDD
Input instruction
Release enables
The P3-3 pin is used as 8-bit pulse
counter input PCTRin. Since it is possible
to select either or both of the rising edge
and falling edge of the input pin, as well as
count-up or count-down, the pin can be
used as an input to a tape count.
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TC9349AFG
PIN No.
Symbol
Pin Name
Function and Operation
Remarks
VDD
8-bit CMOS I/O Port, allowing input and
output to be programmed in 1-bit units.
41
42
P4-0/INTR1
(BRK5)
P4-1/INTR2
INH (BRK6)
43
P4-2/BUZR
(BRK7)
I/O port 4
/External interrupt
input 1
/External interrupt
input 2
/PLL inhibit input
When P4-0 to P4-3 ports are set as the
input and backup release enable states,
the backup state in the clock stop and wait
modes can be released by changing input
state.
/Buzzer output
Pins P4-0 and P4-1 are also used as
external interrupt input INTR1 and INTR2.
VDD
Input instruction
Release enables
(P4-0 to P4-2)
When external interrupt is enabled and a
3-clock pulse of CPU (40 µs: using 75 kHz
oscillator) or longer is input to the INTR1
or INTR2 pin, an interrupt is generated and
a program jumps to the 1st or 2nd
address.
Electronic
volume signal
VDD
44
P4-3/VRout1
(BRK8)
I/O port 4
/Electronic volume
output1
For input interrupt, input logic or
rising/falling edge can be selected for each
pin. The signal input from the INTR1 pin
can measure the pulse width using the
8-bit internal timer. The signal can be used
to detect a remote control signal.
VDD
The P4-1 pin is used as the PLL inhibit
input INH .
If the INH pin is set to the PLL inhibit
enable state, the PLL is stopped during “L”
level of the INH pin.
45
46
47
48
P5-0/VRin1
P5-1/VRcom
P5-2/VRin2
P5-3/VRout2
I/O port 5
/Electronic volume
input1
The P4-2 pin is used as the buzzer output.
For the buzzer output it is possible to
select 4 frequencies, 1/1.56/2.08/3 kHz,
with 4 modes: continuous output,
single-shot output, 10-Hz intermittent
output, and 10-Hz intermittent 1-Hz
interval output.
Input instruction
Release enables
(P4-3)
Electronic
volume signal
VDD
/Electronic volume
reference voltage input
/Electronic volume
input 2
/Electronic volume
output 2
Pins P4-3 and P5-0 to P5-3 are used as
input/output pins for electronic volume.
There are two electronic volume channels.
An I/O port or electronic volume is
selectable for every channel. Attenuation
can be controlled from 0 dB to –78 dB and
∞ dB in 32 steps.
9
VDD
Input instruction
(P5-0 to P5-3)
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TC9349AFG
PIN No.
Symbol
Pin Name
Function and Operation
Remarks
IF signal input pin.
The input frequency is between 0.03 and
12 MHz. A built-in input amp and C
coupling allow small-amplitude operation.
The IF counter can store 20-bit data in
memory. In Manual mode, gate On/Off
control can be performed using an
instruction.
49
IFin/IN
IF signal input
/Input port
The input pin is used as an input port (IN
port). In this case, the pin is for CMOS
input, so that input clocks can be counted
using the IF counter.
Note: When a pin is set to IF input, the
input is at high impedance in
PLL-off mode.
Rfin2
VPLL
VPLL
Input instruction
Note: Since the VPLL power supply is used
in this circuit, an input state cannot
be read when the VPLL power
supply is in the OFF state.
Pin to which power is applied for the PLL
prescaler.
50
VPLL
VPLL
PLL
Power supply pin
Normally, the supply voltage to be applied
is from 0.9 to 1.8 V.
Current dissipation becomes low in PLL-off
mode.
52
GND (PLL)
Usually, the pin is connected to the VDD
Programmable counter input pin.
It is possible to select the pulse-swallow
type (HF mode) or the direct divide type
(LF mode) through programming.
51
OSCin
Local oscillation signal
input
The local oscillation output of 1 to 30 MHz
is input in the HF mode; 0.5 to 4 MHz in
the LF mode.
Rfin1
VPLL
A built-in input amp and C coupling allow
small-amplitude operation.
Note: The input is at high impedance in
PLL-off mode.
10
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TC9349AFG
PIN No.
Symbol
Pin Name
Function and Operation
Remarks
PLL phase comparator output pins.
VDB
Tristate output: When the program counter
divider output is higher than the reference
frequency, High level is output; when the
output is lower, Low level; and when they
match, high impedance.
The doubler voltage VDB is used for phase
comparator power supply. The VDB power
supply potential is output for High level.
The DO1 and DO2 pins incorporate 3
types of output resistance (5 kΩ, 50 kΩ,
100 kΩ), which can be changed for each
pin.
53
DO1/OT1/P
54
DO2/OT2/N
/Tin
Phase comparator
output
/output port
/P output
/Tr. Input for LPF
The DO2 pin can change output resistance
automatically according to the phase
difference of the PLL. Therefore, lock-up
time is improved.
Rout1
(DO1/OT1/P, DO2/OT2)
Tin
VDB
Tout
Rout1~4
(Tin, Tout)
Note: Tin/Tout setting
The DO2 pin can be programmed to
high-impedance or as an output port (OT1,
OT2). The phase comparator charge pump
control signal (P/N), which is used to
configure an external charge pump, can be
output from the DO1/2 pin.
If the phase comparator charge pump
control signal (P/N) is set, when the
program counter divider output is higher
than the reference frequency, P/N is
output at H/L level; when the output is
lower, L/H level; and when they match, L/L
level.
VDD
Input instruction
(P9-0)
VDD
Pins P9-1 to P9-2 is 2-bit CMOS I/O ports.
The P9-0 pin is a 1-bit N-ch open-drain
I/O, allowing input and output to be
programmed in 1-bit units.
P9-0/Tout
I/O port 9
/Tr. Output for LPF
56
MUTE/P9-1
/Mute output
57
P9-2/DDCK2
/TEST
/Clock output 2 for
doubler
/TEST mode input
Input instruction
(MUTE/P9-1)
During system reset ( RESET = “L”), the
P9-2 pin is pulled down and becomes the
test mode input.
Therefore, the pin is normally used at Low
level or in open state during the reset
condition.
Through programming, it is possible to use
the N-ch FET transistor for low path filter
amplifiers (5.5 V voltage).
As for FET transistors, Tin pin is set as
gate input and Tout pin is set as drain
output.
VDD
VDD
Rin2
55
VDD
The P9-1 pin is used as the MUTE output.
The MUTE output is usually used for
muting control signal output. The MUTE bit
can be set to “1” through change in the
input of the I/O port input release (BRK)
pin. The MUTE output logic can be set
through programming.
Input instruction,
Reset
(P9-2/DDCK2/TEST)
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PIN No.
Symbol
Pin Name
Function and Operation
Remarks
The port 8 is a 4-bit N-ch open-drain I/O
port, allowing control of ON/OFF for an
output transistor to be programmed in 1-bit
units When an output is set as OFF, the
pin can be used as an input port.
When the backup release enable state is
set, the backup state in the clock stop and
wait modes can be released by a change
in the input or output pin.
The I/O port is N-ch open-drain I/O. Up to
5.5 V can be input to or output from the I/O
port.
P8-0/VDET
(BRK13)
I/O port 8
/Detected doubler
voltage input
P8-1/SI2
/DDCK1
(BRK14)
/Serial data input 2
/Doubler clock output 1
P8-2/SCK2
/RX2
(BRK15)
/Serial clock input/
output 2
/UART input 2
P8-3/SDIO2
/TX2
(BRK16)
/Serial clock input/
output 2
/UART output 2
58 ~ 61
This pin is used to configure the switching
regulator for VT.
The voltage is doubled by the doubler
clock output DDCK1 (P8-1) or DDCK2
(P9-2). The divided voltage is input to the
detected doubler voltage VDET pin (P8-0)
to control the doubler clock.
The DDCK1 output is 5.5V N-ch output.
The VT doubled voltage is doubled to 5 V
through the use of an external transistor.
Detected
doubler
voltage input
VDD
Input instruction
Release enables
(P8-0)
The DDCK2 output is CMOS output The
voltage can be doubled through the use of
an external transistor.
For the doubler clock, it is possible to
select from three types of dividing
frequency: crystal oscillator, high-speed
oscillator and OSCin input.
It is also possible to select through
programming the comparator reference
potential of the VDET input: either 0.75 V
or 1.0 V.
Pins P8-1 to P8-3 are used as serial
interface circuit (SIO) input/output pins.
The serial interface circuit corresponds to
2-wired type, 3-wired type, and UART.
Serial clock edge, serial clock input/output,
and clock frequency can be selected,
facilitating the control of various LSIs and
communication between controllers.
VDD
Input instruction
Release enables
(P8-1, P8-3)
When interrupts of a serial interface circuit
are enabled, an interrupt is generated after
serial interface and the program jumps to
the 3rd address.
Input pin for system reset signals. The
input uses built-in Schmitt circuit.
62
RESET
Reset input
RESET takes place while at Low level; at
High level, the program starts from
address “0” after 100 ms standby.
VCPU
Normally, if voltage is applied to the VCPU
pin, the system is reset (power-on
reset).Therefore, this pin should be set to
High level during operation.
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Description of Operations
{ CPU
The CPU consists of a program counter, a stack register, an ALU, program memory, data memory, a G-register, a data
register, a DAL address register, a carry flip-flop (F/F), a judge circuit, interrupt stack register and an interrupt circuit.
1.
Program Counter (PC)
The program counter is a 14-bit binary up-counter used to address program memory (ROM). The program counter is
cleared by a system reset and starts from address 0.
The PC is normally incremented by 1 at the execution of each instruction. However, executing a Jump or Call instruction
loads the address specified in the operand of the instruction to the PC.
When an instruction with a skip function (the AIS, SLTI, TMT, RNS instructions, etc.) is executed and the result of the
instruction satisfies the skip condition, the PC is incremented by 2 and the next instruction is skipped.
When an interrupt is received, the system loads the vector address corresponding to the interrupt.
Note: The program memory (ROM) uses the address range 0000H to 1FFFH. Access to addresses outside this
range is prohibited.
Contents of program counter (PC)
Instruction
PC13 PC12 PC11 PC10
JUMP ADDR1
0
CALL ADDR2
0
DAL ADDR3, (r)
(DAL bit = 0)
0
PC9
PC8
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Instruction operand (ADDR1)
Instruction operand (ADDR2)
0
0
0
Contents of general
register (r)
Instruction operand (ADDR3)
DAL (DA)
DAL address register (AR)
(DAL bit = 1)
RN, RNS, RNI
Contents of stack register
When interrupt received
Power-on reset, reset by
RESET pin
PC7
Vector addresses for interrupt
0
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt source
Vector address
INTR1 pin
0001H
INTR2 pin / Timer port
0002H
Serial interface / timer port / decreased voltage detection
0003H
Timer counter
0004H
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2. Address Stack Register (ASR)
The address stack register consists of 16 × 14 bits. When the subroutine call instruction is executed or an interrupt is
processed, this register stores a value equal to the contents of the program counter + 1 (that is, the return address).
Executing the return instruction (RN, RNS, RNI) loads the contents of the address stack register to the program counter.
There are 16 stack levels available and nesting occurs for up to 16 levels. The address stack register is mapped to I/O and
can be read/written by the input and output instructions.
3. ALU
The arithmetic and logic unit (ALU) has binary 4-bit parallel addition/subtraction functions, logical operation,
comparison and multiple bit judge functions. The CPU does not include an accumulator; all operations use the contents of
the data memory directly.
4. Program Memory (ROM)
The program memory consists of 16 bits × 8192 steps and is used for storing programs. The usable address range consists
of 8192 steps between addresses 0000H and 1FFFH.
The program memory divides the 8192 into eight separate steps and consists of pages 0 to 7. The JUMP and CALL
instructions can be freely used throughout all 8192 steps. When the data refer DAL (DAL instruction) is executed, the
program memory addresses 0000H to 03FFH (page 0) are used as data areas; when the indirect refer DAL instruction
(DALR instruction) is executed, the program memory addresses 0000H to 0FFFFH (pages 0 to 3) are used as data areas.
Execution of these instructions enables their 16-bit contents to be loaded into the data register.
Note: Set the data area in program memory to addresses outside the program loop.
Note: The program counter used to set the program memory has 14 bits and can specify a program memory up
to address 3FFF. Do not specify non-existing addresses from 2000H to 3FFFH.
ROM
16 bits
Vector addresses at interrupt
0800H
Page 2
0C00H
Page 3
1000H
Page 4
0001H
0002H
0003H
0004H
INTR1 pin
INTR2 pin / timer port
Serial interface / timer port /
decreased voltage detection
Timer counter
Area available to DALR instruction
Page 1
Area available to CALL instruction
0400H
Area available to JUMP instruction
Page 0
(1-k steps)
0000H Jump destination address at initialization
Interrupt vector
address
Area available to DAL instruction
0000H
1400H
Page 5
1800H
Page 6
1C00H
Page 7
1FFFH
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5. Data Memory (RAM)
The data memory consisting of 4 bits × 512 words is used to store data. These 512 words are expressed in a row address
(4 bits) and column address (4 bits). 348 words (row address = 04H to 1FH) within the data memory are addressed
indirectly by the G-register. Therefore it is necessary to specify the row address with the G-register before the data in this
area can be processed.
The addresses 00H to 0FH within the data memory are known as general registers, and can be used simply by specifying
the relevant column address (4 bit). These sixteen general registers can be used for operations and transfers with the data
memory, and may also be used as normal data memories.
Note: The column address (4 bits) that specifies the general register is the register number of the general
register.
Note: All row addresses (00H to 1FH) can be specified indirectly with the G-register.
Note: The LD and ST instructions can directly address 256 words of data memory (row address area 00H to
0FH).
COLUMN ADDRESS: DC
ROW ADDRESS: DR
0 1 2 3 4 5 6 7 8 9 A B C D E F
Row addresses (04H to
2FH) indirectly specified
by G-register
*
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
General register
(any register within 000H to 00FH)
The LD and ST instructions can
directly specify row addresses
(00H to 0FH).
12
*
Row address area
00H to 1FH can be
indirectly specified.
1D
1E
1F
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6. G-register (G-REG)
The G-register is a 5-bit register used for addressing the row address (DR = 00H to 1FH) of the data memory’s 512 words.
This register is located on the I/O map and accessed by input-and-output instruction. The 5-bit contents can be directly set
by execution of the STIG instruction. (Refer to Register Ports.)
The contents of this register are effective when the MVGD or MVGS instruction is executed, and are not affected
through execution of any other instructions. The contents of the G-register are evacuated to the interrupt stack register when
an interrupt request is generated, and returned to the G-register during execution of the RNI instruction. (Refer to Interrupt
Stack Register.)
7. Data Register (DATA REG)
The data register consists of 16 bits and loads 16 bits of data from any address in the program memory on execution of
the DAL instruction. This register is used as one of the ports. The contents of the register are loaded into the data memory in
4-bit units when the IN1 instruction among the I/O instructions is executed. (Refer to Register Ports.) The contents of data
register are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the data register
during execution of the RNI instruction. (Refer to Interrupt Stack Register.)
8. DAL Address Register (AR)
The DAL address register consists of 14 bits. When the DALR instruction is executed, 16 bits of the data of the program
memory on the address specified by the DAL address register is loaded to the data register. The contents in the DAL address
register are automatically increased by one whenever the DALR instruction is executed.
The contents of the data register can be transferred to the DAL address register by execution of the MVAR instruction.
The DAL address register is located on the I/O map and accessed by input and output instructions.
(Refer to Register Ports.)
9. Carry Flag (Ca Flag)
The carry flag register is set when either Carry or Borrow is issued in the result of calculation instruction execution, and
is reset if neither of these is issued. The flag is located on the I/O map and can be accessed by the input and output
instructions. (Refer to Register Port.)
The contents of a carry flag are changed by execution of only the addition, subtraction, CLT, CLTC, SHRC or RORC
instruction and are not affected by execution of other instructions. The contents of carry flag are evacuated to the interrupt
stack register when an interrupt request is generated, and returned to the carry flag during execution of the RNI instruction.
(Refer to Stack Register.)
10.
Interrupt Stack Register (ISR)
This register consists of 4 levels and 26 bits. When an interrupt occurs, the contents of the G-register (5 bits), data select
(4 bits), carry flag (1 bit) and data register (16 bits) are automatically evacuated to the interrupt stack register. After interrupt
processing has been completed, these contents are returned to each register by the RIN instruction. Four levels of stack and
nesting are allowed in the interrupt stack register. (Refer to Interrupt Stack Register.)
11.
Judge Circuit (J)
This circuit judges the skip conditions when an instruction with the skip function is executed. The program counter is
increased by two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions
with a wide variety of skip functions available. (Refer to the items marked with a “*” symbol in Instruction Function and
Operation Table.)
12.
Interrupt Circuit
An interrupt circuit branches to the various vector addresses according to the demands from peripheral hardware and
performs different types of interrupt processing. (Refer to Interrupt Function.)
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13.
Instruction Set Table
A total of 59 instruction sets are available, and all of these are single-word instructions. These instructions are expressed
with a 6-bit instruction code.
Upper 2 bits
Lower 4 bits
00
01
10
11
0
1
2
3
0000
0
AI
M, I
TMTR
r, M
SLTI
M, I
0001
1
AIC
M, I
TMFR
r, M
SGEI
M, I
0010
2
SI
M, I
SEQ
r, M
SEQI
M, I
0011
3
SIB
M, I
SNE
r, M
SNEI
M, I
0100
4
ORIM
M, I
TMTN
M, N
0101
5
ANIM
M, I
0110
6
XORIM
M, I
0111
7
MVIM
1000
8
1001
9
1010
JUMP ADDR1
TMT
M, N
TMFN
M, N
M, I
TMF
M, N
AD
r, M
IN1
M, C
AC
r, M
IN2
M, C
A
SU
r, M
IN3
M, C
1011
B
SB
r, M
1100
C
ORR
1101
D
1110
E
LD
r, M*
ST
M*, r
OUT1
M, C
r, M
CLT
r, M
OUT2
M, C
ANDR
r, M
CLTC
r, M
OUT3
M, C
XORR
r, M
MVGD
r, M
DAL
ADDR3, r
SHRC
M
RORC
M
STIG
I*
CAL ADDR2
SKP, SKPN
RN, RNS
1111
F
MVSR
M1, M2
MVGS
M, r
WAIT
P
CKSTP
XCH
M
DI, EI, RNI
DALR
MVAR
NOOP
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14.
Instruction Function and Operation Table
(Description of the symbols used in the table)
M
M*
r
PC
ASP
ASR
ISP
ISR
G
DATA
I
I*
N
−
C
CN
RN
ADDR1
ADDR2
AR
Ca
CY
P
b
IN1~IN3
OUT1 ~ OUT3
()
[]C
[]
[]P
IC
*
DC
DR
DR*
(M) b0 ~ (M) b3
Data memory address
Normally, an address within 000H to 03FH in the data memory.
Data memory address (256 words)
An address within 000H to 0FFH in the data memory.
(Effective only during execution of the ST or LD instruction)
General register
An address within 000H to 00FH in the data memory.
Program counter (14 bits)
Address stack pointer (14 bits)
Address stack register (14 bits)
Interrupt stack pointer (2 bits)
Interrupt stack register (26 bits)
G-register (5 bits)
Data register (16 bits)
Immediate data (4 bits)
Immediate data (6 bits, effective only during execution of the STIG instruction)
Bit position (4 bits)
All “0”
Port code number (4 bits)
Port code number (4 bits)
General register number (4 bits)
Program memory address (13 bits)
Upper 6 bits of program memory address within page 0
DAL address register (14 bit)
Carry
Carry flag
Wait condition
Borrow
Ports used during execution of the IN1 to IN3 instructions
Ports used during execution of the OUT1 to OUT3 instructions
Contents of registers or data memory
Contents of the port indicated by the code number C (4 bits)
Contents of data memory indicated by the register or data memory
Contents of program memory (16 bits)
Instruction code (6 bits)
Command with skip function
Data memory column address (4 bits)
Data memory row address (2 bits)
Data memory row address
(4 bits, effective only during execution of the ST or LD instruction)
Bit data of data memory contents (1 bit)
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Mnemonic
Compare instruction
Subtraction instruction
Addition instruction
Instruction
Set
Skip
Function
Machine Language (16 Bits)
Function
Operation
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
AI
M, I
Add immediate data
M ← (M) + I
to memory
000000
DR
DC
I
AIC
M, I
Add immediate data
to memory with
M ← (M) + I + ca
carry
000001
DR
DC
I
AD
r, M
Add memory to
general register
001000
DR
DC
RN
AC
r, M
Add memory to
general register with r ← (r) + (M) + ca
carry
001001
DR
DC
RN
SI
M, I
Subtract immediate
data from memory
M ← (M) − I
000010
DR
DC
I
SIB
M, I
Subtract immediate
data from memory
with borrow
M ← (M) − I − b
000011
DR
DC
I
SU
r, M
Subtract memory
from general
register
r ← (r) − (M)
001010
DR
DC
RN
SB
r, M
Subtract memory
from general
register with borrow
r ← (r) − (M) − b
001011
DR
DC
RN
SLTI
M, I
r ← (r) + (M)
*
Skip if memory is
less than immediate Skip if (M) < I
data
110000
DR
DC
I
Skip if (M) >
=I
110001
DR
DC
I
SGEI
M, I
*
Skip if memory is
greater than or
equal to immediate
data
SEQI
M, I
*
Skip if memory is
equal to immediate
data
Skip if (M) = I
110010
DR
DC
I
SNEI
M, I
*
Skip if memory is
not equal to
immediate data
Skip if (M) ≠ I
110011
DR
DC
I
SEQ
r, M
*
Skip if general
register is equal to
memory
Skip if (r) = (M)
010010
DR
DC
RN
SNE
r, M
*
Skip if general
register is not equal
to memory
Skip if (r) ≠ (M)
010011
DR
DC
RN
CLT
r, M
Set carry flag if
general register is
less than memory,
or reset if not
(CY) ← 1 if (r) < (M)
or
(CY) ← 0 if (r) >
= (M)
011100
DR
DC
RN
r, M
Set carry flag if
general register is
less than memory
with carry or reset if
not
(CY) ← 1 if (r) < (M) +
(ca) or
(CY) ← 0 if (r) >
= (M) +
(Ca)
011101
DR
DC
RN
CLTC
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Mnemonic
Transfer instruction
Instruction
Set
I/O instruction
Machine Language (16 Bits)
Function
Operation
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
LD
r, M*
Load memory to
general register
r ← (M*)
0101
DR*
(4 bits)
DC
RN
ST
M*, r
Store memory to
general register
M* ← (r)
0110
DR*
(4 bits)
DC
RN
MVSR M1, M2
Move memory to
memory in same
row
(DR, DC1) ← (DR,
DC2)
001111
DR
DC1
DC2
MVIM
Move immediate
data to memory
M←I
000111
DR
DC
I
MVGD r, M
Move memory to
destination memory
referring to
G-register and
general register
[(G), (r)] ← (M)
011110
DR
DC
RN
MVGS M, r
Move source
memory referring to
G-register and
(M) ← [(G), (r)]
general register to
memory
011111
DR
DC
RN
STIG
Move immediate
data to G-register
111111
M, I
I*
MVAR
Logical Operation instruction
Skip
Function
G ← I*
I*
0010
Move DATA register
data to DAL
AR← (DATA)
address register
111111
⎯
⎯
1001
IN1
M, C
Input IN1 port data
to memory
M ← [IN1] C
111000
DR
DC
CN
OUT1
M, C
Output contents of
memory to OUT1
port
[OUT1] C ← (M)
111011
DR
DC
CN
IN2
M, C
Input IN2 port data
to memory
M ← [IN2] C
111001
DR
DC
CN
OUT2
M, C
Output contents of
memory to OUT2
port
[OUT2] C ← (M)
111100
DR
DC
CN
IN3
M, C
Input IN3 port data
to memory
M ← [IN3] C
111010
DR
DC
CN
OUT3
M, C
Output contents of
memory to OUT3
port
[OUT3] C ← (M)
111101
DR
DC
CN
ORR
r, M
Logical OR of
general register and r ← (r) ∨ (M)
memory
001100
DR
DC
RN
ANDR
r, M
Logical AND of
general register and r ← (r) ∧ (M)
memory
001101
DR
DC
RN
ORIM
M, I
Logical OR of
memory and
immediate data
M ← (M) ∨ I
000100
DR
DC
I
ANIM
M, I
Logical AND of
memory and
immediate data
M ← (M) ∧ I
000101
DR
DC
I
XORIM M, I
Logical exclusive
OR of memory and
immediate data
M ← (M) ∀ I
000110
DR
DC
I
XORR r, M
Logical exclusive
OR of general
register and
memory
r ← (r) ∀ (M)
001110
DR
DC
RN
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Instruction
Set
Mnemonic
Interrupt instruction
Jump
instruction
Subroutine instruction
Bit judge instruction
TMTR
r, M
Skip
Function
Machine Language (16 Bits)
Function
Operation
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
*
Test general
register bits by
memory bits, then
skip if all bits
specified are true
Skip if r [N (M)] = all
“1”
010000
DR
DC
RN
Skip if r [N (M)] = all
“0”
010001
DR
DC
RN
TMFR
r, M
*
Test general
register bits by
memory bits, then
skip if all bits
specified are false
TMT
M, N
*
Test memory bits,
then skip if all bits
specified are true
Skip if M (N) = all “1”
110101
DR
DC
N
TMF
M, N
*
Test memory bits,
then not skip if all
bits specified are
false
Skip if M (N) = all “0”
110111
DR
DC
N
TMTN
M, N
*
Test memory bits,
then skip if all bits
specified are true
Skip if M (N) = not all
“1”
110100
DR
DC
N
TMFN
M, N
*
Test memory bits,
then not skip if all
bits specified are
false
Skip if M (N) = not all
“0”
110110
DR
DC
N
SKP
*
Skip if carry flag is
true
Skip if (CY) = 1
111111
00
⎯
0011
SKPN
*
Skip if carry flag is
false
Skip if (CY) = 0
111111
01
⎯
0011
CALL ADDR2
Call subroutine
ASR ← (PC)  1 and
PC ← ADDR2
ASP ←(ASP) + 1
101
RN
Return to main
routine
PC ← (ASR)
ASP ←(ASR) - 1
111111
10
⎯
0011
Return to main
routine and skip
unconditionally
PC ← (ASR) and skip
ASP ←(ASR) - 1
111111
11
⎯
0011
JUMP ADDR1
Jump to address
specified
PC ← ADDR1
10
DI
Reset IMF
(Note) IMF ← 0
111111
00
⎯
0111
EI
Set IMF
(Note) IMF ← 1
111111
01
⎯
0111
111111
11
⎯
0111
RNS
RNI
*
PC ← (ASR)
PC ← (ASR) – 1
Return to main
Ca, G, DATA, DATA
routine and set IMF SELECT ← (ISR)
(Note) ISP ← (ISP) – 1
ADDR2 (13 bits)
ADDR1 (13 bits)
IMF ← 1
Note: The IMF bit is an interrupt master enable flag located on the I/O map. (Refer to Interrupt Functions.)
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Other instructions
Instruction
Set
Mnemonic
Skip
Function
Machine Language (16 Bits)
Function
Operation
SHRC M
Shift memory bits to
0 → (M) b3 → (M) b2 →
right direction with
(M) b1 → (M) b0→ (CY)
carry
RORC M
Rotate memory bits
to right direction
with carry
XCH
Exchange memory
bits mutually
M
(M) b3 → (M) b2 →
(M) b1→ (M) b0 →
(CY)
(M) b3 ↔ (M) b0,
(M) b2 ↔ (M) b1
IC
(6 Bits)
A
(2 Bits)
B
(4 Bits)
C
(4 Bits)
111111
DR
DC
0000
111111
DR
DC
0001
111111
DR
DC
0110
DAL ADDR3, r
Load program in
DATA ← [ADDR3 +
page 0 to DATA
(r)] P in page 0
register
(Note)
111110
DALR
Load program
memory to DATA
register referring to
DAL address
register, and
increment DAL
address register
DATA ← [(AR)]P
AR ← (AR) + 1
111111
⎯
⎯
1000
At P = “1” H, all
functions except for
clock generator
enter the waiting
state (hard wait
mode)
Wait at condition P
111111
P
⎯
0100
CKSTP
Clock generator
stop
Stop clock generator to
MODE condition
111111
⎯
⎯
0101
NOOP
No operation
⎯
111111
⎯
⎯
1111
ADDR3 (6 bits)
RN
At P = “0” H, the
condition is CPU
waiting (soft wait
mode)
WAIT
P
Note: The lower 4 bits of the 10 bits of program memory specified by the DAL instruction (DAL ADDR2, r) are
addressed indirectly by the contents of the general register. The 13 bits of program memory specified by DALR
instruction are used for indirect addressing.
Note: The DAL address register (AR) is located on the I/O map. (Refer to Register Ports.)
Note: The DAL or DALR instruction run-time is two machine cycles.
22
2006-02-24
TC9349AFG
{ I/O Map, Data Select Port (φL/K1A)
All the ports within the device are expressed with a matrix of six I/O instructions (OUT1 to 3 instructions and IN1 to 3
instructions) and 4-bit code numbers.
The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in the execution
of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port code numbers indicated on the
vertical axis. The G-register, data register and DAL bits are also used as ports.
The OUT1 to 3 instructions are specified as output ports, and the IN 1 to 3 instructions are specified as input ports.
Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device.
When data is output to a non-existing output port by execution of the output instruction, the contents of
other ports and data memories are not affected. When a non-existing input port is specified by execution
of an input instruction, the data loaded from the data memory assumes “don’t care” status.
Note: The output ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports
assumes “don’t care” status.
Note: The Y1 contents of the ports expressed in 4 bits correspond to the LSB and the Y8 contents correspond
to the MSB in the data memory.
The ports specified with the six I/O instructions and code number C are coded in the following manner.
φ [K/L]
m n (o) (Pp)
Pages (1 to 3)
Contents of selected port (indirectly specified data, 0 to F (HEX))
I/O instruction operand CN (0 to F (HEX))
The six I/O instructions are coded with digits 1 to 3
I/O instruction
OUT1
OUT2
OUT3
IN1
IN2
IN3
m
1
2
3
1
2
3
Indicates input/output ports.
K: Input port (instructions IN1 to 3)
L: Output port (instructions OUT1 to 3)
Example:
The setting for the G-register is allocated to code 8 and 9 in the OUT1 instruction. The encoded expression at
this time becomes φL18 and φL19.
23
2006-02-24
TC9349AFG
Data port (φL10 to 16, φK10 to 11) on the I/O map is divided into 16 and indirectly specified by the contents of the data
select port (φL/K1A). The indirectly specified port is accessed by the OUT1 instruction with the operand [CN = 0 to 6H] or
IN1 instruction with the operand [CN = 0 to 1H]. Whenever the data select port accesses the data port, it is automatically
incremented by 1.
The data select port has a 4-bit interrupt stack register. When an interrupt request is generated, the 4 bits in the data select
port are evacuated to the interrupt stack register specified by the interrupt stack pointer, and returned to the data select port
during execution of the RNI instruction.
φL/K10(6)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interrupt stack pointer
φL/K10(A)
0
ISRS0
ISRS2
ISRS4
ISRS8
1
2
3
Interrupt stack register
Interrupt processing
Execution of the RIN
instruction
φL10 ∼ φL15, φK10 ∼ φK11
φL/K1A
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Y1
Y2
Y4
Y8
(0)
(1)
Data select
(2)
(F)
< Indirect specification by the data selection port >
24
2006-02-24
TC9349AFG
I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
Page 1
Y1
φL1
φL2
φL3
φK1
φK2
OUT1
OUT2
OUT3
IN1
IN2
Y2
Y4
Y8
Y1
Y2
Data port 1
0
EF1
(INTR1)
ILR1
(INTR1)
EF2
EF3
(INTR2/TM) (SIO/TP/W)
ILR2
(INTR2/TM)
ILR3
(SIOTP/W)
INTR1 control
POS1
Data port 4
3
Y1
Y2
Y4
Y8
Y1
Y2
POS2
AS SEL0
AS SEL1
Y1
EF1
(INTR1)
NEG2
ILR1
(INTR1)
-0
-1
-2
IF data 1
-3
F0
AS SEL2
STA
-0
DO1 control
F2
-1
-2
F3
IMF
IF data 2
-3
F4
Y1
EF2
(INTR2/TM)
EF3
(SIO)
Y2
Y4
Y8
EF4
(TIMER)
ILR2
(INTR2/TM)
ILR3
(SIOTP/W)
ILR4
(TIMER)
0
0
I/O port 3 input data
0
-0
A/D converter data
F5
F6
I/O port 5 output data
Y8
Interrupt master flag
F1
I/O port 4 output data
Y4
Interrupt latch
ILR4
(TIMER)
I/O port 3 output data
IN3
Y2
Interrupt enable flag
Data port 2
A/D converter control
Data port 5
Y8
EF4
(TIMER)
INTR2 control
NEG1
Y4
Data port 1
Interrupt latch reset
Data port 3
2
Y8
Interrupt enable flag
Data port 2
1
Y4
φK3
F7
AD0
IF data 3
AD1
AD2
-1
-2
-3
I/O port 4 input data
AD3
-0
A/D converter data
-1
-2
-3
I/O port 5 input data
4
R0
R1
Data port 6
5
R0
DISP OFF
LCD OFF
BIAS
*
G-register 1
8
G0
G1
M1
-0
-1
-2
-3
F8
F9
M0
M1
-0
-1
-2
ENA
CK0
CK1
UNLOCK
RESET
PN
POL
LPFON
-3
F12
F13
G2
G3
F17
-1
-2
Break
G4
*
S1
*
CA flag
S2
Busy
MANUAL
MUTE
ENA
G0
G4
*
Timer reset
S4
S8
2 Hz F/F
*
NEG
G1
d1
d2
d3
CTR
RESET
Data-register 2 (DATA)
D
d4
d5
d8
d6
d7
CK
d9
d12
d13
-0
F19
-0
STOP
F/F
BUZER
10 Hz
0
UNLOCK
ENA
VDO OFF
F/F
ENA
-0
d10
d14
-1
-2
-3
I/O port 4 control
DOWN
*
-0
OVER
RESET
*
PW
CR
Disable
-1
-2
SEL1
G2
CA flag
G3
Unknown
-0
IO1
POL
-1
-2
-0
d0
CR
-0
-1
-2
d11
ID0
d15
ID4
ID1
ID2
ID6
SEL4
0
SEL8
2 Hz F/F
0
-0
d2
0
d4
d5
d6
d8
ID3
I/O port 16 data
ID7
-0
-1
-2
d9
d10
d3
PC4
d12
d13
-3
-1
-2
-1
-3
IN
-2
-1
-2
-3
d14
200 Hz
PC1
PC2
I/O port 12 input data
PC3
-0
PC5
PC6
d7
OVER
0
0
PC7
CT0
d15
CT4
CT1
CT2
-0
0
CT6
-1
-0
-1
I/O port 15 input data
CT3
-0
CT7
-0
Timer counter data 2
CT5
-2
-3
-2
-3
I/O port 14 input data
Timer counter data 1
d11
-1
I/O port 13 input data
Pulse counter data
Data-register 4 (DATA)
-3
100 Hz
Pulse counter data
Data-register 2 (DATA)
-3
10 Hz
Pulse counter data
Data-register 3 (DATA)
Timer counter interrupt detect data 2
ID5
d1
-2
I/O port 9 input data
-0
Data-register 1 (DATA)
-3
-1
Timer
PC0
I/O port 16 control
-3
I/O port 8 input data
Unknown
0
-3
I/O port 5 control
*
0
-2
I/O port 10 input data
0
SEL2
-1
0
MUTE control
MUTE
Data select
Timer counter interrupt detect data 1
Data-register 4 (DATA)
F
CK SEL
Timer counter control
Data-register 3 (DATA)
E
0
Unlock detect
OVER
0
I/O port 3 control
Pulse counter control 2
Data-register 1 (DATA)
d0
Clock
Timer port interrupt
control
*
POS
C
F18
G-register 1
Pulse counter control 1
*
Busy
G-register 2
Data select
A
AD5
F15
IF monitor
-3
MUTE control
POL
F14
F16
I/O port 8 output data
-0
AD4
I/O port 6 input data
IF data 5
AUTO1
MUTE
F11
IF data 4
G-register 2
9
F10
I/O port 6 output data
DO2 control 2
LCD driver control
7
B
R1
Data port 7
6
M0
DO2 control 1
-2
-3
0
0
-1
I/O port 16 input data
-1
-2
-3
Refer to the next page
25
2006-02-24
TC9349AFG
φL/K1A
Data select
SEL1
SEL2
SEL4
SEL8
φL10
φK10
OUT1
IN1
I/O
φL/K1A
Y1
Y2
Y4
Y8
Y1
Address stack pointer (ASP)
0
ASP0
ASP1
ASP2
ASS0
ASS1
ASS2
ASP3
ASP0
ASR0
ASR1
ASR2
ASS3
STKS0
ASR4
ASR5
ASR6
ASR3
ASR0
ASR8
ASR9
ASR10
Y2
ASP1
STKS1
ASR1
ASR7
ASR4
ASR5
ASP2
ASP3
AR0
AR1
STKS2
ASR2
ASR6
ASR11
ASR8
ASR9
ASR10
IN1
Y4
Y8
Y1
STKS3
AR4
AR5
AR2
AR3
DA0
AR8
AR9
AR6
AR7
DA4
AR12
AR13
AR10
AR11
DA8
ASR11
SO0
SO1
DA1
DA2
DA3
DA5
DA6
DA7
DA9
DA10
DA11
DAL address 4 (AR)
TROM
*
DA12
Serial interface output data 1
Address stack register 4 (ASR)
Y8
DAL address 3 (AR)
DAL address 4 (AR)
ASR7
Y4
DAL address 2 (AR)
DAL address 3 (AR)
ASR3
Y2
DAL address 1 (AR)
DAL address 2 (AR)
Address stack register 3 (ASR)
Address stack register 4 (ASR)
φK11
DAL address 1 (AR)
Address stack register 2 (ASR)
Address stack register 3 (ASR)
4
Y1
Address stack register 1 (ASR)
Address stack register 2 (ASR)
3
Y8
Address stack select
Address stack register 1 (ASR)
2
Y4
Address stack pointer (ASP)
Address stack select
1
Y2
φL11
OUT1
DA13
TROM
0
Serial interface input data 1
SO2
SO3
SI0
Serial interface output data 2
SI1
SI2
SI3
Serial interface input data 2
5
ASR12
ASR13
*
*
ASR12
6
ISP0
ISP1
*
*
ISP0
Interrupt stack select
7
ISS0
ISS1
*
ASR13
0
0
SO4
SO5
Interrupt stack pointer (ISP)
Interrupt stack pointer (ISP)
ISP1
0
0
SO8
SO9
Interrupt stack select
*
ISS0
Interrupt stack register (ISR)
ISS1
0
SO6
SO7
SI4
Serial interface output data 3
SOE
SOF
SI8
Serial interface control 1
0
M0
M1
Interrupt stack register (ISR)
SI5
SI6
SI7
Serial interface input data 3
SI9
SIE
SIF
Serial interface monitor 1
PORT SEL
SIO
BUSY1
Serial interface control 2
SOERR
RX F/F
BUSY2
Serial interface monitor 2
8
ISRG0
ISRG1
ISRG2
ISRG3
ISRG0
Interrupt stack register (ISR)
9
ISRG4
*
*
*
ISRG4
Interrupt stack register (ISR)
A
ISRdS0
ISRdS1
ISRdS2
ISRCA
*
*
ISRdS3
ISRdS0
ISRd0
ISRd1
ISRd2
*
ISRCA
ISRd4
ISRd5
ISRd6
ISRd3
ISRd0
ISRd8
ISRd9
ISRd10
ISRd7
ISRd4
0
0
0
ISRdS1
ISRdS2
0
0
ISRd1
ISRd2
ISRd5
ISRd6
ISRd11
ISRd8
ISRd9
ISRd10
ISRdS3
ISRd14
0
ISRd12
ISRd13
ISRd14
26
OCT0
MASTER
POL
OCT1
OCT2
OCT3
Serial interface monitor 3
N-chS
SIS
ICT0
ICT1
ICT2
ICT3
STPS
SWENA
MSB
SOS
STA0
STA1
STA2
STA3
Serial interface control 6
ISRd3
STP0
STP1
STP2
STP3
Serial interface control 7
ISRd7
TSTA1
TSTA2
STP
Decreased voltage detection voltage trimming register
F/F RESET
TR0
Decreased voltage detection control 1
ISRd11
Interrupt stack register (ISR)
ISRd15
OSC1
Serial interface control 5
WAIT ENA
INH ENA
VSTOP ENA
ISRd15
STOP F/F
RESET
INT LB
SEL
TIM
SEL
TR1
TR2
TR3
Constant-voltage trimming register
*
TT0
Decreased voltage detection control 2
F
ISRd13
OSC0
Serial interface control 4
Interrupt stack register (ISR)
Interrupt stack register (ISR)
ISRd12
CK1
Serial interface control 3
Interrupt stack register (ISR)
Interrupt stack register (ISR)
E
CK0
Interrupt stack register (ISR)
Interrupt stack register (ISR)
D
ISRG3
Interrupt stack register (ISR)
Interrupt stack register (ISR)
C
ISRG2
Interrupt stack register (ISR)
Interrupt stack register (ISR)
B
ISRG1
Interrupt stack register (ISR)
TT1
TT2
TT3
PLL amplifier trimming register
BREAK
ENA
TA0
TA1
TA2
TA3
2006-02-24
TC9349AFG
φL/K1A
Data select
S1
S2
S4
S8
I/O
φL/K1A
Y1
Y2
φL12
φL13
φL14
φL15
φL16
OUT1
OUT1
OUT1
OUT1
OUT1
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
I/O port 9 output data
0
-0
-1
-2
COM1
*
COM2
I/O port 10 output data
1
-0
-1
-2
-0
-1
-2
COM1
-3
-0
-1
-2
-0
-1
-2
COM1
-3
COM1
-3
-3
COM1
COM2
-2
-3
COM1
-0
-1
*
COM3
COM2
I/O port 15 output data
6
COM4
COM3
COM4
S3
*
7
COM1
COM1
COM2
-1
-2
-0
-1
-2
COM1
COM4
PRI1-0
*
COM1
COM3
COM2
COM4
PRI3-0
COM3
COM4
VC0
COM1
COM2
COM1
COM2
I/O port 12 control
-0
-1
-2
-3
COM1
COM2
C
-0
-1
-2
COM1
I/O port 14 control
D
-0
BP4
COM3
COM4
PU30
PU31
-1
-2
E
-0
-1
*
VR0
-3
COM1
COM4
PD30
COM1
COM4
CH1
COM4
S5
S6
COM4
S9
S10
COM3
COM4
VDET
SEL
Interrupt priority 2
COM3
COM4
S13
S14
BF1
*
BM1
BUZR
ON
VR1
VR2
*
*
Y4
Y8
BEN
NC
IFin
Prescaller
IN
0
IF counter control 2
POL
STA/ STP
MANUAL
G0
G1
TEST port 1
VR3
#0
#1
#2
#3
TEST port 2
*
#4
*
*
*
CH2
VR MUTE
-∞dB
PRI2-0
PRI2-1
DD0
Interrupt priority 4
PRI4-0
PRI4-1
CLAMP
BP6
PU32
PD32
S7
S11
*
0
VDET
ENA
*
DC/DC converter control 2
DD1
DD2
DD3
DC/DC converter control 3
DDCK1/2
DDCK
ENA
POL
*
PLL mode select
OSC2
HF
*
*
0
0
0
BP8
0
INH ENA
Programmable counter 1
PU33
P0
P1
P2
P3
Programmable counter 2
PD33
P4
P5
P6
P7
Programmable counter 3
S8
P8
P9
P10
P11
Decreased voltage detection voltage trimming
register
Programmable counter 4
S12
P12
I/O port 15 / Segment select
S12
Y2
IF counter control 1
DC/DC converter control 1
I/O port 14 / Segment select
COM3
COM2
COM3
I/O port 13 / Segment select
S11
*
PD31
Y1
Electric volume control
I/O port 3 pull-down
COM3
COM2
VR4
I/O port 3 pull-up
S10
I/O port 15 control
VC1
BP3
COM3
COM2
PRI3-1
COM4
S9
-3
PRI1-1
COM3
S8
I/O port 13 control
COM4
I/O port 2 brake permit
S7
A
B
COM4
Doubler voltage control for CPU
S6
-3
COM2
Y8
Electric volume data 2
COM3
COM2
Interrupt priority 3
S5
I/O port 10 control
9
COM1
Interrupt priority 1
COM3
COM2
I/O port 9 control
*
BM0
S18
S4
8
COM4
S17
S2
Y4
Electric volume data 1
COM3
COM2
Y2
Buzzer output control 2
COM3
COM2
S1
5
-1
BF0
S16
I/O port 14 output data
-0
COM4
S15
I/O port 13 output data
4
Y1
Buzzer output control 1
COM3
COM2
I/O port 12 output data
3
Y8
S14
I/O port 11 output data
2
Y4
S13
P13
P14
P15
TR0
Reference select
*
R0
I/O port 16 / segment select
R1
R2
TR1
TR2
TR3
Constant-voltage trimming register
R3
TT0
Clock generator control
TT1
TT2
TT3
PLL amplifier trimming register
F
COM1
COM2
COM3
COM4
27
S15
S16
S17
S18
INV ON
OSC2 ON
CK SEL
*
TA0
TA1
TA2
TA3
2006-02-24
TC9349AFG
{
System Reset
The device system will be reset when the RESET pin is subject to the “L” level or when a voltage of 0 V → 1.2 V to
3.6 V is supplied to the VCPU pin (power-on reset). On system reset, the program will start from “0” address immediately
after a standby time of 100 ms following the startup of the low-speed oscillator. Since the power-on reset function is being
used, the RESET terminal should be fixed at “H” level under normal conditions.
Note: The input circuit of the RESET pin operates on a VCPU power supply, and the input voltage level is 0
V~VCPU.
Note: The power-on reset circuit operates on power startup of the VCPU power supply.
Note: The LCD common output and the segment output will be fixed at “L” level during system reset and during
the subsequent standby period.
Note: It is necessary to initialize any internal port shown in the above-mentioned I/O map that has not been
initialized after system reset. The
mark on the I/O map shows a port or bit that is set to “0” after system
reset, while the
mark shows a port or bit that is set to “1”. No mark shows a port or bit that is unfixed.
φL2F
I/O
OUT2
φL2D
Y1
Y2
Y4
Y8
After system reset, unmarked
port is unfixed.
MUTE control
8
IMUTE
POL
After system reset, this port is set to “1”.
MUTE
Break
ENA
After system reset, these ports are set to “0”
VDD pin
GND
(Note)
(Note)
VCPU pin
GND
RESET pin
GND
A crystal oscillator stops
during the reset from a reset pin.
XOUT pin
Standby
(about 100 ms)
Internal reset
signal
CPU operation
CPU
operation
Standby
(about
100 ms)
Reset
CPU
operation
Standby
(about 100 ms)
< Timing of Operation >
Note: If the VDD power supply voltage falls below 0.9 V or the VCPU power supply voltage falls below 1.2 V, set
to clock stop mode and operate the reset function. The VCPU power supply voltage will be reset when the
power supply is restarted (power-on reset).
Note: VCPU pins are usually supplied from doubler voltage VDB pins. Refer to the backup mode item.
28
2006-02-24
TC9349AFG
{ System clock control circuit
The system clock control circuit consists of a clock generator, clock generator control port, timing generator and backup
mode control circuit.
Clock generator
CO
Ｒ
XOUT1
75 kHz
CI
Clock generator
control port
(φL15F)
Low-speed
oscillator
Backup mode
control circuit
X IN1
Ｒ
300 ∼
600 kHz
CI
XOUT2
Peripheral clock
Peripheral timing generator
High-speed
oscillator
CPU clock
CPU timing generator
XIN2
VDD
Note: It is necessary to use a crystal resonator with a low CI value and favorable startup characteristics.
Note: Adjust and determine the external resistance and capacitor constant to match the crystal resonator
actually used.
Note: The low-speed oscillator and high-speed oscillator are equipped with a built-in Schmitt circuit.
Note: The power supply of the low-speed oscillator and high-speed oscillator uses a VDD pin.
1. Clock generator
The clock generator circuit generates the basic clock used as the standard for the system clock supplied to a core-based
CPU and peripheral hardware. The circuit incorporates low-speed and high-speed oscillators, with a 75 kHz crystal
resonator connected to the XIN1 and XOUT1 pin and a 300 to 600 kHz ceramic resonator or a crystal resonator connected to
the XIN2 to XOUT2 pin.
The CPU clock and doubler clock (VDB doubler or doubler for VT) can be converted to a high-speed oscillation clock
through programming. Since items such as the timer and reference frequency utilize the 75 kHz clock during this time, the
timer duration measurement and PLL are unaffected.
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2. Clock generator control port
The clock generator control port controls the low-speed and high-speed oscillators.
φL15(F)
Y1
Y2
Y4
Y8
INV ON
OSC2
ON
CK
SEL
*
Selection of CPU clock
High-speed oscillator
control
Selection of low-speed
oscillator
0: Low-speed oscillator
1: High-speed oscillator
0: Oscillator stop
1: Oscillator
0: Constant-current system
1: Inverter system
The OSC2ON bit controls the on/off setting of the high-speed oscillator. If this bit is set to “1”, the high-speed oscillator
is enabled and oscillation is started.
The CK SEL bit converts the CPU operation clock to a low-speed or high-speed oscillator clock. After reset, the CPU
operates with a 75 kHz low-speed clock. When the high-speed clock is to be used, conversion to the high-speed clock takes
place after the OSC2 ON bit is set to “1” and the high-speed oscillator frequency is stabilized. The INV ON bit can be used
to change the circuit type of the 75 kHz low-speed oscillator. This is usually set to a constant-current type.
Note: The high-speed oscillator clock can be used as the doubler clock for the VDB pin or doubler clock for the
VT (DDCK1/DDCK2).
Note: CK SEL bit control is restricted to conversion of the CPU operation clock and does not affect items such
as PLLs and timers.
Note: The circuit type of the 75 kHz low-speed oscillator is used for the constant-current system. If the crystal
oscillator circuit is set to an inverter type, its output level rises. This circuit type should only be used to
investigate whether or not the tuner characteristic of the crystal oscillator has been affected.
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{ DC/DC converter for CPU
The device incorporates a DC/DC converter for the CPU power supply. The CPU doubler circuit comprises a charge
pump system utilizing a capacitor.
There is a built-in clamp control function, for which an electrical potential of 2.0, 2.5 and 3.0 V can be set through
programming.
The capacitor-utilizing charge pump system supplies a VDD level charge between the C1 and C2 pins, and a doubler
potential twice the VDD potential is output to the VDB pin. Note that, if twice the voltage of the VDD pin decreases
following clamp setting using this method, the doubler potential also decreases.
Three types of 1/2 frequency can be selected for the doubler clock: 37.5 kHz, 75 kHz, and a high-speed oscillation clock.
After reset, a frequency of 37.5 kHz is output. Set the doubler clock to the required doubler capability.
The doubled VDB potential is supplied to the A/D converter and the VEE constant-voltage circuit. The VDB potential is
usually supplied to the VCPU pin through a Schottky diode.
φL14(8)
Y1
Y2
Y4
Y8
VC0
VC1
CLAMP
OSC2
Doubler clock frequency selection for doubler
OSC2 ON
(φL15(F)-Y2)
OSC2
Doubler Clock Frequency for the CPU
Doubler Clock
Frequency for
the LCD Driver
*
0
Low-speed oscillator clock (75kHz)×1/2
Same as left
0
1
1
1
Low-speed oscillator clock (75kHz)
Low-speed
High-speed oscillator clock (300～600kHz)×1/2 oscillator clock
Clamp function control
0: Off（VDD × 2）
1: On
Clamp voltage control
Note: This becomes effective only when the clamp function is ON.
VC0
VC1
Clamp voltage
0
0
Prohibition
0
1
2.0V
1
0
2.5V
1
1
3.0V
Note: If the OSC2 bit is set to “1”, the doubler clock for the LCD driver is also changed simultaneously.
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Doubler clock
CLAMP
Doubler circuit
Internal reference voltage
VDD
Internal doubler voltage
(A/D converter, constantvoltage
C2
circuit)
C1
3
2
VDB
4
10 µF
0.1 µF
10 µF
0.1 µF
Doubler voltage
Example of an Application Circuit for a Charge Pump Doubler System Utilizing a Capacitor
Note: The VDB pin is fixed at the VDD pin level while the clock stop instruction is being executed.
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{
Constant-voltage circuit (VEE)
There is a built-in constant-voltage circuit (VEE) to provide the reference voltage of the LCD driver and DC/DC
converter for the VT and for the CPU and A/D converter. The constant-voltage circuit utilizes the doubler VDB pin power
supply for the CPU and outputs a constant voltage of 1.5 V from the VEE pin. There is a constant-voltage compensation
data port for rectifying the constant-voltage value VEE, and voltage can be rectified per 20 mV. Do not set this port through
programming as correction data is usually determined at the time of shipment.
φL16(E)
Y1
Y2
Y4
Y8
TR0
TR1
TR2
TR3
The constant-voltage rectify data
Note: After system reset, this serves as the port for data rectification so that VEE is set to 1.5 V at the time of
shipment. For this reason, do not access this port.
Note: During reset or a clock stop, the VEE pin becomes high impedance.
{
LCD driver doubler circuit (VLCD)
There is a built-in doubler circuit for LCD drivers (VLCD) that acts as an LCD driver power supply.
The doubler circuit for LCD drivers outputs a 3 V constant voltage doubled from a 1.5 V constant voltage through the
capacitor-utilizing charge pump system doubler.
1.5 V constantvoltage circuit
VEE
37.5kHz
or
75kHz
C4
C3
9
To LCD driver
Doubler circuit
6
VLCD
7
0.47 µF
0.1 µF
8
0.1 µF
Note: During reset or a clock stop, the VLCD pin outputs the VCPU level.
Note: The VLCD doubler potential is used for the power supply in the I/O port, etc.
Note: The doubler clock can use 37.5 kHz or 75 kHz (OSC2 bit).
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{ Backup mode
Backup mode decreases the operating current and holds data memory and other registers. Backup mode can be
implemented through programming-based backup or hardware-based backup.
For programming-based backup, three types of backup mode are possible through the executing of CKSTP or WAIT
instructions.
For hardware-based backup there are two types of function: a decreased voltage detection function and a power-off
backup function. When the VDD pin power supply falls to the decreased voltage detection setting potential (VDD = 0.85 V 1.225 V), a decrease voltage detection function stops the CPU temporarily and prevents incorrect operation of the CPU.
During this time, the operational status of such items as the LCD driver, I/O ports, and PLL is held. If the VDD pin level is
set to approximately 0.5 V or less, the power-off backup function will stop functions such as LCD driver, I/O port, and PLL
operations; reduce the only power supply for the CPU (VCPU pin) to a low consumption current (0.5 µA or less); and hold
memory contents and the status of other registers.
1. Clock stop mode
Execution of the CKSTP instruction actuates clock stop mode.
Clock stop mode suspends system operations while maintaining the internal status immediately prior to suspension. At
this time, the VDD, VPLL and VCPU pin power supplies change to low consumption current (10 or less µA); crystal
oscillation stops; the LCD indication output pin and CMOS output port are fixed to the "L" level; and the N-ch open drain
pins are all set to the OFF (high-impedance) state automatically. The power supply of the VDD and VPLL pins can be
lowered to the OFF state, and the power supply of the VCPU pin power supply can be lowered to 0.75 V.
Clock stop is released under the following conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) If the VDD power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the VDD
power supply break is enabled (BRAEK ENA bit (φL11(F)) = "1").
Release of clock stop mode causes the next address to be executed after 100 ms of standby time have elapsed.
Note: The PLL changes to the off state during execution of the CKSTP instruction.
Break pin
High impedance
XOUT1 pin
CKSTP
instruction
CPU
operation
Clock stop
Standby
(about 100 ms)
CPU
operation
Executing of
CKSTP instruction
Executing of
CKSTP instruction
Example of Operation Timing Using a Break Pin
Note: Clock stop mode is actuated on execution of the CKSTP instruction.
Note: When break pin input is set, it is necessary to read this input state before execution of the CKSTP
instruction.
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VCPU pin
GND
VDD pin
When a voltage of approx. 0.5 V or more is impressed,
it is released.
GND
XOUT1 pin
CPU
operation
Clock stop
(backup)
Standby
(about 100 ms)
CPU
operation
Clock stop
CKSTP pin
Executing of
CKSTP instruction
Executing of
CKSTP instruction
Example for Operating Timing by Power Supply Pin
Note: Release of the CKSTP instruction through on/off of the VDD power supply pin requires the BREAK ENA
bit (φL11(F)) to be set to "1". When this function is enabled, about 10μA will be consumed in the VCPU
pin if voltage is applied through the VDD pin during CKSTP instruction execution. For this reason, this
function should be prohibited if voltage is always impressed through the VDD pin power supply.
Note: It is necessary to retain the potential of the VCPU pin. Provide backup using a capacitor or similar means.
Note: Reset occurs if the VCPU pin level (typ: 0.3 V) falls to 0.75 V or below and the voltage is then applied
(power-on reset).
2. Wait mode
Wait mode suspends system operations, maintains the internal status immediately prior to suspension and decreases
current consumption. This mode stops at the address for the execution of the WAIT instruction on execution of hard
and soft wait. On cancellation of wait mode, the next address is executed immediately, with no standby interval.
(1)
SOFT WAIT mode
Only CPU operations within the device are suspended when a WAIT instruction is executed in which [P = 0H] has
been specified in the operand. The crystal resonator and other elements will continue to operate normally at this time.
SOFT WAIT mode is efficient in reducing current consumption during clock operations when used in programs that
include clock functions.
The wait status applies whenever the WAIT instruction is executed. Wait mode is canceled on the following
conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) When the 2 Hz Timer F/F is set as “1”
Note: The backup state applies if the VDD power supply pin goes off in wait mode when the VDD power
supply is enabled (BRAEK ENA bit (φL11(F)) = "1"). The state is released when the power supply is
turned on (at approximately 0.5 V or more). At this time, the CPU starts up after 100 ms of standby
time have elapsed.
Note: Current consumption will vary depending on the execution time of the CPU operation.
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(2)
HARD WAIT mode
The operations of all elements, with the exception of the crystal resonator and doubler operating (VDB / VLCD pin),
can be suspended by execution of a WAIT instruction in which [P = 1H] has been specified in the operand. This
enables even greater levels of current consumption reduction than SOFT WAIT mode. This suspends the CPU
operation.
During hard wait mode, the state of the output port is maintained and all LCD output pins are fixed at the “L" level.
The wait status is assumed whenever the WAIT instruction is executed. Wait mode is canceled on the following
conditions:
1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to
input. (Refer to the section on I/O ports.)
2) If the VDD power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the
VDD power supply break is enabled (BRAEK ENA bit (φL11(F)) = "1").
Note: Wait mode is also released when the VDD power supply pin in wait mode is changed from the off to
the on state (at approximately 0.5 V or more) when the VDD power supply break has been enabled
(BRAEK ENA bit (φL11(F)) = "1").
Note: The PLL OFF status will be assumed during wait mode.
Note: During wait mode, the power supply doubler circuit (VDB pin), the constant-voltage supply circuit for
the LCD (VEE pin) and the doubler circuit for the LCD ( VLCD pin) continue to operate.
3.
Backup mode by hardware
The backup mode by hardware detects the power supply voltage level of a VDD pin and actuates backup mode.
There are two types of backup function by hardware: a decreased voltage detection function and a power supply off
detection function.
(1)
Decreased voltage detection function
The decreased voltage detection function detects the VDD pin level, suspends the operation of the CPU and
prevents incorrect operation of the CPU. If the VDD pin level falls below the decreased voltage detection setting
(VDD = 0.85V - 1.225V) potential when the detected decrease voltage function is enabled, CPU operation will be
suspended; and if the VDD pin again rises above the set voltage, the CPU will restart. Although the CPU stops, other
functions continue to operate normally.
Decreased voltage detection operation is performed at intervals. The frequency of detection can be selected through
programming, with detection being performed at a rate of once every two instructions or 16 instruction cycles. Select
according to power consumption and speed of power supply variation.
The detection voltage can be set to an interval of 25 mV within the range of VDD = 0.85 V ∼ 1.225 V. Set
according to the specification. Since suspension of CPU operation can be prohibited, it is also possible to detect
residual battery level between 0.85 V and 1.225 V by varying the detection setting voltage and detecting the detection
flag. In this case, execute a backup instruction after detection of the minimum voltage level to prevent incorrect
operation of the CPU.
Where interrupt is permitted, the interrupt will be issued if the VSTOP F/F bit is set to “1”. If interrupt is received,
the program will branch to 0003H address.
Moreover, PLL off-mode can be actuated during decreased voltage detection. Therefore the PLL can be quickly
suspended should the voltage drop.
The VSTOP F/F bit enables detection of suspension or of a fall below the detection voltage. Upon detection this bit
is set to "1" and will be reset by execution of flag reset (STOP F/F Reset = "1").
Through programming, therefore, it is possible to make various operation settings for when a decrease in the VDD
potential (battery voltage) occurs.
Note: Both serial interface and timer port are used for the interrupt function of the decreased voltage
detection circuit. When this interrupt is used, the interrupt function of the serial interface and the
timer port cannot be used.
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(2)
Detected power supply OFF function
Detected power supply OFF function detects the fact that the power supply is off during battery exchange or similar
procedures and actuates the backup state of the CPU circuit (VCPU pin) to keep it on hold.
If the detected power supply off function is enabled (BRAEK ENA bit (φL11(F)) = "1"), the VDD pin level is about
0.5 V or less and all functions stop. At this time, the VCPU pin power supply changes to low current consumption (0.5
µA or less); the LCD output pin and CMOS output port change to “L” level; the N-channel open-drain pins are all
automatically fixed to the off (high-impedance) state; and the PLL changes to off mode. If the power supply is
switched on again, the CPU will operate after a standby interval of 100 ms. The VDD OFF F/F bit enables detection of
whether the power supply has been switched off.
Note: Set the VDD pin level to GND level during power supply off. If VDD level potential remains, current
will be consumed by the VCPU pin.
Note: The BRAEK ENA bit (φL11(F)) permits VDD power supply break and power supply off detection
function.
Note: Use this function together with the decreased voltage detection function.
(3)
Backup control register by hardware
Decreased voltage detection and power supply off detection function control are accomplished through access of the
decreased voltage control port (φL11(E), φL11(F)); the decreased voltage detection setting data port (φL16(D),
φK11(D)); and the flag register (φK26).
φL11(E) (decreased voltage control 1)
Y1
Y2
Y4
Y8
WAIT
ENA
PLLoff
ENA
STOP
ENA
*
Permission for decreased voltage detection function
0: Prohibition Decreased voltage detection function suspended
1: Enable
Decreased voltage detection function operating
Permission for PLL stop function on decreased voltage detection
0: Prohibition
1: Enable
PLL off mode and PLL stop are executed
when decreased voltage is detected.
Permission for CPU stop function on decreased voltage detection
0: Prohibition
1: Enable
CPU stops when decreased voltage is detected.
(Note) Settings become invalid if the decreased voltage
detection function is suspended.
Note: If the decreased voltage detection function is not being used, set the WAIT ENA bit to "0" for
reduced consumption current.
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φL11(F) (decreased voltage control 2)
Y1
Y2
Y4
Y8
STOP
F/F
Reset
INT LB
SEL
TIM
SEL
BREAK
ENA
Power supplies off break enable/power off function enable
0: Prohibition
1: Enable
Function stop
Function operation
(Note) If not using this function, set this bit to "0" for consumption current
reduction.
Selection of decreased voltage detection operating timing
0: Detection is performed at a rate of once every 2 instruction cycles.
1: Detection is performed at a rate of once every 16 instruction cycles.
(Note) If this bit is set to "1", the consumption current of this function can
be decreased.
Permission of interruption by decreased voltage detection
(refer to the item on the interruption function)
0: Serial interface or timer port
1: Decreased voltage detection
Y1
φK26
STOP
F/F
Y2
Y4
Y8
VDD
OFF
F/F
0
Reset execution of decreased voltage detection F/F and power
supply OFF F/F:
Every time it is set to "1" decreased voltage F/F and power
supply OFF detection F/F are reset simultaneously.
Power supply off detection flag
0: Power supply off not detected
1: Power supply off detected
Decreased power supply detection flag
0: Over the decreased voltage detection setting voltage
1: Under the decreased voltage detection setting voltage
Note: The STOP F/F changes to the reset state, with a CPU standby interval (100 ms), after system reset; after
release of the CKSTP instruction; and after detection of power off using the power-off detection circuit.
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φL16(D)
φΚ11(D)
Y1
Y2
Y4
Y8
TR0
TR1
TR2
TR3
TR3 TR2 TR1 TR0 Data (HEX)
Decreased voltage
detection setting data
Note: Decreased voltage detection voltage detected
VDD pin level.
Note: Any fall below the decreased voltage
detection voltage will cause the STOP F/F to
be set to "1"; and the CPU will stop as a result
of decreased voltage detection.
Note: The decreased voltage detection value is a
standard value. The constant voltage of the
VEE pin is used as the standard voltage of the
decreased voltage detection circuit. Since this
VEE voltage varies from product to product,
the decreased voltage detection value also
varies at the same time.
Note: If a high-speed oscillator clock is being used
for the CPU clock, assign the decreased
voltage setting data to between 0H ∼ 6H (0.85
V ∼ 1.00 V). Do not make any other setting.
0
0
0
0
0
0.850
0
0
0
1
1
0.875
0
0
1
0
2
0.900
0
0
1
1
3
0.925
0
1
0
0
4
0.950
0
1
0
1
5
0.975
0
1
1
0
6
1.000
0
1
1
1
7
1.025
1
0
0
0
8
1.050
1
0
0
1
9
1.075
1
0
1
0
A
1.100
1
0
1
1
B
1.125
1
1
0
0
C
1.150
1
1
0
1
D
1.175
1
1
1
0
E
1.200
1
1
1
1
F
1.225
～
～
Decreased voltage detection, power supply off detection timing
～
～
(4)
Decreased voltage
detection voltage (V)
VCPU
VCPUPin
端子
GND
VDB
VDBPin
端子
～
～
～
～
GND
GND
～
～
VDD
VDDPin
端子
Backup
operates on a setting of approximately
0.5 V or less
約0.5V以下になるとバックアップ動作し
、 この電圧以上
but
will be canceled if the voltage exceeds
this value.
の電圧が印加されると解除されます
。
～
～
端子
XXOUT1
OUT1 Pin
～ ～
～ ～
Decreased
減電圧設定電圧
voltage
setting voltage
CPU停止
CPU
stop
（ 注１）
(Note
1)
Power supply
電源オフ検出
detection
（OFF
バックアップ
）
(Backup)
Stand-by
スタンバイ(約100ms)
(About 100 ms)
CPU
CPU動作
operation
CPU
stop
CPU停止
CPU
CPU動作
operation
～
～
Flag
reset execution
フラグリセット実行
(execution
of Reset
STOP F/F
Reset=1)
(STOP F/F
= 1の実行)
CPU動作
CPU
operation
CPU停止
CPU stop
～
～
CPU
CPU動作
operation
～ ～
～ ～
～ ～
～ ～
（ 注２）
STOP F/F
VDD OFF F/F
When interrupt has、been
interrupt is issued using STOP F/F.
割り込みを許可していると
STOPpermitted,
F/Fの立ち上がりで割り込みが発行されます
。
Example of timing operation
Note 1: Decrease voltage is detected and CPU operation is suspended. It is then necessary to detect the VDD
power supply voltage. When performing power off, therefore, ensure that the fall time from the
decreased voltage detection voltage to the detection of the power supply voltage (approximately 0.5 V)
is equal to or greater than the timing period for operation of decreased voltage detection (i.e., two or 16
instruction cycles). Failure to do so will cause CPU malfunction.
Note 2: STOP F/F is reset during standby time.
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TC9349AFG
(5)
Backup circuit
50 VPLL
62 RESET
C1
2
3
C2 VDB
4
VCPU
5
10
0.47 µF
10 µF
0.1 µF
10 µF
Schottky diode
0.1 µF
0.1 µF
POWER
470 µF
(Capacitor for
backup)
VDD
1 kΩ
10 kΩ
Reset input
Example Capacitor Backup Circuit (1)
62 RESET
VDD
C1
2
3
C2 VDB
4
VCPU
5
10
Schottky diode
0.47 µF
1 kΩ
10 kΩ
Reset input
Break input pin
50 VPLL
Release signal
input
0.1 µF
10 µF
0.1 µF
10 µF
0.1 µF
POWER
Example Battery Backup Circuit (2)
Note: If backup operation using a CKSTP/WAIT instruction is available, use release signal input to perform the
release operation as necessary. Moreover, on execution of the CKSTP command, connect an external
capacitance of 4.7 mF or more for the VCPU pin resistance as in Example Capacitor Circuit (2) above.
Note: The diode shown in the circuit diagrams should be a Schottky diode with a low VF and a small reverseleakage current.
Recommended diodes: 1SS357, 1SS393
Note: Set the backup capacitor capacity value according to the required backup time.
Note: The "H" level of reset input requires the application of a VCPU level voltage. Therefore set high
impedance at the time of reset off.
Note: The VCPU pin power supply is a logic power supply with a timing circuit, ALU, data memory and all
registers. The VCPU pin power supply should usually be retained at the time of backup.
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4.
PLL OFF mode
The PLL can be turned on or off depending on the contents of the reference selection port. If all the contents of the
reference selection port are set to "1", PLL off mode applies. (Refer to the section on the reference frequency divider.)
When the INH ENA bit is set to "1", the PLL can be turned on or off with the INH pin. The INH pin input serves
as PLL off mode at "L" level, and serves as PLL on mode on the "H" level. As a result, it is possible quickly to set
PLL off mode when changing batteries These data are accessed by an OUT1 instruction specifying 9h for the data
select port (φK/L1A) and [CN = 5H] for the operand.
Moreover, PLL off mode can be set by decreased voltage detection.
(Refer to the section in 3. Backup mode by hardware.)
The VPLL pin serves as low consumption current at the time of PLL off mode. Moreover, the power supply for a
VPLL terminal can be turned off at this time.
φL15(9)
Y1
Y2
Y4
0
0
0
Y8
INH
ENA
Enable to the PLL control by INH pin
0: Prohibition
1: Enable
P4-1/ INH pin
“L”: PLL off mode
“H”: PLL on mode
Note: PLL off mode applies during clock stop mode, hard wait mode, and when power off occurs as a result of
the power supply off detection function.
Note: The VPLL pin power supply is a prescaler and programmable counter power supply. When only the VPLL
pin power supply is turned off, the setting method of dividing frequency and the value of dividing
frequency are maintained because the VCPU power supply is used. Moreover, when the PLL is on, the
level of the applied VPLL pin voltage can supply power to the PLL regardless of the VDD pin or the
potential of the VCPU pin.
Note: INH input pin is used together with the P4-1 pin. The functionality becomes effective when the INH
input is enabled, and the external interrupt function (INTR2) and the break function are enabled.
Moreover, the input state can be judged by reading the P4-1 input data of an I/O Port 4 input port (φK33).
Note: The I/O port control port of P4-1 pin becomes invalid and is forced to enter the input state if INH input
has been enabled.
Note: Set the Y1/Y2/Y4 bit of the above-mentioned port to "0".
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{
Register port
The G-register, data register and DAL address register, which were mentioned in the description of the CPU, are arranged
on the I/O map, and treated as one of the internal ports. The carry flag can also be accessed from an I/O map. (Refer to the
section on I/O access of the stack register.)
Of these registers, the G-register, the carry flag, and the data register have a four-page interrupt stack register
corresponding to the four stack levels. On execution of interrupt processing, these contents are automatically stored in the
interrupt stack register together with the contents of data selection and automatically returned on execution of an RNI
instruction. (Refer to the section on the interrupt stack register.)
1. G-register (φL/K18, φL/K19)
This register addresses the row addresses (DR = 04H ~ 1FH) of the data memory during execution of the MVGD
instruction and MVGS instruction. The register is accessed with the OUT1/IN1 instruction for which [CN = 8H ~ 9H] has
been specified in the operand. Moreover, if the STGI instruction is used, data can be set to this register with a single
instruction.
This register has a four-level interrupt stack register. On the issuing of interrupt, the contents of the G-register are
evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are
executed and are ineffective when any other instruction is executed. Moreover, this register is unaffected
by the MVGD instruction and MVGS instruction.
Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 1FH in the Gregister (DR = 00H ~ 1FH).
Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRG0 ~ ISRG4
(φL/K10(8), φL/K10(9)) through programming.
φL/K10(6)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interruption
Interruptstack
stackpointer
pointer
Interrupt
stack
pointer
φL/K10(8)
Page
0
φL/K10(9)
Page
ISRG0 ISRG1 ISRG2 ISRG3
0
1
ISRG4
*/0
*/0
*/0
1
2
2
3
3
Interrupt stack register
Interruption stack register
At the time of RNI
At the
time
of
interrupt
thetime
timeof
ofinterruption
interrupt
AtAtthe
instruction execution
processing
execution
processing
execution
processing
execution
Y2
Y4
Y8
G0
G1
G2
G3
φL/K19
Y1
Y2
Y4
Y8
G4
*
*
*
Specification of the low address of a data memory
G-register
STGI instruction
Ｉ1
Ｉ2
Ｉ3
Ｉ*
42
Ｉ4
G3
G2
G1
G0
DR
0
0
1
0
0
04H
0
0
1
0
1
05H
0
0
1
1
0
06H
1
1
1
1
1
1FH
～
～
Ｉ0
G4
～
～
φL/K18
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2006-02-24
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2. Data register (φL/K1C ~ φL/K1F), DAL address register (φL/K11(0) ~ φL/K11(3)) and
control bit
The data register is 16-bit register for which the program memory data is loaded when the DAL instruction and DALR
instruction are executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of
the OUT1/IN1 instructions for which [CN = CH ~ FH] has been specified in the operand. This register can be used for
loading LCD segment decoding operations, radio band edge data and data related to binary-to-BCD conversion.
The data register has a four-level interrupt stack register. On the issuing of interrupt, the 16 data register bits are
evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
φL/K10(6)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interrupt stack
Interruption
stackpointer
pointer
Interrupt stack
Interruption
stack register
register
Y1
Y2
Y4
Y8
φL/K10(C) ISRd0 ISRd1 ISRd2 ISRd3
φL/K10(D) ISRd4 ISRd5 ISRd6 ISRd7
φL/K10(E) ISRd8 ISRd9
ISRd1 ISRd1
0
1
φL/K10(F) ISRd1 ISRd1 ISRd1 ISRd1
2
3
4
5
Page 0
Page 1
Page 2
Page 3
At the time of RNI
instruction execution
At the
of interrupt
At the
timetime
of interruption
processing
processingexecution
execution
DAL address register (AR)
Data
(16
Dataregister
registerdata
data(
16bits)
bit)
LSB
Y1
Y2
Y4
Y8
φL/K11
φL/K1C
ｄ0
ｄ1
ｄ2
ｄ3
(0)
φL/K1D
ｄ4
ｄ5
ｄ6
ｄ7
φL/K1E
ｄ8
ｄ9
ｄ10
ｄ11
φL/K1F
ｄ12
ｄ13
ｄ14
ｄ15
Y1
Y2
Y4
Y8
AR0
AR1
AR2
AR3
AR4
(1)
(2)
MVAR instruction
execution
MSB
DALR instruction
／DAL
instruction
/DAL instruction
execution
(3)
AR5
AR8
AR12
AR9
AR6
AR10
AR7
AR11
AR13 TROM
0
Data select
（ φL/K1A）
Program memory
16
bit data
16-bit
data
DALR instruction indirect
specification address
Note: Whenever it executes a DALR instruction,
Program memory area
(ROM)
Note: Each
a DALR of
instruction
executed,register
the
+1time
increment
the DALis address
done.
DAL address register(AR)
(AR) is
is incremented
by +1.
DAL instruction indirect
specification address
(ADDR3,r)
（ADDR3,r）
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TC9349AFG
The DAL address register (AR) is a register that specifies the program-memory-indirect when the DALR instruction is
executed with the 16-bit register.
There are two types of commands that load the program memory data: the DAL instruction and the DALR instruction.
For the DAL instruction, the contents of the (six-bit) ADDR3 in the operand and of the general register (r) become the
reference address of the program memory. For the DALR instruction, the 14 bits of the DAL address register become the
reference addresses. When the DAL instruction is executed, the program memory area (0000H ~ 03FFH) becomes the
reference area. All the areas in the program memory area can be referred to by executing the DALR instruction. Whenever
the DALR instruction is executed, the content of the DAL address register is increased by +1. Therefore data can be
continuously loaded.
Moreover, the content of the data register can be transmitted to the DAL address register in 14 bits with one instruction
by executing the MVAR instruction.
The contents of the DAL address register can be accessed in four-bit units on execution of an OUT1/IN1 instruction for
which [CN = 1H] is specified in the operand. DAL address register port is divided and indirectly specified with the data
selection port (φL1A) and set. The data of the specified port to be set beforehand is set and the data port corresponding to it
is accessed. Each time the data select port (φL/K11) is accessed it is increased by +1. Therefore the data can be continuously
accessed after setting up a data selection port.
Note: The DAL address register is valid only when the DALR instruction is executed, and is ineffective when
any other instruction is executed. Moreover, the DAL address register is unaffected by the DAL
instruction.
Note: This product has 8 k steps of ROM capacity; if 2000H ~ 3FFFH is specified in the DAL register and the
DALR instruction is executed, the contents of the data register will become indeterminate.
Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRd0~ISRd15
(φL/K10(C∼F)) through programming.
3. Carry flag (φL/K1B)
The carry flag is set when either Carry or Borrow occurs in the result of the calculation instruction execution and is reset
if neither of these occurs. This carry flag is accessed with an OUT1/IN1 instruction for which [CN = BH] has been specified.
The carry flag contains a four-level interrupt stack register. When an interrupt is issued, this bit is evacuated to the
interrupt register specified by the interrupt stack pointer, and is returned with the RNI instruction.
φL/K10(6)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interrupt stack
stack pointer
Interruption
pointer
φL/K10(B)
Page
Page
0
ISRCA
*/0
*/0
*/0
1
2
3
Interrupt stack
Interruption
stack register
register
At the time of RNI
instruction execution
At the
of interruption
At time
the time
of interrupt
processing execution
processing
execution
Y1
Y2
Y4
Y8
φ L/K1B
Ca
*/0
*/0
*/0
Carry
Carryflag
flag
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{
Stack register
The stack register consists of an address stack register (ASR) and an interruption stack register (ISR). A stack register is
used when subroutine call instructions and interrupt processing are executed. Interrupt stack registers comprise 26 Gregister, data select, carry flag, and data register bits, as described in the register port item and I/O map. These stack
registers are arranged on an I/O map, and are read from and written into with input and output instructions.
1. Address stack register (ASR)
The address stack register (ASR) is a 14 bit × 16 page register. When the subroutine call instruction and the interrupt
processing are executed, the value increased by +1 of the content of the program counter, i.e., the return address, is stored in
the address stack register. When interrupt processing is executed, a return address that is an interrupt processing execution
address is stored in the address stack register. This register consists of 16 pages and is specified by four address stack
pointer (ASP) bits. If transmitted to an address stack, an address stack pointer will be adjusted by -1. Then, after processing
of the subroutine or interrupt, the address stack pointer is increased by +1 with the RN/RNS instruction or the RNI
instruction, the content of the address stack register is transmitted to the program counter, and the program returns from the
subroutine or the interrupt processing.
An address stack register comprises 16 pages and features 16 nesting levels.
The address stack register and the address stack pointer are arranged on the I/O map, and their contents can be referred to
or rewritten.
φL/K10(0)
Y1
Y2
Y4
Y8
ASP
0
ASP
1
ASP
2
ASP
3
At
instruction // interruption
interrupt processing
execution
At the time of CAL instruction
processing
execution
At the time of RN/RNS/RNI instruction processing execution
Address stack pointer
(ASP)←ASP+1
(ASP)←ASP-1
Page specification
Y1
Y2
Y4
Y8
At the
the time
time of
of CAL
CALinstruction
instruction/ /
At
interrupt processing
processing execution
execution
interruption
φL/K10(2) ASR0 ASR1 ASR2 ASR3
ASR←(PC)+1
φL/K10(3) ASR4 ASR5 ASR6 ASR7
φL/K10(4) ASR8 ASR9 ASR10 ASR11
PC←(ASR)
At the time of RN/RNS/RNI
instruction processing execution
φL/K10(5)
Page 0
ASR12 ASR13
*/0
*/0
Program
Programcounter
couter (PC:
(PC 14
: 14bit)
bit)
Address
stackstack
register
Address
register
Program memory
area
（ROM）
(ROM)
Page
Page 1
Page 2
Page 33
Page
Page 15
Page
Note:
The program memory area consists of 16 kilobytes, and 13 bits are used. Therefore set the most
significant bit (ASR13) to “0”.
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2. Interrupt stack register (ISR)
The interrupt stack register (ISR) is a 14 bit × 16 page register. When interrupt processing is executed, the contents of the
26-bit G-register, data selection, carry flag, and data register are stored automatically. This register consists of four pages
and is specified with a two-bit interrupt stack pointer (ISP). When interrupt is generated, the G-register and other 26-bit
register contents are transmitted to the interrupt register. Simultaneously, the interrupt stack pointer is adjusted by -1. When
the RNI instruction is executed after the interrupt processing is finished, G-register and other 26-bit register contents are
returned and the interrupt stack pointer is increased by +1. In this way, the interrupt stack register (ISR) is used as a save
register for when interrupt occurs.
The Interrupt Stack register consists of four pages, and there are four interrupt stack levels.
The interrupt stack register and the interruption stack pointer are arranged on the I/O map, and their contents can be
referred to and rewritten.
φL/K10(0)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
At the time of interruption processing execution (ISP)←ISP+1
(ISP)←ISP-1
RNI instruction processing execution
Interrupt stack pointer
Interrupt stack register
Y1
φL/K10(8)
Page specification
φL/K10(9)
φL/K10(A)
φL/K10(B)
φL/K10(C)
φL/K10(D)
φL/K10(E)
Y2
Y4
Y8
φL/K18
ISRG0 ISRG1 ISRG2 ISRG3
ISRG4
*/0
*/0
Y1
Y2
Y4
Y8
G0
G1
G2
G3
*/0
*/0
φL/K19 G4
*/0
At the time of interruption
processing execution
φL/K1A SEL1 SEL2 SEL4 SEL8
*/0
ISRS0 ISRS1 SEL4 ISRS2
φL/K1B
CA
*/0
*/0
*/0
ISRd0 ISRd1 ISRd2 ISRd3
φL/K1C
d0
d1
d2
d3
ISRd4 ISRd5 ISRd6 ISRd7
φL/K1D
d4
d5
d6
d7
φL/K1E
RNI instruction
processing execution
d8
d9
d 10
d11
φL/K1F
d 12
d 13
d 14
d15
ISRCA
*/0
ISRd8 ISRd9
*/0
*/0
ISRd1 ISRd1
0
1
φL/K10(F) ISRd1 ISRd1 ISRd1 ISRd1
4
5
2
3
Page 0
Page 1
Page 2
G-register
Data select
Carry flag
Data register
Page 3
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3. I/O access of a stack register
The stack register is arranged in the I/O map. Therefore reading the state of the stack register and rewriting data are
possible. The contents of an address stack pointer (ASP) or an interruption stack pointer (ISP) can also be accessed. These
data are accessed with an OUT1/IN1 instruction for which [CN = 0H] is specified for the operand, and divided and arranged
by the data selection function.
The address stack register and the interrupt stack register have 16 and four pages respectively. When these ports are
accessed with the I/O instruction, the page is specified before the stack register is accessed. The address stack selection
specifies the page of the address stack register. The interrupt stack selection specifies the page of the interrupt stack register.
Rewriting of address stack registers is set from low-ranking bit, while the 14 address stack register bits are updated by
accessing high-ranking bits. Therefore care is required: it is still necessary to access the high-ranking bits even when only
low-ranking bits are being changed.
φL/K10(0)
φL/K10(0)
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ASP
0
ASP
1
ASP
2
ASP
3
ISP0
ISP1
*/0
*/0
Address stack pointer
Interrupt stack pointer
nesting level is setting / detectable.
nesting level is setting / detectable.
φL/K10(1)
φL/K10(7)
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ASS
0
ASS
1
ASS
2
ASS
3
ISS0
ISS1
*/0
*/0
Address stack select
Interrupt stack select
Interrupt stack register
Address stack register
Y1
Y2
Y4
Y1
Y8
Y2
Y4
Y8
φL/K10(8)
ISRG0 ISRG1 ISRG2 ISRG3
φL/K10(2) ASR0 ASR1 ASR2 ASR3
φL/K10(9)
ISRG4
φL/K10(3) ASR4 ASR5 ASR6 ASR7
φL/K10(A)
φL/K10(4) ASR8 ASR9 ASR10 ASR11
*/0
*/0
*/0
ISRS0 ISRS1 SEL4 ISRS2
φL/K10(B)
φL/K10(5)
ASR12 ASR13
Page 0
*/0
ISRCA
*/0
*/0
*/0
*/0
φL/K10(C)
1
ISRd0 ISRd1 ISRd2 ISRd3
2
φL/K10(D)
3
ISRd4 ISRd5 ISRd6 ISRd7
φL/K10(E)
ISRd8 ISRd9
15
ISRd1 ISRd1
0
1
φL/K10(F) ISRd1 ISRd1 ISRd1 ISRd1
2
3
4
5
Page 0
1
2
3
Note: The program memory area is 16 kilobytes and 13 bits are used. Therefore it is necessary to set the most
significant bit (ASR13) of the address stack to "0".
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{ Interrupt function
There are six types of peripheral hardware for which the interrupt function can be utilized: the INTR1 terminal, the
INTR2 terminal, the timer port, the serial interface, the timer counter, and the decreased voltage detection circuit.
This peripheral hardware will issue an interrupt request signal if certain conditions are satisfied. On reception of an
interrupt, the data for the G-register, data selection, carry flag, and data register are shunted to an interrupt stack register,
and the return address is shunted to the address stack register. The process then branch to the vector address determined by
the various interrupt factors and starts the related interrupt processing routine.
The interrupt routine requires preprocessing and post-processing to enable recovery of the same operational state that
prevailed when the interrupt occurred. On interrupt, the G-register, data selection, carry flag, and data register are
automatically shunted to the interrupt stack register; they are returned from the interrupt stack register on execution of the
return instruction for interrupt (RNI). Registers used with other ALU and memory data that cannot be broken must be
shunted to and recovered from the data memory for interrupt through the use of programming.
Interrupt priority can be set through programming. During interrupt processing, processing of an interrupt with a priority
lower than the interrupt currently being processed is prohibited.
The data of the interrupt stack register and the address stack register return on executing of the return instruction for
interrupt (RNI), and the interrupt processing ends.
1. Interrupt control circuit
The interrupt control circuit consists of an interrupt enable flag, interrupt latch, and interrupt priority circuit block. These
performs are set and controlled with OUT2/IN2 instructions.
(1)
Interrupt enable flags
The interrupt enable flags consist of individual enable flags corresponding to the four interrupt factors, and a
master enable flag, which permits and prohibits the whole interrupt processing. The individual enable flags permit
and prohibit interrupt corresponding to each interrupt factor. The enable registers of these flags indicate permission if
set to “1”, prohibition if reset to “0”.
An individual enable flag is accessed with OUT2/IN2 instructions for which [CN = 0H] has been specified in the
operand.
The interrupt master enable flag sets interrupt permission and prohibition. On execution of the EI instruction, the
master enable flag is set to “1” and interrupt is permitted. On execution of the DI instruction, the master enable flag is
reset to “0” and interrupt is prohibited. When an interrupt request permitted by the individual enable flag is issued in
the interrupt-enabled state, the CPU receives the interrupt and, by branching to the different vector addresses,
executes the interrupt routine. In interrupt reception processing and interrupt return processing, the master enable flag
is in the hold state. When all other interrupts are to be prohibited during interrupt processing, therefore, the DI
instruction is executed and interrupt is prohibited.
The interrupt master flag can be read into a data memory by an IN2 instruction for which [CN = 2H] is specified in
the operand.
φLK20
Y1
Y2
Y4
Y8
EF1
EF2
EF3
EF4
Individual enable flag:
EF1･･･INTR1 pin
EF2･･･INTR2 pin / Timer port
EF3･･･Serial interface / Timer port /
Decreased voltage detection
EF4･･･8 bit timer counter
φK22
Y1
Y2
Y4
Y8
IMF
0
0
0
Master enable flag
“0” ･･･Prohibition
“1” ･･･Enable
Reset to “0” on acceptance of interrupt or on execution of the DI instruction.
Reset to “1” on execution of the RNI or of the EI instruction.
Note: Do not change the setting of the individual enable flag during interrupt processing.
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2006-02-24
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(2)
Interrupt latch
The interrupt latch is set to “1” through the issuing of an interrupt request from peripheral hardware. If interrupt is
enabled, an interrupt reception request will be sent to the CPU, which will execute the interrupt routine and carry out
branching. The data latch is automatically reset to “0” if an interrupt is received at this time. Interrupt latch data can
read by the program and the existence or nonexistence of an interrupt request can be determined on an individual
basis. An interrupt latch that has been set to “1” by interrupt request can also be reset to “0”, and the interrupt request
can be canceled or initialized.
φL21
Y1
Y2
Y4
Y8
ILR1
ILR2
ILR3
ILR4
Interrupt latch reset
φK21
If set to “1”, the interrupt latch is reset to “0”.
Y1
Y2
Y4
Y8
IL1
IL2
IL3
IL4
Set to “1” on issuance of interrupt request and reset
to “0” on interrupt acceptance.
0: No interrupt
1: Interrupt
Interrupt latch data
IL1･･･INTR1 pin
IL2･･･INTR2 pin
IL3･･･Serial interface / Timer port / Detected decrease voltage
IL4･･･8-bit timer counter
Note: Do not execute interrupt latch reset during interrupt processing.
(3)
Interrupt priority circuit block
The interrupt priority circuit is a circuit that determines the order in which interrupts are processed if interrupt
requests occur simultaneously or if interrupt is enabled after multiple interrupt requests have occurred. Vector
addresses to the interrupt routine are also generated by this block. The interrupt priority level can be set through
programming. The priority level is determined by setting the interrupt ID No. corresponding to each interrupts factor
to the interrupt priority level setting port. The interrupt priority level setting ports are composed of priority levels 1 to
4, and the circuit sets the interrupt ID No. in order of the priority levels 1 to 4. For instance, when the interrupt
priority level is set in the order of serial interface (2), INTR1 pin (0), INTR2 pin (1) and timer counter (3), then 2h, 0h,
1h, and 3h (φL14(6) = 2h, φL14(7) = dh) are set to priority levels 1 to 4. These ports can be accessed with an OUT1
instruction for which [CN = 4H] is specified in the operand and 6h and 7h are specified for the data selection ports
(φK/L1A).
Interrupt ID No.
Interrupt Factor
Vector Address
0
INTR1 pin
0001H
1
INTR2 pin / timer port
0002H
2
Serial interface / timer port / decreased voltage detection
0003H
3
Timer counter
0004H
Y1
φL14(6)
Y2
Y4
Y8
PRI1-0 PRI1-1 PRI2-0 PRI2-1
Priority 1
Y1
φL14(7)
Priority 2
Y2
Y4
Y8
PRI3-0 PRI3-1 PRI4-0 PRI4-1
Priority 3
Priority 4
Interrupt priority setting port
Interrupt ID No. is set.
Note: Do not set the same interrupt ID No. to each interrupt priority level.
Note: Do not change the interrupt priority setting during interrupt permission and interrupt processing.
Note: Interrupt priority after system reset reverts to an order corresponding to that of the interrupt ID No.’s
(i.e., ID No. 0 → Priority Level 1).
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2006-02-24
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(4)
Change of interrupt factor
From among the ID numbers, ID Nos. 1 and 2 can be used to select, respectively, INTR2 pin / timer port and serial
interface / timer port / decreased voltage detection. These changes are made through the control port in each block.
Since selection is possible through the following settings, select according to the specification. These settings are also
made when routine initialization is being carried out. Do not perform the change while interrupt enable or interrupt
processing is in progress. Carry out any change in a state other than these states, and always reset the interrupt latch
after the change.
Decreased
voltage
detection
control
2
Detected
decrease
voltage
control
2
Y1
Y2
Y4
Y8
INT LB
SEL
φL11(F)
Interrupt
factor
of interrupt
ID No.
Interruption
factor
of interruption
ID2No. 2
INT LB
ENA
SEL
Y1
Y2
Y4
CK
SEL
φL2A
Y8
ENA
CK
SEL
Interruption
function
Interrupt function
0
0
*
SIO
Interrupt
SIO
Interruption
0
1
0
100 Hz
Timer
Interrupt
100Hz
Timer
Interruption
0
1
1
200Hz
Timer
Interruption
200 Hz
Timer
Interrupt
1
0
*
Decreased
voltagevoltage
detection
interrupt
Detected
decrease
interruption
1
1
*
Prohibition
Timerinterruption
interrupt control
Timer
control
Y1
φL22
Y2
Y4
Y8
POS2
NEG2
INTR2 control
Interruption
factorof
ofinterrupt
interruption
ID No.
Interrupt factor
ID No.
1 1
POS2 NEG2
CK
SEL
Interruption
function
Interrupt function
0
0
0
100
Hz Timer Interruption
Interrupt
100Hz
0
0
1
200
Hz Timer
TimerInterruption
Interrupt
200Hz
1
0
*
0
1
*
1
1
*
50
Rising edge
External
interrupt
External
interruption
of INTR2
INTR2 pin
pin
Falling edge
Bothedges
edge
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2006-02-24
TC9349AFG
2. Interrupt Reception Processing
The interrupt request is held until interruption is received, it interrupts by system reset operation or the program and it
resets a latch to "0" through programming. Interrupt reception operation is as shown below.
1) Each item of peripheral hardware outputs each interrupt request and sets the interrupt latch to “1” if the interrupt
conditions are fulfilled.
2) If an interrupt enable flag corresponding to a particular interrupt factor or a master enable flag is set to “1”, the
CPU receives its interrupt, and the corresponding interrupt latch is reset to “0”.
3) Any interrupt with a priority level below the accepted interrupt factor is prohibited.
4) The contents of the address stack pointer (ASP) and the interrupt stack pointer (ISP) are adjusted by -1.
5) The contents of the program counter (PC) are evacuated to the address stack register. The contents of the carry flag
(Ca), G-register (G-REG), data selection and data register (DATA) are evacuated to the interrupt stack register. At
this time, the contents of the program counter change to the next address for the time the interrupt was received or
the next address for which interrupt was enabled.
6) The contents of the vector address corresponding to the received interrupt are transferred to the program counter.
7) The contents of the vector address are executed.
Steps 2) to 6) are executed in one instruction cycle. This instruction cycle is called an “interrupt cycle”.
In the case of an interrupt enable period
Instruction
Interrupt
Interrupt
ion
cycle
cycle
EI
instruction
IMF
( Master enable flag )
Interrupt signal
Interruption
signal
Interrupt signal
Interruption
signal
IL
(Interrupt latch)
( Interruption
latch)
1 instruction
cycle
Interruption
processing
routine
Interrupt
processing
routine
Interruption
enableperiod
period
Interrupt enable
Interruption
reception
Interrupt
reception
In the case of an interrupt retention period
EI
Instruction
instruction
Interrupt
Interrupt
ion
cycle
cycle
IMF
( Master enable flag )
Interrupt signal
Interruption
signal
Interrupt signal
Interruption
signal
IL
(Interrupt latch)
( Interruption
latch)
Interruption
enable
period
Interrupt
retention
period
51
Interruption
processing
routine
Interrupt processing
routine
Interruption
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Interrupt reception
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3. Return Processing from the Interrupt Processing Routine
The only RNI instruction is used to return the operational state to the processing being carried out before reception of
the interrupt from the interrupt routine.
Execution of the RNI instruction causes the following processing to be carried out automatically in sequence.
1)
2)
3)
Interrupt of the priority below the returning interrupt factor is permitted.
The contents of the interrupt stack register specified by the interrupt stack pointer are returned to the G-register,
data selection, carry flag, and data register; and the contents of the address stack register data specified by the
address stack pointer are returned to the program counter.
The contents of the address stack pointer (ASP) and the interrupt stack pointer (ISP) are adjusted by +1.
The RNI instruction for the above-mentioned processing is processed in one instruction cycle.
Note: Always execute the return from interrupt using the RNI instruction.
4. Interrupt Processing Routine
If interrupt has been permitted, the CPU accepts the interrupt request regardless of the program executed at that time
when the interrupt request is issued. To return to the original program on execution of interrupt processing, therefore, it is
necessary to restore the original operational state, as if interrupt processing had not occurred. For this reason, it is necessary
to perform shunting and return operations within the interrupt processing routine, at least for those register and data
memories that can be operated within the interrupt processing routine.
(1)
Evacuation processing
When the CPU accepts the interrupt, it automatically evacuates the content of G-register, data selection, carry flag
and data register to the interrupt stack register. The contents of the area of the data memory and the general register
used by the interrupt processing routine are evacuated as necessary by the program before use
(2)
Return processing
The contents of the G-register, data selection, carry flag, and data register return automatically when the RNI
instruction is executed. Therefore the return processing works in the opposite way to that of the evacuation
processing previously mentioned.
5. Multiplex Interrupt
Multiplex interrupt is a method of processing other interrupts during interrupt processing.
As shown in the figure, the separate interrupt factors C and D are processed during the interrupt processing of interrupt
factors A and B. The depth of interrupt at this time is called the interrupt level.
Main
routine
Interrupt
level 1
Interrupt
level 2
MAIN
B
D
A
B
Interrupt
level 3
Interrupt
level 4
C
D
C
Example of multiplex interrupt
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Exercise particular care regarding the following points when using multiplex interrupt:
1)
2)
3)
The priority of the interrupt factors
Restrictions on the address stack levels used when interrupt requests are issued.
Shunting processing for the carry flag, data memory, etc.
(1)
Priority of interrupt factor
The order of priority for multiplex interrupt becomes A < B < C < D as shown in the figure.
When an order of priority of this type applies, the processing of interrupt C must have priority during the interrupt
processing of A or B, while the processing of interrupt D is in turn given priority during execution of interrupts C.
Multiplex interrupt requires the setting of priority levels. For example, for interrupt factors A and B, let us assume
that a request is issued for factor A every 10 ms, with an interrupt processing time of 4 ms; and that a request is issued
for factor B every 2 ms, with an interrupt processing time of 1 ms. When there is no order of priority for A and B,
then, should an A interrupt request occur during the interrupt processing of B, it may sometimes be the case that the A
interrupt processing is executed and the B interrupt processing is not. In such a case, it is necessary to set the order of
priority of A < B through programming and prohibit any A interrupt during interrupt processing of B, and also allow a
B interrupt to be received even during the interrupt processing of A.
Priority ordering of this kind is set through the priority level ports (φL14(6), φL14(7)), described in the item on the
interrupt priority circuit block. Setting interrupt priority in the order of factors A < B < C < D prohibits during the
processing of a prioritized interrupt any interrupt with the same priority level or lower. For example, all interrupts are
prohibited during factor D interrupt, while during processing of a factor C interrupt, factor D interrupt is enabled
while factor A, B and C interrupts are prohibited. Any change in the interrupt order is prohibited during the
processing of an interrupt. To prohibit the acceptance of a higher-priority interrupt factor during the execution of a
lower-priority interrupt, use a DI/EI instruction to prohibit interrupt in the program area where prohibition is required.
(2)
Restriction of address stack levels
As described in the section on interrupt reception processing, when an interrupt request is issued, the return address
is automatically evacuated to the address stack register; and the G-register, data selection, carry flag and data register
are automatically evacuated to the interrupt stack register. There are four interrupt stack levels and 16 address stack
levels. The content of the interrupt stack register and the address stack register is broken when the interrupt stack
levels and the address stack levels are exceeded; it is therefore necessary to use them in such a way to ensure they are
not exceeded. Since it can also be used with the execution of a subroutine call command, the address stack register
should take into account the address stack levels for both interrupt and subroutine calls.
(3)
Evacuation processing
When using multiplex interrupt, it is necessary to secure the evacuation area for evacuation processing separately
for each Interrupt factor.
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{ External Interrupt and Timer Counter Functions
There are two types of pin for external interrupt: INTR1 and INTR2. An interrupt request is issued on detection of the
edge of the signal applied to pins INTR1 and INTR2, whether rising, falling or both. The interrupt input pins also combine
the functions of I/O port; break during backup; and, in the case of the INTR2 pin, PLL INH input pin.
The timer counter is an 8-bit binary counter and has timer mode and pulse width measurement mode functions. In pulse
width measurement mode, the pulse width input from the external interrupt pin (INTR1) is measured. This can be used for
purposes such as detecting the leader pulse of a remote control.
1. External Interrupt Function
There are two types of pin for external interrupt, INTR1 and INTR2, and an interrupt request is issued on detection of the
edge of these inputs. The inputs incorporate a Schmitt circuit and a noise canceller, the frequency of the CPU clock
(low-speed oscillation clock: 75 kHz; high-speed oscillation clock: 300 ∼ 600 kHz) being used for the noise-filtering clock.
Any pulse of less than 1 ~ 3 clocks of the CPU clock is removed as noise; and an interrupt is generated when a pulse at or
over 1 ~ 3 clocks of the CPU clock (at the time of a 75 kHz oscillation: 13.3 ~ 40 µs) is input. Either the rising or the falling
edge, or both, can be selected for each pin.
The pin used for the external interrupt function also serves as an I/O port. Interrupt will be permitted if edge selection is
enabled through use of the external interrupt control port. The external interrupt input state can be read from the I/O port 4
input data port (φK33), which is used in combination.
The INTR1 pin is used in combination with the input pin of the pulse width measurement mode function of the timer
counter. The INTR1 control port is also used to control the logical setting of the pulse.
(Refer to the section on the timer counter.)
The external interrupt of the INTR2 pin is selected together with the timer port interrupt. When external interrupt of the
INTR2 pin is used, it is necessary to set the timer port. (Refer to the sections on the timer port and on changing the interrupt
factor.) The program will branch to address 0001H if an INTR1 pin interrupt is received, to address 0002H if an INTR2 pin
interrupt is received.
φ L22
Y1
Y2
Y4
Y8
POS1
NEG1
POS2
NEG2
INTR1
Control
INTR2
Control
INTR2 external interruption / Control of timer port interruption
POS2 NEG2
0
0
1
0
0
1
1
1
Interrupt Function
100/200Hz timer interrupt
Edge Select
I/O port function
Rising edge
External interrupt of INTR2 pin
Falling edge
Both edges
Control of INTR1 external interruption
POS1 NEG1
0
0
1
0
0
1
1
1
Interrupt Function
Edge Select
External interrupt prohibition
I/O port function
External interrupt of INTR1 pin
Falling edge
Rising edge
Both edges
Note: The function becomes effective when INH input function and break function are permitted on setting of
the external interrupt function.
Note: When interrupt is permitted, the I/O port 4 control port becomes invalid and is forced to change to an
input port.
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2. Timer Counter Function
The timer counter consists of an 8-bit binary counter, a counter coincidence register, a digital comparator, and a control
circuit for controlling these items.
The timer counter function has a timer mode and a pulse width measurement mode.
The timer mode is a mode for detecting a regular time. The coincidence signal pulse is output and the interrupt request is
issued when the timer clock is input to the 8-bit binary counter and is in agreement with the contents of the counter
coincidence register. In pulse width measurement mode, measurement of pulse width and detection of pulse width are
performed through calculation of the timer counter between "H" or "L" levels input from the INTR1 pin. Pulse width
detection can be used to detect the leader pulse of remote controls.
For both timer mode and pulse width measurement mode, a timer clock of 25 kHz or 1 kHz can be used.
(1)
Timer counter register configuration
The timer counter register consists of counter data, a coincidence register and a control register.
φL2A
φL2B
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Timer counter coincidence data
φK2A
A coincidence pulse will be output if the data agrees with
the timer counter.
φK2B
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Timer counter data
Timer counter data is read into data memory as binary data.
φ L 2D (Timer counter control)
Y1
CK
Y2
Y4
Y8
PW
CR
Disable
CR
Timer counter reset･･･Whenever sets “1”, counter is reset.
Enable counter reset by coincidence pulse.
"0" ･･･Enable
"1" ･･･Prohibition
"0"･･･Timer mode
Selection of timer mode and pulse width
measurement mode
"1"･･･Pulse width
measurement mode
"0"･･･25 kHz
Selection of timer clock
INTR1 control
(φ L22)
"1"･･･1 kHz
Clock enable logic of INTR1 input signal
(Effective only when CR Disable = 0 is set.)
Reset condition of INTR1 input signal
(Effective only when CR Disable = 0
is set.)
POS1
NEG1
0
0
1
0
Counted in “H” level
Falling edge
0
1
Counted in “L” level
Rising edge
1
1
Always in operation
Both edges
Not counted
⎯
Note: This becomes invalid when the settings CR Disable = 1 and PW = 0 apply as above.
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(2)
Timer mode
Timer mode is a mode for detecting a regular time. Whenever the regular time is detected, an interrupt request is
executed and the counter reset. At this time, the control bit is set to 25 kHz or 1 kHz, the PW bit to “0”, and the CR
bit to “0”.
At this time, the timer coincidence data is
Timer time = IDn (coincidence data) × timer clock cycle
IDn ≧ 1 (HEX)
This sets the data for required timer interval.
25 kHz or 1 kHz
Timer clock
IDn
Timer data
00H
01H
02H
03H
ID (N − 1)
IDn
00H
01H
02H
03H
Coincidence pulse
Request for interrupt and
reset timer counter.
(3)
Pulse width measurement mode
Pulse width measurement mode enables the detection and measurement of the “H” or “L” pulse width of the
INTR1 input.
The control bit at this time is used to select 1 kHz or 25 kHz for the timer clock and set “1” to the PW bit. If the
PW bit is set to “1”, the INTR1 input becomes the input enable signal of the counter clock and the timer clock is
input to the timer counter in the enabled state. Then, if the coincidence data values and counter values match, a timer
interrupt is issued.
The input logic is used in combination with the external interrupt logic setting (POS1/NEG1 bit).The timer counter
is “H” level if the POS1 bit and NEG1 bit are set to “1” and “0” respectively; and “L” level if the POS1 bit and
NEG1 bit are set to “0” and “1” respectively.
• Pulse width detection
The pulse width detection function detects a pulse width equal to or greater than a regular pulse width. This
function can be used for detection of the leader pulse of remote controls and data detection. At this time the control
bit is set to “0” for the GR Disable bit, and the timer counter is automatically reset on completion of pulse width
measurement. With automatic reset, no timer interrupt will be issued when the pulse width is below the set value.
Only on input of a pulse equal to or greater than the detection pulse width is a timer interrupt issued and detection
enabled. This feature enables the detection of data from remote control devices when used in combination with
external interrupts.
The detection pulse width at this time is as follows:
Detection pulse width = Idn (coincidence data) × the cycle of timer clock
Idn ∞ 1(HEX)
• Measurement of pulse width
When the pulse width is being measured, the CR Disable bit of control bit is set to “1”, setting to prohibited status
the execution of reset to the timer counter when pulse width measurement is finished. On completion of pulse width
measurement, the issuing of the external interrupt is detected, and the pulse width can be measured by referencing the
timer counter value. The pulse width at this time is as follows:
Pulse width = CTn (timer counter data) × the cycle of timer clock
After reading of the timer counter data (CR = “1”), the timer counter is reset and initialized.
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INTR1 input
Timer clock
Timer counter data
01H 02H
03H 00H
01H
02H
03H
ID(n-1)
IDn
ID(n+1) ID(n+2) 00H
Coincidence pulse
is issued if counter
data and
When the counterInterrupt
data is corresponding
to the agreement
coincidence data correspond
data, it issues it interrupt.
Counter reset pulse
External interruption pulse
External interruption issue
Example of timing of pulse width detection operation in pulse width
measurement mode (CR Disable = “0”)
INTR1 input
Timer clock
Timer counter data
01H 02H
03H
00H
01H
02H
03H
ID(n-1)
IDn
ID(n+1) ID(n+2)
00H
Coincidence pulse
Instruction execution
Interrupt
is issued
counter
data and
When
the counter
dataif is
corresponding
to the
coincidence
data correspond
agreement
data, it issues
it interrupt.
Reading of counter data
CR="1"
CR="1"
Reading of counter data
External interruption pulse
External interruption issue
Example of timing of pulse width detection operation in pulse width
measurement mode (CR Disable = “1”)
Note: The counter is reset whenever the CR bit is set to “1”. Execute reset if necessary.
Note: The end of measurement can be detected through the concomitant use of external interrupt.
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{ Internal Interrupts and the Interrupt Function
There are four types of internal interrupt: timer port, timer counter, serial interface, and decreased voltage detection. Of
these, three types of interrupt: timer port; serial interface; and decreased voltage detection; can serve a double purpose and
act as interrupts for other factors. Select and use the necessary interrupt factor.
(Refer to the section on changing the interrupt factor.)
1. Timer Port Interrupt
The timer port interrupt is generated on the rising edge of a 100 Hz or 200 Hz timer. For details, refer to the item on the
timer port function.
2. Timer Counter Interrupt
The timer counter interrupt is generated if the timer counter value corresponds to the coincidence register value. For
details, refer to the item on the timer counter function.
3.
Serial Interface Interrupt
The serial interface interrupt is generated on the ending of serial interface operation. For details, refer to the item on the
serial interface function.
4.
Interrupt for Decreased Voltage Detection
The interrupt for decreased voltage detection is generated on detection of decreased voltage. For details, refer to the item
on the decreased voltage detection function.
5.
Interrupt Block Configuration
INT LB SEL
ENA
Interruption
of Serial
inter interrupt
face
Serial
interface
Timer port
interrupt
Interruption
of timer
port
Interruption
of Detected
Decreased
voltage
decrease
voltage
detection
interrupt
CPU clock
External
interruption
～
Selector
POS2/
NEG2
Interruption
of Timer
counter
Timer counter
interrupt
INTR2
Noise
canceller
Edge
detected
Selector
INTR1
Noise
canceller
Edge
detected
Selector
ILR1
Ｓ
～
POS1/
NEG1
ILR2
R
ＩＬ1
CK
R
Ｓ
ＩＬ2
ILR4
Ｓ
R
ＩＬ3
EF2
R
ＩＬ4
EF3
EF4
25 kHz
1 kHz
EF1
Ｓ
ILR3
Logic
Selector change
POS1/NEG1
PRI1-1/1
PRI1-2/1
PRI1-3/1
PRI1-4/1
Decoder
Priority determination ・Vector address
generate circuit
La
Vector address
CT0～CT7
8-bit
8 bit binary
binary counter
counter
+
PW
R
Coincidence pulse
Coincidence register (ID0 ~ ID7)
Interrupt
reception signal
Interruption
receiving signal
PW
CR Disable
EI
instruction
IMF
Ｓ
R
DI
instruction
PW
CR Disable
CR
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{
Timer port
Equipped with 200 Hz, 100 Hz, 10 Hz and 2 Hz F/F bits, the timer is used for counting of clock operations and of tuning
scan mode. Through selection in the timer port for interrupt, interrupts can be generated with a 100 Hz or 200 Hz rising
edge.
1. Timer port
Timer
interrupt control
control
Timer
interruption
φL2A
Y1
Y2
Y4
Y8
2Hｚ
F/F
Timer
CK
SEL
ENA
Timer
Selectport
of timer
interrupt
interruption
selection
(refer
(refer
toto
section
the section
in interruption
on the interrupt
function)
function)
0 : Serial interface / Decreased
Detected decrease
voltage function
voltage detection
1 : Timer port
Selection
of interrupt timer
Select of interruption
0 : 100 Hz
1 : 200 Hz
The 22 Hz
Hz timer
is reset
“1”istime
set. “1” is set.
The
F/Fwhenever
is reset every
The counters for 200 Hz, 100 Hz, and 10 Hz bits, and for
100 Hｚ,
and
under
1 kHz
bits
are reset
1The
kHz200
andHz,
under,
are 10
reset
every
time
“1” is
set.
whenever “1” is set.
Y1
φK2A
2Hｚ
F/F
Y2
Y4
Reset port
Y8
10Hｚ 100Hｚ 200Hz
The timer ports are accessed with an OUT2/IN2 instruction for which [CN = AH] has been specified in the operand.
2. Timer port timing
The 2 Hz timer F/F is set with the 2 Hz (500 ms) signal and is reset by setting “1” in the 2 Hz F/F of the reset port. This
bit is usually used as a clock counter.
The 2 Hz timer F/F can only be reset with the 2 Hz F/F of the reset port; therefore not resetting within a 500 ms cycle
will result in count errors and failure to obtain the correct time.
2 Hz F/F output
2 Hz F/F reset execution
t < 500 ms
2 Hz clock
500 ms
t
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The 10 Hz, 100 Hz and 200 Hz timer is output to 10 Hz, 100 Hz and 200 Hz bits respectively with frequency pulses of
100 ms, 10 ms and 5 ms respectively. The 10 Hz and 100 Hz timers have a duty cycle of 50%. The 200 Hz timer is output at
a duty cycle of 60% with a high level of 3 ms and a low level of 2 ms. Counters at 1 kHz or below will be reset whenever
the reset port’s timer bit is set to “1”.
100 Hz or 200 Hz timer can be selected for the interrupt. When timer interrupt is enabled, interrupt is generated on the
rising of this pulse. If interrupt is received, a program will branch to 0003H address.
3 ms
200 Hｚ
2 ms
100 Hｚ
5 ms
Interruption
the
rising
edge
ofof
the
timer.
Interruptisisissued
issuedbyon
the
rising
edge
the
timer.
10 ms
10 Hｚ
50 ms
100 ms
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Input and Output Ports
A maximum of 45 I/O ports are available for the input/output of control signals. These 45 I/O ports include 36 CMOS I/O
ports and 9 N-ch open-drain I/O ports. Up to one exclusive input ports and two exclusive output ports are also available.
I/O port 3 can be set to the pull-down or pull-up state, while I/O ports 3, 4, 6 and 8 can be set to backup release (break
function). Individual input and output ports also serve as the pins for peripheral equipment. Switch them according to the
specifications.
1. I/O Ports, Input-only Ports (IN/IN2) and Output-only Ports (OT1/OT2)
Each of the I/O ports, exclusive input ports and exclusive output ports has the following dual-purpose functions and
features.
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I/O port 3 is a CMOS I/O port. Pins P3-0 to P3-2 are also used as the serial interface and pin P3-3 is also used as a pulse
counter input pin. These pins can be set to pull-up or pull-down state and to the break function.
(→ Refer to the sections on Serial interface and Pulse counter.)
I/O ports 4 and 5 are CMOS I/O ports. Pins P4-0 and P4-1 are also used as external interrupt input pins. Pin P4-1 is also
used as the PLL inhibit input pin. Pin P4-2 is also used as the buzzer output pin. Pins P4-3 and P5-0 to P5-3 are also used as
the electronic volume pins. Pins P4-0 to P4-3 can be set to the break function.
(→ Refer to the sections on External interrupt, Back-up, Buzzer output and Volume.)
I/O port 6 is a N-ch open-drain I/O port. Voltage can be applied up to the VDB pin level. This port is also used for the
6-bit A/D converter analog input, and can be set to the break function.
(→ Refer to the sections on A/D converter.)
I/O port 8 is an N-ch open-drain I/O port. Voltage can be applied up to 5.5 V. Pin P8-0 is also used as the doubler voltage
detection input pin for the DC-DC converter of VT. Pin P8-1 is also used as the clock output pin for the DC-DC converter
of VT. Pins P8-1 to P8-3 are also used as the serial interface. These pins can be set to the break function.
(→ Refer to the sections on the DC-DC converter of VT and Serial interface.)
I/O port 9 consists of the N-ch open-drain pin (P9-0) and the CMOS pins (P9-1 and P9-2). P9-0 is also used as the Tr
output pin for LPF. Pin P9-1 is also used as the MUTE output pin. P9-2 is also used as the clock output pin for the DC-DC
converter. In addition, pin P9-2 is pulled down to serve as the test mode input pin when pin RESET is at the “L” level.
This pin must be in the open state or at the “L” level during test mode input.
(→ Refer to the sections on MUTE output, DC-DC converter of VT and Phase comparator.)
I/O ports 10 to 16 are CMOS I/O ports, and also serve as the LCD driver output pins. Pins P16-2 and P16-3 are also used
as high-speed oscillators. (→ Refer to the sections on the LCD driver and System clock control circuit.)
The exclusive input port is the IN input pin of IFin input combination. The IN input can be switched by the program.
The two phase comparator output pins can be used as the exclusive output ports (OT1/OT2). These pins output any of
three values; an “H” level that is the VDB pin level, “L” level and High impedance.
The I/O circuit of 41 pins at I/O ports 3, 4, 5, 8, 9 and 10 to 16 uses the VLCD (3 V) power supply pin. Voltage can be
applied up to 3 V, and a stable output current can be obtained because the output is not heavily reliant on the VDD pin
power supply. Pin IN2 of I/O port 6 can accept voltage up to the VDB pin level and pin IN can accept voltage up to the
VPLL pin level
Note: When setting individual pins as input/output ports, refer to the corresponding sections on the
Dual-purpose Function.
Note: The “H” level of OT1/OT2 output is the VDB level. All the other CMOS I/O ports output the VDD level.
Note: The IN input at the input-only port uses the VPLL power supply. The “H” level is VPLL × 0.8 or higher and
the “L” level is VPLL × 0.2 or lower. When the VPLL power supply is turned off with the tuner off, IN input
becomes unfixed. The input level for the other pins is VDD × 0.8 or higher at the “H” level and VDD × 0.2
or lower at the “L” level.
Note: After a system reset, pin MUTE/P9-1 is set to the MUTE output and all the other input and output pins
are set to the I/O port input or high impedance. The MUTE output becomes the “L” level during system
reset, and becomes the “H” level after release.
Note: When the clock stop instruction is executed, the “L” level is outputted at all the pins that have been set to
the I/O port ouput. After the clock stop is released, the previous state is outputted.
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2.
Control Ports of Input and Output Ports
Y1
Y2
Y4
Y8
SEL1 SEL2 SEL4 SEL8
φL12( Data port 1)
Data select
(0)
Y2
Y4
Y8
-0
-1
-2
*
Y1
-1
-2
-1
-2
I/O port 11 output data
(3)
I/O port 12 output data
(4)
I/O port 13 output data
(5)
I/O port 14 output data
(6)
I/O port 15 output data
-1
-0
-1
-0
-1
-0
-1
-2
φL32
-3
-2
-3
-2
-3
*
-0
-1
-0
-1
(B)
-1
-0
-1
-2
-0
-1
-2
-1
Y8
-0
-1
-2
-3
-3
-1
-2
-1
-2
I/O port 3 input data
-0
φK33
-3
-1
-0
φK34
-3
-3
-1
-2
-3
I/O port 5 input data
-0
φK35
I/O port 6 output data
-2
I/O port 4 input data
-1
-2
-3
I/O port 6 input data
φK36
-1
-2
-3
-0
φK37
I/O port 8 output data
-2
φL39
φK39
I/O port 10 input data
-0
φL3A
φL3B
*
-2
-1
-2
-0
-1
-2
-0
-1
-2
-0
φK3B
-3
-3
φL3E
φK3E
φL3F
(F)
-2
-3
φK3F
I/O port 16 output data
-2
-3
-1
-2
-3
I/O port 13 input data
-0
φK3D
*
-1
-1
I/O port 12 input data
-0
φK3C
I/O port 16 control
-0
-3
φK3A
-3
I/O port 5 control
φL3D
IN
-3
I/O port 4 control
φL3C
-3
-1
I/Ocontrol3
-0
I/O port 15 control
-3
-0
-1
-2
I/O port 9 input
data
-0
-1
-2
-3
-2
-2
φK38
-3
-2
-1
I/O port 8 input data
φL38
-3
I/O port 14 control
-0
-2
-3
I/O port 13 control
(D)
-1
*
I/O port 12 control
(C)
(E)
-2
I/O port 11 control
-0
φK32
φL36
I/O port 10 control
(A)
Y4
*
I/O port 9 control
(9)
-3
I/O port 5 output data
-0
φL35
-2
I/O port 4 output data
-0
φL34
-1
I/O port 3 output data
-0
φL33
φL37
-1
Y2
φK31
-0
(7)
*
Y1
φK30
-0
(8)
IN3 instruction
Y8
φL31
-3
(2)
-0
Y4
-3
I/O port 10 output data
-0
Y2
φL30
I/O port 9 output data
-0
(1)
OUT3 instruction
Y1
-1
-2
-3
I/O port 14 input data
-0
-1
0
0
I/O port 15
input data
-0
-1
-2
-3
I/O port 16 input data
Y1
Y2
(UnφK25 known)
IN2
Y4
Y8
(Un(Unknown) known)
I/O control data
( Setting of input and output)
I/O port output data
●CMOS type I/O port
0 ： Setting of I/O port input
1： Setting of I/O port output
0 ： Output pin “L” level
1 ： Output pin “H” level
I/O port input data
0 ： Input pin “L” level
1 ： Input pin “H” level
●Nch open drain type I/O port
0 ： Output pin “L” level
1 ： Output pin High impedance
Setting of DO1 / DO2 output status
DO1 control
Y1
Y2
Y4
M0
φL24
Y8
M1
M1
M0
Output status
0
0
Phase comparator output
0
1
1
0
1
1
“L” level output
OT output
“H” level output
High impedance
DO２ control１
Y1
φL25
Y2
Y4
Y8
M0
M1
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I/O port input/output settings are determined at the I/O control data ports. Set the I/O control data port bit corresponding
to each port to “0” to program as an input port or set to “1” to program as an output port.
Determine the output state of an output port by setting the I/O port output data port. Set the output data bit corresponding
to each port to “1” to output the “H” level or set to “0” to output the “L” level.
I/O control data and I/O port output data are programmed and controlled at the OUT1 instruction data port-3, the OUT3
instruction.
When the IN3 instruction is executed, the pin state is read into the data memory. Note that execution of the IN3
instruction has no influence on the contents of the output latch.
OT1/OT2 output is programmed by the contents of the DO control port. (→ Refer to the section on Phase comparator.)
Note: There is no I/O control port for N-ch open-drain ports (I/O ports 6, 8 and 9-0). To set these ports as input
ports, set high impedance by specifying output data to “1”.
Note: I/O port 1, I/O port 2, ... correspond to pin names P1-0 to P1-3, P2-0 to P2-3, ....
Note: The contents of output ports become unfixed after a system reset. It is recommended that the output
data be determined before output setting.
Note: Data select port increments by 1 automatically when φL10 to φL15, φK10 and φK11 on the I/O map are
accessed.
Note: The state of a pin that has been set to output is read when the IN3 instruction is executed.
Note: All the input circuits have the AND structure, which turns the AND gate on only when data reading (IN
instruction) is executed. There is little influence on consumption current; even when the input is in the
floating condition or has midpoint potential. This enables pull-up at a potential lower than the VDD
potential and output at three levels. Pay close attention to setting to the break pin, serial interface or
interrupt input, because the consumption current will increase rapidly when the input has midpoint
potential.
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3. Break Setting and Pull-up/Pull-down Setting
16 pins of I/O ports 3, 4, 6 and 8 can be set as backup release pins (break pins). If there is a change in the input state of an
I/O port that has been set to input, the break pin releases execution of the WAIT or CKSTP instruction and restarts the CPU
operation. When the break bit of the MUTE port is “1”, the MUTE bit is compulsorily set to “1” when there is a change in
the input state. (→ Refer to the section on MUTE output.)
Each pin of I/O port 3 can be programmed to a pull-down or pull-up state with 50 kΩ (standard) at the pull-up/pull-down
control port. Adjust settings at the pull-up/pull-down control ports that corresponds to the pins of I/O port 3.
φL/K1A
Y1
Y2
SEL1
SEL2
Y4
Y8
SEL4
SEL8
(Data port 4)４）
φL14
φL14
（ データポート
Y1
Y2
Y4
Y8
Data select
データセレクト
I/Oポートブレーク許可
I/O port break enabled
(9)
BP3
BP4
BP6
Break
enabled (for each I/O port)
ブレーク許可(I/Oポート単位)
BP8
0: Prohibition
0： 禁止
1: Enabled
1： 許可
I/Oポート3　プルアップ
I/O port 3 pull-up
(A)
PU0
PU1
PU2
PU3
I/O port 3 pull-down
I/Oポート3　プルダウン
(B)
PD0
PD1
PD2
PD3
Pull-up/pull-down
setting
プルアップ/ダウン設定
PU
PD
Pin state
端子状態
0
0
Pull-up/pull-down off
プルアップ/ダウンオフ
0
1
プルダウン
Pull-down
1
*
プルアップ
Pull-up
Note: BP3, BP4, BP6 and BP8 correspond to I/O ports 3, 4, 6 and 8 respectively. PU0/PD0, PU1/PD1,
PU2/PD2 and PU3/PD3 correspond to pins P3-0, P3-1, P3-2 and P3-3 respectively.
Note: Break is enabled only when the I/O port is programmed as an input port. The input pin that has been set
as a break pin must not be used at the intermediate level.
Note: Execution of the wait or clock stop instruction requires reading of the input of the I/O port to be released.
Note: When the serial interface function, the pulse counter function or the interruption input is used and break
is enabled, the wait or clock stop instruction is released due to change in the input of the pin. This
requires input setting at the I/O control port and reading of input of the I/O port before the instruction is
executed.
Note: I/O port 3 can be set to a pull-up or pull-down state when the serial interface function or the pulse
counter function is used.
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Pull-up and pull-down settings can be used to configure the key matrix. The key matrix is configured with usual I/O port
output as the output of the key matrix and the I/O port 3 that has been set to pull-down or pull-up as the key input. Setting
the key input to break enables restarting depending on the presence or absence of this key input when the CDSTP or WAIT
instruction is executed.
An example configuration of the key input matrix circuit is shown below.
～
VDD
P3-3
Pull-up
プルアップ
40
P3-2
プルアップ
Pull-up
P3-2
39
P3-1
P3-1
38
P3-0
P3-0
37
P16-3
36
P16-2
P16-2 35
P16-1
P16-1 34
P16-0
P16-0 33
I/O port 3
I/Oポート3の
data loading
データ取り込み
P3-3
P16-3
When
P16-3
and
P3-1 keys are pressed
P6-3とP3-1のキーが押された場合
P16-3
と P3-1
のキーが押された場合
プルアップ
Pull-up
ハイインピーダンス
High
impedance
～
Example
of key input matrix circuit
キー入力マトリクス回路構成例
Note: After the CKSTP instruction is released by key input, there is a standby time of 100 ms. Pay close
attention to this time lag.
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MUTE Output
This is the 1-bit CMOS output port for muting control and also used as P9-1 of the I/O port.
The MUTE output can be reversed by the output logic setting or changes in the I/O port.
1. MUTE Port
Y1
φL/K28
MUTE
Y2
POL
Y4
Y8
Break
MUTE
ENA
/0
MUTE output enabled
MUTE出力許可
0:
(I/O port setting:
0：Prohibition
禁止(I/Oポート設定
： P9-1)P9-1)
1:
(MUTE output)
1：Enabled
許可(ミュート出力)
Control by changes in the input state of the break pin
Break端子の入力状態の変化による制御
0:
The MUTE output does not change when the input state of。the break pin
0： Breakの入力状態が変化してもMUTE出力は変化しない
has changed.
1： Breakの入力状態の変化によりMUTEビットは"1"にセットされる。
1: The MUTE bit is set to “1” when the input state of the break pin has
changed.
MUTE
output polarity setting
MUTE出力の極性の設定
0:0：Positive
logic – The MUTE bit is outputted as is.。
正論理・・・MUTEビットがそのまま出力される
1:1：Negative
logic – The Mute bit is outputted in a reversed
state.
負論理・・・MUTEビットが反転して出力される
。
MUTE output setting
MUTE出力の設定
0: MUTE output becomes the “L” level in the positive logic and becomes the
0： MUTE出力は
、 正論理のとき"L"レベル
、 負論理のとき"H"レベルとなる。
“H” level in the
negative logic.
正論理のとき"H"レベル
、 負論理のとき"L"レベルとなる
1:1： MUTE出力は
MUTE output、becomes
the “H” level in the
positive logic and becomes the 。
“L” level in the negative logic.
The MUTE output is usually used for muting control.
The MUTE output is also used as the I/O port function pin (P9-1). The I/O port and MUTE output pin are switched by
the MUTE ENA bit. After a reset, this bit is set to “1” and becomes the MUTE output.
Data set to the MUTE bit is outputted to the MUTE output pin using positive or negative logic. By enabling the I/O port
break function (refer to the section on the input and output ports) and setting the break bit to “1”, the MUTE bit can be set
to “1” each time the input of the I/O port is changed. This function promptly activates the muting state and prevents noise
from being generated in the linear circuit when the band is switched or the radio is turned off using the I/O port input.
POL bit sets up the logic of MUTE output. Set it up according to specifications.
This port is accessed by the OUT2/IN2 instruction with [CN = 8H] specified in the operand.
Note: During a system reset, the “L” level is outputted as the MUTE output. After the reset is released, the “H”
level is outputted. During execution of the clock stop instruction, the output becomes the “L” level. After
the instruction is released, the previous state is outputted.
Note: When the MUTE is controlled by the break function, the break pin sets the MUTE bit to “1”. The state of
the MUTE bit can be checked at the MUTE bit (φK28). The state of the MUTE pin can be checked at the
P9-1, I/O port 9 input data port (φK38) .
Note: When the MUTE bit is set to “1”, the electronic volume can be set to −∞dB. (→ Refer to the section on
Electronic volume.)
2. Circuit Composition of MUTE Output
～
MUTEビット
MUTE bit
56
S
MUTE/P9-1
POL bit
POLビット
CKSTP命令
CKSTP
instruction
Breakビット
Break bit
Break端子の入力変化の信号
Break pin input change signal
Reset signal
リセット信号
～
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Serial Interface
This is the 2-channel, 1-system serial interface, which has three functions; a three-wire serial interface, two-wire serial
interface and full-duplex UART functions.
The serial interface communicates with the extended LSI and microcomputer using CMOS serial interface pins
SCK1/TX1 (P3-0), SDIO1 (P3-1) and SI1 (P3-2) or N-ch open-drain pins SCK2/TX2 (P8-2), SDIO2 (P8-3) and SI2 (P8-1)
(that can accept voltage up to 5.5V). When the serial interface operation is finished, an interruption is issued.
The serial interface consists of the 4-bit input/output serial counter, the 12-bit serial output latch, the 12-bit serial input
latch and the control circuit that controls them.
The basic operations of the serial interface are as follows. For the serial output, the serial data output bit data is outputted
as specified by the serial output counter, and the serial counter is moved up or down by the serial clock so that the data is
outputted to the serial output pin in the specified order. For the serial input, serial input data is sequentially taken to the
serial latch specified by the serial input counter as in the case of the serial input.
1. Control Port and Data Port for Serial Interface
The serial interface executes control and data transmission and receiving using the control port and data port. These ports
are assigned in I/O map data port 2 and accessed by the OUT1/IN1 instruction.
Serial interface control 1
シリアルインタフェースコントロール
１
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(7)
M0
M1
PSEL
Selection of serial interface pin
シリアルインタフェース端子の選択
SIO
PSEL
SIO
シリアルインタフェース端子
Serial interface pin
*
0
Each pin for I/O port operation。
各端子はI/Oポート動作します
0
Mode setting
モード設定
1
1
I/O port 3 (CMOS)
I/Oポート3(CMOS構造)
I/Oポート8(Nchオープンドレイン構造)
I/O port 8 (N-ch open-drain)
Serial
interface mode setting
シリアルインタフェースモード設定
68
M1
M0
シリアルインタフェースモード
Serial interface mode
0
0
0
1
2線式インタフェース
2-wired interface
1
0
3線式インタフェース
3-wired interface
1
1
UART
Operation
stop
動作停止
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Serial interface control 2
シリアルインタフェースコントロール
２
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(8)
CK0
CK1
OSC0
OSC1
Clock setting
クロック設定
Serial
clock (transmission rate) frequency setting
シリアルクロック(転送レート)周波数設定
OSC1
0
OSC0
Oscillator
発振器の設定
0
Low-speed
低速発振器
oscillator
(75kHz)
(75kHz)
setting
High-speed
0
1
高速発振器
oscillator
(300kHz)
High-speed
1
0
高速発振器
oscillator
(450kHz)
(450kHz)
High-speed
1
1
高速発振器
oscillator
(600kHz)
(600kHz)
2/3-wired
interface clock
2/3線式設定時
frequency (fSCK)
クロック周波数(fSCK)
CK1
CK0
UART transmission rate (fSCK)
UART送受信転送レート(fSCK)
0
0
fosc/2
37.5kHz
0
1
fosc/4
18.75kHz
fosc/8bps
9375bps
9600bpsモード
mode
1
0
fosc/8
9.375kHz
fosc/32bps
2344bps
2400bpsモード
mode
1
1
fosc/16
4.6875kHz
fosc/64bps
1172bps
1200bpsモード
mode
0
0
fosc/2
150kHz
fosc/16bps
mode
18750bps 19200bpsモード
0
1
fosc/4
75kHz
fosc/32bps
9375bps
mode
9600bpsモード
1
0
fosc/8
37.5kHz
fosc/128bps
2344bps
2400bpsモード
mode
1
1
fosc/16
18.75kHz
fosc/256bps
1172bps
1200bpsモード
mode
0
0
fosc/2
225kHz
fosc/24bps
18750bps 19200bpsモード
mode
0
1
fosc/4
112.5kHz
fosc/48bps
9375bps
9600bpsモード
mode
1
0
fosc/8
56.25kHz
fosc/192bps
2344bps
mode
2400bpsモード
1
1
fosc/16
28.125kHz
fosc/384bps
1172bps
1200bpsモード
mode
0
0
fosc/2
300kHz
fosc/32bps
mode
18750bps 19200bpsモード
0
1
fosc/4
150kHz
fosc/64bps
9375bps
9600bpsモード
mode
1
0
fosc/8
75kHz
fosc/256bps
2344bps
mode
2400bpsモード
1
1
fosc/16
37.5kHz
fosc/512bps
1172bps
1200bpsモード
mode
-
Serial interface control 3
シリアルインタフェースコントロール ３
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(9)
MASTER
POL
NchS
SIS
0: Select
SDIO input
pin
０：SDIO
入力端子を選択
Selection
of serial
input of SDIO
SDIO
端子と
SI 端子のシリアル入力の選択
1: Select
SI
input
pin
and SI pins
１：SI 入力端子を選択
0: Select０：CMOS
CMOS output
form
出力形式を選択
1: Select１：Nch
N-ch open-drain
output form
オープンドレイン出力形式を選択
SelectionI/O
of output
form of serial
シリアル
ポート端子の出力形式の選択
I/O port pin
Selection
of serial clock logic for serial data
シリアルータのシリアルクロックの論理選択
0: ０：正論理出力
Positive logic output
(“L” level outputs
clock)
(”Ｌ”レベルから
SCKSCK
クロックが出力する
。)
1: １：負論理出力
Negative logic output
(“H” level outputs
clock)
(”H”レベルから
SCK SCK
クロックが出力する
。)
０：外部クロック入力
0: External
clock input (slave) (スレーブ)
Selection
of external or internal
SCK
クロックの外部／内部の選択
１：内部クロック出力
(マスタ)
1: Internal
clock output (master)
SCK
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Serial interface control 4
シリアルインタフェースコントロール４
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(A)
STPS
SWENA
MSB
SOS
０： SDIO端子入力設定
0: Pin SDIO
input setting
Output
setting for serial
SDIO端子シリアル出力の出力設定
１： SDIO端子出力設定
1: Pin SDIO
output setting
output of pin SDIO
0: Input/output
serial data from the least significant bit
０： シリアルデータを最下位から入出力
シリアルデータのビット順序の選択
Selection of order of serial
1:
Input/output
serial
data from the most significant bit
１：
シリアルデータを最上位から入出力
data bits
シリアルウエイト許可設定
Serial
wait enable setting
0: Prohibition
０： 無効
1: Enabled
１： 有効
Note:
When the serial wait is set to be enabled,
the SCK output is compulsorily outputted
注： シリアルウエイトを許可に設定すると
、 シリアルデータSOF出力時にSCK出力を
at　強制的に"L"レベルを出力し
the “L” level and becomes the clock
wait state when the serial data
、 クロックウエイトとなります
。 SOF is outputted.
(This is effective only in the 2-wired serial mode.)
（２ 線式シリアルモードのみ有効です。）
０： 入力クロックカウンタを選択
0: Select the input clock counter
Selection
of serial clock counter
シリアルクロックカウンタ停止条件の選択
1: Select １：
the出力クロックカウンタを選択
output clock counter
stop condition
Serial interface control 7
シリアルインタフェースコントロール
７
Ｙ１ Ｙ２ Ｙ４ Ｙ８
φL11(D)
TSTA1 TSTA2
STP
F/F
Reset
内部フラグのリセット・・・”
１ ”をセットするたびに内部フラグをリセットする
。
internal flag each time “1” is set
Internal flag reset ･･･Resets the
シリアル動作停止
１serial
”をセットするとシリアル動作が停止する
。
Stops
operation by setting “1”
Serial
operation stop ･･･・・・”
２ 線式設定時のリスタートの実行・・・”
”をセットすると動作が再開する
。
Execute
restart in 2-wired mode ･･･Restarts１
operation
by setting “1”
マスタ時のシリアル動作の開始・・・”
１ ”をセットすると動作が開始する
。
operation by setting “1”
Start
serial operation in master mode ･･･Starts
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φL11(4)
φL11(5)
φL11(6)
Ｙ１
Ｙ２
Ｙ４
Ｙ８
Ｙ１
Ｙ２
Ｙ４
Ｙ８
Ｙ１
Ｙ２
Ｙ４
Ｙ８
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
SO8
SO9
SOE
SOF
Serial output data
シリアル出力データ
Data that has been set
the output data
セットしたデータが
、outputs
出力カウンタ番号に対応した出力
corresponding to the output counter number to the serial
データをシリアル出力端子に出力する
。
output pin.
φK11(4)
φK11(5)
シリアル出力”
0:０：Serial
output “L” Ｌ ”
シリアル出力”
1:１：Serial
output “L” Ｈ ”
φK11(6)
Ｙ１
Ｙ２
Ｙ４
Ｙ８
Ｙ１
Ｙ２
Ｙ４
Ｙ８
Ｙ１
Ｙ２
Ｙ４
Ｙ８
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
SI8
SI9
SIE
SIF
０：input
シリアル入力”
Ｌ”
The
state of the serial input pin is inputted to the input
data
入力カウンタ番号に対応した入力データに
、 シフトクロック
0: Serial
“L”
corresponding to the input counter number at the edge of
１：input
シリアル入力”
Ｈ”
1: Serial
“H”
のエッジでシリアル入力端子の状態が入力される。
the shift clock.
Serial input data
シリアル入力データ
Serial interface control 5
シリアルインタフェースコントロール５
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(B)
STA0
STA1
STA2
STA3
Serial counter start data
シリアルカウンタの開始データ
The specified counter number、is
set to the serial
シリアル動作が開始されると
設定したカウンタ番号がシリアル
counter when the serial operation starts.
カウンタにセットされる。
Serial interface control 6
シリアルインタフェースコントロール６
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φL11(C)
STP0
STP1
STP2
シリアルカウンタの開始・停止の設定
。
Serial
counter start/stop setting
STP3
Serial counter stop data
シリアルカウンタの停止データ
The serial counter is stopped at the specified counter number.。
設定したカウンタ番号でシリアルカウンタが停止する
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Serial interface monitor 1
シリアルインタフェースモニタ１
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φK11(7)
０：２ 線式停止状態
0: 2-wired
stop state
２ 線式設定時
：２ 線式動作状態の検出
2-wired mode:
Detection of
１：２ 線式動作状態
1: 2-wired
operating
BUSY1 SOERR RX F/F BUSY2
2-wired operation state
state
UART setting: Detection of
0: Receiving
operation
０： 受信動作停止状態
receiving ：(RX)
operation
UART設定時
受信(RX)動作状態の検出
stop１：
state
受信動作状態
state
1: Receiving operation
operating state
０： 受信動作なし
0: No receiving operation
シリアル受信実行フラグ
Serial receiving execution flag
１： 受信動作実行
1: Execution of receiving operation
シリアル動作モニタ
２ 2
Serial
operation monitor
0:
Serial
data output abnormality
シリアルデータ出力異常検出フラグ
detection flag
1:
０：
出力データ正常
Output
data normal
１：
出力データ異常
Output
data abnormal
０： シリアル停止状態
0: Serial stop state
１： シリアル動作状態
1: Serial operating state
Serial
operation monitor
シリアル動作モニタ
１ 1
Serial interface monitor 2
シリアルインタフェースモニタ２
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φK11(8)
OCT0
OCT1
OCT2
OCT3
Serial output counter monitor
シリアル出力カウンタモニタ
The current serial output data number is read.
現在のシリアル出力データ番号が読み込まれる
。
Serial interface monitor 3
シリアルインタフェースモニタ
３
Ｙ1
Ｙ2
Ｙ4
Ｙ8
φK11(9)
ICT0
ICT1
ICT2
Serial
counter operation monitor
シリアルカウンタの動作モニタ
ICT3
シリアル入力カウンタモニタ
Serial input counter monitor
現在のシリアル入力データ番号が読み込まれる
。
The current serial input data number is read.
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1-1. Serial Interface Setting and Control Bits
(1)
Serial pin setting (PSEL and SIO bits)
I/O ports 3 or 8 can be used as serial input/output pins. I/O port 3 has a CMOS structure and I/O port 8 has an N-ch
open drain structure. Since voltage up to 5.5V can be applied to I/O port 8, it can do an interface with LSI of 5 V
system easily.
I/O port 3 is usually used for communication with LSI that drives the VDD power supply in the same power supply
system. This port can also be used as a N-ch open-drain port, and accept voltage up to the power supply of the VLCD
pin (3 V). Therefore, it can be used as an interface with LSI in power supply systems of 3 V or below.
Set this control bit to “0” when the serial interface is not used.
SIO
PSEL
Serial interface pin
Pin structure
Pin type
Maximum applicable voltage
0
*
Each pin I/O Port operation
-
-
~VLCD (3 V)
~5.5 V
1
0
I/O port3
CMOS
CMOS or
Nch open drain
1
1
I/O port8
Nch open drain
Nch open drain
Note:
(2)
Type of serial operation (M0 and M1 bits)
The serial operation can be selected from three serial interface modes; 3-wired type, 2-wired type and UART. Set
this control bit to “0” when the serial interface is not used. When a mode is selected, the pins are switched to the
function pins as listed below.
Name of pin being used
使用端子および名称
M1
M0
シリアルインタフェースモード
Serial interface mode
0
0
Operation
stop
動作停止
P3-0
P3-1
P3-2
P8-1
P8-2
P8-3
0
1
2線式インタフェース
2-wired interface
SCK1
SDIO1
P3-2
P8-1
SCK2
SDIO2
1
0
3線式インタフェース
3-wired interface
SCK1
SDIO1
SI1(P3-2)
SI2(P8-1)
SCK2
SDIO2
1
1
UART
RX1
TX1
P3-2
P8-1
RX2
TX2
Note:
(3)
These bits are reset to “0” after a system reset.
I/Oポート3選択
Select I/O port 3
I/Oポート8選択
Select I/O port 8
These bits are reset to “0” after system reset.
Selection of serial operation clock (CK0, CK1, OSC0 and OSC1 bits)
The serial operation clock sets the serial interface operating speed. When the 2- or 3-wired master mode is selected,
operation speed can be selected from four types, fosc/2, fosc/4, fosc/8 and fosc/16. When UART is selected, operation
speed can be selected from three types, 9600/2400/1200 bps. When a high-speed oscillator is used, the operation
speed of the 2- or 3-wired type can be accelerable to 300 kHz, which enables the use of the UART transmission rate,
19200 bps. Refer to the following table and select the operation clock.
When the 2- or 3-wired slave mode is selected, these bits revert to “don't care” state, which enables serial clock
operation at an operation speed of up to 200 kHz.
Note:
The duty of the 2- or 3-wired mode is always 50%.
Note:
When the high-speed oscillator is prohibited, the OSC0 and OSC1 bits revert to “don't care”
state.
Note:
Set all of these bits to “0” when the 2- or 3-wired slave mode is selected.
Note:
These bits are reset to “0” after a system reset.
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Serial
clock (transmission rate) frequency setting
シリアルクロック(転送レート)周波数設定
OSC1
Oscillator
OSC0
発振器の設定
setting
0
低速発振器
oscillator
(75kHz)
(75kHz)
Low-speed
0
0
1
High-speed
oscillator
高速発振器
(300kHz)
High-speed
1
0
高速発振器
oscillator
(450kHz)
(450kHz)
High-speed
1
1
高速発振器
oscillator
(600kHz)
(600kHz)
2/3線式設定時
2- or 3-wired mode
2- or 2/3線式設定時
3-wired interface clock
frequency (fSCK)
クロック周波数(fSCK)
CK1
CK0
0
0
fosc/2
37.5kHz
0
1
fosc/4
18.75kHz
fosc/8bps
9375bps
mode
9600bpsモード
1
0
fosc/8
9.375kHz
fosc/32bps
2344bps
2400bpsモード
mode
1
1
fosc/16
4.6875kHz
fosc/64bps
1172bps
1200bpsモード
mode
0
0
fosc/2
150kHz
fosc/16bps
mode
18750bps 19200bpsモード
0
1
fosc/4
75kHz
fosc/32bps
9375bps
9600bpsモード
mode
1
0
fosc/8
37.5kHz
fosc/128bps
2344bps
2400bpsモード
mode
1
1
fosc/16
18.75kHz
fosc/256bps
1172bps
1200bpsモード
mode
0
0
fosc/2
225kHz
fosc/24bps
mode
18750bps 19200bpsモード
0
1
fosc/4
112.5kHz
fosc/48bps
9375bps
mode
9600bpsモード
1
0
fosc/8
56.25kHz
fosc/192bps
2344bps
2400bpsモード
mode
1
1
fosc/16
28.125kHz
fosc/384bps
1172bps
mode
1200bpsモード
0
0
fosc/2
300kHz
fosc/32bps
18750bps 19200bpsモード
mode
0
1
fosc/4
150kHz
fosc/64bps
9375bps
9600bpsモード
mode
1
0
fosc/8
75kHz
fosc/256bps
2344bps
mode
2400bpsモード
1
1
fosc/16
37.5kHz
fosc/512bps
1172bps
mode
1200bpsモード
fSCK
UART transmission rate (fSCK)
UART送受信転送レート(fSCK)
-
UART設定時
UART mode
Serial
clock (SCK)
シリアルクロック(SCK)
tSCK
UART入出力(TX/RX)
UART
input/output (TX/RX)
シリアル入出力(SDIO)
Serial
input/output (SDIO)
(4)
Serial operation condition setting
MASTER bit (Selection of external/internal SCK clock)
Set the master or slave mode. Select the internal clock for the serial clock (SCK) to set the serial operation to
master mode, and select the external clock to set the serial operation to slave mode.
If the master setting is selected, the serial operation will start and the serial clock will be outputted when start
setting is made by the serial start bits (TSTA1 and TSTA2 bits), and the operation will stop under the serial counter
stop condition. The serial clock selected by the clock selection bits (CK0, CK1 bit) will be outputted.
If the slave setting is selected, the serial operation will start automatically when the external clock is inputted. For
the 2- or 3-wired type, frequencies no higher than 200 kHz (fSCK) can be inputted as the external clock.
0: External clock input (slave)
Selection of external or internal SCK
clock (MASTER bit)
1: Internal clock output (master)
Note:
Select the slave setting when the UART is selected.
Note:
This bit is reset to “0” after a system reset.
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POL bit (Selection of serial clock logic for serial data)
Select the logic for shift clock input/output of the serial clock.
When "1" is set to the bit of POL and a master setup is selected, serial operation stops on the "H" level in the state
of a stop, if operation starts, the serial clock outputs and it stops on "H" level. When the POL bit is set to “0”, the
logic will be reversed, that is, the operation will start from the “L” level.
Together with the output logic, this bit controls the serial counter operation edge by the serial clock input/output
and the serial input take-in edge. The timing operation by the POL bit is as shown below.
0: Positive logic output (SCK clock is outputted from the “L” level)
Selection of serial clock logic for serial data
(POL bit)
1: Negative logic (SCK clock is outputted from the “H” level)
(A) 2-wired master and slave and 3-wired slave modes (POL=”1”)
（ A）２ 線式マスタ・スレーブ、３ 線式スレーブ設定時（ POL="1"）
(A) 2-wired master and slave and 3-wired slave modes (POL=”1”)
（ B）２ 線式マスタ・スレーブ、３ 線式スレーブ設定時（ POL="0"）
Take
in data input
データ入力の取り込み
Take in data input
データ入力の取り込み
シリアルクロック
Serial clock
シリアルクロック
Serial clock
Serial
output
シリアル出力
Serial
output
シリアル出力
Serial
output
シリアル出力
counter
カウンタ
(OTC0
3 bit)）
（ OTC0
～to
3ビット
Serial
output
シリアル出力
counter
カウンタ
(OTC0
3 bit)）
（ OTC0
～to
3ビット
Serial input
シリアル入力
シリアル入力
Serial input
Serial input
シリアル入力
counter
カウンタ
(ITC0
3 bit)）
（ ITC0
～to
3ビット
Serial input
シリアル入力
counter
カウンタ
(ITC0
3 bit)）
（ ITC0
～to
3ビット
3-wired
master mode （(POL=”1”)
（(C)
C）３
線式マスター設定時
POL="1"）
tsck/4
(D)
3-wired
master mode （(POL=”0”)
（ D）３
線式マスター設定時
POL="0"）
tsck/4
tsck/4
tsck
シリアルクロック
Serial clock
tsck/4
tsck
Serial clock
シリアルクロック
Serial
output
シリアル出力
Serial
output
シリアル出力
Serial
output
シリアル出力
counter
カウンタ
3 bit) ）
（(OTC0
OTC0～to3ビット
Serial
output
シリアル出力
counter
カウンタ
3 bit)）
（(OTC0
OTC0～to3ビット
シリアル入力
Serial input
Serial input
シリアル入力
Serial input
シリアル入力
counter
カウンタ
3 bit)）
（(ITC0
ITC0～to3ビット
Serial input
シリアル入力
counter
カウンタ
(ITC0
3 bit)）
（ ITC0
～to
3ビット
Note:
When the 3-wired master mode is selected, the serial output (serial output counter) changes in
timing shifted by tsck/4.
Note:
When the 2-wired master mode is selected, the serial clock is operated by the input of the SCK
pin clock. Therefore, the serial operation will not start if the SCK pin clock does not output
waveforms for some reason.
Note:
Set to POL = “0” when UART is selected.
Note:
This bit is reset to “0” after a system reset.
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NchS bit (Selection of output form for the serial I/O port pins)
Set the serial interface input/output circuit type. Setting this bit to “0” to select the CMOS circuit form, and setting
this bit to “1” to select the N-ch open-drain circuit.
0: Select the CMOS output form
Selection of output form for serial I/O port pins
(NchS bit)
NchS
0
1
1: Select the N-ch open-drain output form
I/O port 3
I/O port 8
I/Oポート3
I/Oポート8
CMOS type
Setting
disabled
CMOS形式
設定禁止
N-ch open-drain type
Nchオープンドレイン形式
Note:
Select the N-ch open-drain setting when the 2-wired mode is selected.
Note:
This bit is also effective when the UART is selected.
Note:
This bit is reset to “0” after a system reset.
SIS bit (Selection of SDIO pin or SI pin for serial input)
Select a serial input pin. Set this bit to “0” to select the SDIO pin for serial input. Set this bit to “1” to select the SI
pin for serial input.
The I/O port function is enabled for the SI pin. Therefore, when the SI input pin is used for serial input, it is
necessary to set the I/O port corresponding to this pin as an input port. When the SDIO pin is used for serial input, the
SI pin can be used as an I/O port.
Selection of SDIO or SI pins for serial input
(SIS bit)
0: Select the SDIO input pin
1: Select the SI input pin
Note:
When the SI pin is selected, set the I/O port corresponding to this pin as an input port.
Note:
When the SDIO input is selected, the SI pin can be used as a normal I/O port.
Note:
Select the SDIO input when UART is selected.
Note:
This bit is reset to “0” after a system reset.
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STPS bit (Selection of the serial clock counter stop condition)
The serial operation stops when it becomes the stop position of a serial counter. There are two types of serial
counters, the serial output counter and the serial input counter. The stop condition is switched between the output and
input counters.
Selection of serial clock counter stop condition
(STPS bit)
(A)
or 3-wired
mode (POL=”0”,
STP=”0”)
（ A2）２／３
線式設定時
（ POL="0"
、 STP="0"）
0: Select the input clock counter
1: Select the output clock counter
(B)（ B
2-）２／３
or 3-wired
mode (POL=”0”,
STP=”1”)
線式設定時
（ POL="0"
、 STP="1"）
Stop
停止
Stop
停止
Serial clock (SCK)
シリアルクロック
（ SCK)
Serial clock (SCK)
シリアルクロック
（ SCK)
シリアル出力カウンタ
Serial output counter
(OTC0
3 bit)）
（ OTC0
～to
3ビット
シリアル入力カウンタ
Serial input counter
(ITC0
3 bit)）
（ ITC0
～to
3ビット
Serial output counter
シリアル出力カウンタ
(OTC0
3 bit)）
（ OTC0
～ to
3ビット
Serial input counter
シリアル入力カウンタ
(ITC0
3 bit)）
（ ITC0
～ to
3ビット
2- or 3-wired
mode (POL=”1”,
（(C)
C）２／３
線式設定時
（ POL="1"STP=”0”)
、 STP="0"）
(D)
or 3-wired
mode (POL=”1”,
STP=”1”)
（ D2）２／３
線式設定時
（ POL="1"
、 STP="1"）
停止
Stop
停止
Stop
Serial clock（(SCK)
シリアルクロック
SCK)
Serial clock（(SCK)
シリアルクロック
SCK)
シリアル出力カウンタ
Serial output counter
(OTC0
to 3 bit)
（ OTC0
～ 3ビット
）
シリアル入力カウンタ
Serial input counter
(ITC0
to 3 bit)
（ ITC0
～ 3ビット
）
Serial output counter
シリアル出力カウンタ
(OTC0
to 3 bit)
（ OTC0
～ 3ビット
）
Serial input counter
シリアル入力カウンタ
(ITC0
to 3 bit)
（ ITC0
～ 3ビット
）
Note:
Set to STPS = “1” (Select the clock output counter) as shown in (B) when the 2-wired or UART
mode is selected.
Note:
This bit is reset to “0” after a system reset.
SWENA bit (Serial wait enable)
This control bit is effective only when the 2-wired mode is selected. usually, set this bit to “1” when the 2-wired
mode is selected.
If serial wait is enabled in the 2-wired mode, the SCK is outputted at the “L” level and becomes the clock wait
state and the serial clock is suspended when the serial output counter (OCT0~3) becomes “F” (HEX).
0: Prohibition
Serial wait enabling setting (SWENA bit)
1: Enabled (Set to “1” when the 2-wired setting is selected)
When
the 2-wired
mode is selected
(POL=”1”,
STP=”0”,
２ 線式設定時
（ POL="1"
、 STP="0"
、 SWENA="1"
） SWENA=”1”)
Serial clock (SCK)
シリアルクロック
（ SCK)
Serial output counter
シリアル出力カウンタ
(OTC0
3 bit)）
（ OTC0
～to
3ビット
SCK出力は"L"レベルが出力され、
SCK is outputted at the “L” level
一時停止します
。
and is suspended
F(HEX)
Note:
Set to SWENA = “0” when the 3-wired or UART mode is selected.
Note:
This bit is reset to “0” after system reset.
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SOS bit (Output setting for SDIO pin serial output)
This control bit switches the serial data input/output pin (SDIO pin) between data output and input. Set this bit to
“0” for serial data input or set to “1” for serial data output.
In the 3-wired mode, switching between input and output is executed when the instruction to this bit is executed.
In the 2-wired mode, switching between input and output is updated and determined under the following conditions
after this bit is specified.
0: SDIO pin input setting
Output setting for SDIO pin serial output
(SOS bit)
1: SDIO pin output setting
Update timing of SDIO pin input/output switching in the 2-wired mode
Stop condition
Falling edge of the shift clock when the communication is started
Falling edge of the serial clock after ACK input/output
SDIO
input/output switching timing in the 2-wired
mode (master）mode)
２ 線式設定時のSDIO入出力切り替えタイミング
（ マスター設定時
Serial clock
シリアルクロック
(SCK)
（ SCK)
Serial
input/output
シリアル入出力
（(SDIO)
SDIO)
ACK
Execution
of
命令の実行
instruction
ACK
TSTA2=”1”
execution
TSTA2="1"実行
TSTA1="1"実行
TSTA1=”1”
execution
SOSビット設定
SOS bit setting
STP=”1”
execution
STP="1"実行
SOSビット設定
SOS
bit setting
SDIO
SDIO入出力更新タイミング
input/output update timing
SOSビット設定
SOS
bit setting
SDIO入出力更新タイミング
SDIO
input/output update timing
SDIOSDIO入出力更新タイミング
input/output update timing
SDIO
２ 線式設定時のSDIO入出力切り替えタイミング
input/output switching timing in the 2-wired
（ スレーブ設定時
mode (slave mode)
）
Serial clock
シリアルクロック
(SCK)
（ SCK)
Serial input/output
シリアル入出力
(SDIO)
（ SDIO)
Execution
of
命令の実行
instruction
ACK
SOSビット設定
SOS bit setting
ACK
SOSビット設定
SOS
bit setting
SDIO入出力更新タイミング
SDIO
input/output update timing
SOSビット設定
SOS
bit setting
SDIO入出力更新タイミング
SDIO
input/output update timing
SDIO SDIO入出力更新タイミング
input/output update timing
SDIO
input/output switching timing in the 3-wired mode
３ 線式設定時のSDIO入出力切り替えタイミング
シリアルクロック
Serial clock
（(SCK)
SCK)
シリアル入出力
Serial
input/output
（ SDIO)
(SDIO)
Execution of
命令の実行
instruction
Input
入力
0
SOS="1"
Output
出力
1
SOS="0"
Input
入力
0
SOS="1"
Note:
If the SOS bit is set in the 3-wired mode, the input/output of the SDIO pin will be updated when
the instruction is executed.
Note:
Always set the SOS bit to “1” when UART is selected.
Note:
This bit is reset to “0” after a system reset.
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MSB bit (Selection of the order of serial data bits)
This control bit controls the arrangement of serial data input/output data. Select whether data input/output started
from the most or the least significant bit respectively.
For the serial interface, serial data specified by the serial counter is inputted and outputted. The MSB bit controls
the serial counter to count up or down. When the MSB bit is set to “0”, the serial counter counts up. When the MSB
bit is set to “1”, the serial counter counts down.
0: Input/output serial data beginning with the least significant bit
Selection of the order of serial data bits
(MSB bit)
1: Input/output serial data beginning with the most significant bit
Serial counter and serial input/output timing (when
MSB=、“0”
and POL= “0”)）
シリアルカウンタとシリアル入出力タイミング
（ MSB="0"
POL="0"設定時
Serial clock
シリアルクロック
(SCK)
（SCK)
シリアル出力
Serial output
カウンタ
counter
(OTC0
OTC3)
（ OTC0
～to
OTC3)
Ｄ
Ｅ
Ｆ
０
１
２
３
４
５
６
７
８
９
Ａ
Serial input
シリアル入力
counter
カウンタ
(ITC0
to ITC3)
（ ITC0～ ITC3)
Ｄ
Ｅ
Ｆ
SOE
シリアル入出力
Serial input/output
（ SDIO)
(SDIO)
０
SOF
１
SO0
２
SO1
３
SO2
４
SO3
５
SO4
６
SO5
７
SO6
８
SO7
９
SO8
Ａ
SO9
(注)上記はHEX表記
(Note) Shown
in HEX notation。
Serial counter and serial input/output timing (when
MSB=、“1”
and POL= “1”)）
シリアルカウンタとシリアル入出力タイミング
（ MSB="1"
POL="1"設定時
シリアルクロック
Serial clock
(SCK)
（ SCK)
シリアル出力
Serial output
counter
カウンタ
(OTC0
OTC3)
（ OTC0
～to
OTC3)
Ａ
９
８
７
６
５
４
３
２
１
０
Ｆ
Ｅ
Ｄ
Serial input
シリアル入力
counter
カウンタ
(ITC0
to ITC3)
（ ITC0～ ITC3)
シリアル入出力
Serial input/output
(SDIO)
（ SDIO)
Ａ
９
８
SO9
７
SO8
６
SO7
５
SO6
４
SO5
３
SO4
２
SO3
１
SO2
０
SO1
Ｆ
SO0
Ｅ
SOF
Ｄ
SOE
(Note) Shown (注)上記はHEX表記
in HEX notation 。
Note:
Serial data corresponding to the serial output counter is outputted to the serial output pin. The
state of the serial input pin corresponding to the serial input counter is stored in the serial input
data at the edge.
Note:
Input and output serial counters have up and down edges reverse to each other.
Note:
If any serial input/output data not present in the serial counter is designated, the output will be
“L” and the input will be “don't care”.
Note:
This bit is reset to “0” after a system reset.
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Serial counter, Serial data
(STA0 to 3, STP0 to 3, OCT0 to 3 and ICT0 to 3 bits, SO0 to SO9/SOE/SOF, SI0~SI9/SIE/SIF)
The serial counter consists of the serial input counter (ICT0 to 3) that counts the serial input clock and the serial
output counter (OCT0 to 3) that counts the serial output clock. When stop is executed (STP = “1”), these serial
counters are preset to the stop data (STP0 to 3). When start is executed (TSTA1 = “1”, TSTA2 = “1”) or the external
serial clock is started, these serial counters are preset to serial counter start data (STA0 to 3) and counted by the serial
clock. When the serial counter coincides with the serial stop data (STP0 to 3), the serial counter is stopped and an
interruption is issued.
The operating state can be checked on the serial counter monitor (ICT0 to 3, OCT0 to 3).
Serial counter start data (STA0 to 3 bits)
→ When the serial operation is started, the start data is set to the serial counter.
Serial counter stop data (STP0 to 3 bits)
→ When a stop is executed (STP = “1”), the stop data is set to the serial counter. After the serial
counter operation, the serial operation is stopped in the stop data position, and an interruption issued.
Operation monitor for serial output counter
(OCT0 to 3 bits)
→ The operating state of the serial output counter can be detected.
Operation monitor for serial input counter (ICT0 to 3 bits)
→ The operating state of the serial input counter can be detected.
Serial data consists of 12 bits each of serial output data (SO0 to SO9/SOE/SOF) and serial input data (SI0 to
SI9/SIE/SIF). For serial output data, the serial data corresponding to the serial output counter number is outputted to
the serial output pin. For serial input data, the state of the serial data input pin is read at the edge of the serial clock
corresponding to the serial input counter number.
When the 2-wire mode is selected, the SOE/SOF bits in the serial output data are automatically set to “1” when the
serial operation is started or when stop is executed (STP = “1”) with the master setting. usually, the bits of SO0/SI1 to
SO7/SI7 are used for serial input/output data. The SOE bit is used as the output bit of the serial stop state,while the
SOF/SIF bits are used as input/output data of ACK.
When UART is selected, the bits of SO0/SI1 to SO7/SI7 are used for UART input/output data, while the SO8/SI8
bits are used as parity bits. The SO9 bit is used for the output of the stop output data.
When the 3-wire mode is selected, up to 14 bits of serial data can be inputted and outputted. Set the serial data start
and stop data according to the number of bits, and specify this number.
Example of serial operation timing（ MSB="0"
when the 、3-wire
mode
is selected (when）MSB= “0”, POL= “0” and STPS= “1”)
３ 線式設定時のシリアル動作タイミング例
POL="0"
、 STPS="1"設定時
STP0～ 3="0"
STA0～ 3="7"
シリアルカウンタが一致すると停止する
Stop when the serial counters match. 。
Serial clock
シリアルクロック
(SCK)
（ SCK)
シリアル出力
Serial output
counter
カウンタ
toOTC3)
OTC3)
（(OTC0
OTC0～
０
Serial input
シリアル入力
counter
(ITC0カウンタ
to ITC3)
（ ITC0～ ITC3)
０
Serial input/output
シリアル入出力
(SDIO)
SO0
７
７
６
６
SO7
５
１
５
SO6
１
SO1
SO1
０
０
７
７
SO0
６
６
SO7
１
５
SO6
１
SO1
０
０
SO0
（ SDIO)
Execution of
命令の実行
TSTA1= “1” execution
TSTA1="1"実行
TSTA1=
“1” execution
TSTA1="1"実行
instruction STP="1"実行
割り込み発行
Issue
of interruption
STP= “1” execution
割り込み発行
Issue
of interruption
(Note) Shown
in HEX notation
(注)上記はHEX表記
。
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(5)
Start and stoppage of serial operation
TSTA1 and TATA2 bits (Start of serial operation)
The TSTA1 bit controls the start of serial operation in the master mode. When this bit is set to “1”, the serial clock
will be outputted and the serial interface operation will start.
When start is executed in the 3-wire mode, the serial counter start data (STA0 to 3) will be preset in the serial
input/output counters, and serial output data corresponding to the start data will be outputted. After that, serial data
(SO0 to SO9, SOE, SOF) will be outputted sequentially according to the serial clock (SCK).
When start is executed in the 2-wire mode, the start condition pulse will be outputted to the serial data output.
When this start condition is satisfied, the serial operation will be started. When start is executed in the UART mode,
the start pulse will be outputted from the TX pin, and then the same operation as in the 3-wire mode will be executed.
In slave mode, operation can be started by the external serial clock without the need to use this control bit.
The TSTA2 bit controls the restart of serial operation in the 2-wire master mode. When start is executed by the
TSTA1 bit, the start condition will be outputted, the 8-bit serial clock will be active and the operation will enter the
serial wait state. When the TSAT2 bit is set to “1”, the serial operation will be restarted for serial input/output.
Start of serial operation in the master mode (TSTA1 bit)
→ When this bit is set to “1” in the master mode, serial operation will start.
When in 2-wire mode, the start condition will be outputted automatically.
When in UART mode, the start pulse will be outputted.
Execution of restart in the 2-wire mode (TSTA2 bit)
→ When this bit is set to “1”, the operation will be restarted.
Note:
When these bits are set to “0”, the system will be in a “don't care” state.
Note:
Allow the wait time that corresonds to at least one cycle of the serial operation clock between
execution of stop (STP = “1”) and execution of start (TSTA = “1”).
STP bit (Stoppage of serial operation)
The STP bit controls the compulsive stoppage of serial operation, the initialization of internal state and the output
of the stop condition.
When the STP bit is set to “1” (stop is executed), the serial counter stop data (STP0 to 3) is preset to the serial
counter and initializes the internal state. When a stop is executed during serial operation in master mode, the serial
clock operation will be stopped.
When a stop is executed in the master 2-wire mode, the stop condition will be automatically outputted from the
serial data output and the serial clock in addition to the operation as mentioned above.
Stoppage and initialization of serial operation in the master mode (STP bit)
→ When this bit is set to “1”, the operation will be stopped and initialized. In the 2-wire mode, the stop
condition will be outputted automatically.
Note:
When this bit is set to “0”, the system will be in a “don't care” state.
Note:
After setting the condition, be sure to execute stoppage (STP = “1”) for internal initialization.
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(6)
Serial operation monitor
BUSY1/BUSY2 bits (Operation monitor)
The BUSY1/BUSY2 bits detect the serial operating state. The BUSY1 bit can detect the serial clock operating state,
while the BUSY2 bit can detect the operating state in the 2-wire mode or the receiving operation state in the UART
mode. When interruption is enabled, it will be issued at the falling edge of the BUSY1 bit and the program will
branch to address 0001H.
SOERR bit (2-wire serial output error flag)
The SOERR bit is used to detect arbitration in the 2-wire multi master mode. When serial data is outputted in the
master mode, the output state is compared to the internal output data. If there is any discrepancy between them, the
serial operation will be stopped automatically and the SOERR bit set to “1”. When this state is detected, the serial
clock and data respectively will be opened and the operation will continue. For normal arbitration detection, the serial
operation will be stopped by the clock supplied from another master. When the 2-wire operation is completed, FF
Reset = “1” will be set and the flag will be reset.
This detection is carried out during serial output setting, regardless of the master or slave mode. Therefore, program
processing is required if any discrepancy occurs in the output data due to noise or for any other reason. Usually,
provide a timer to detect this bit if there is no issue involving interruption or the BUSY1 signal does revert to “L”
after a certain time has elapsed. If the detected bit is “1”, set the STP bit to “1” to execute stop and initialization.
In any other modes than the 2-wire mode, this bit is in the “don’t care” state.
In線式のとき
the 2-wire、mode,
the serial
２
シリアルクロック
clock and the serial output
およびシリアル出力端子は開
pin are opened.
放されます
。
シリアルクロック
Serial clock
（ SCK)
(SCK)
Serial
input/output
シリアル入出力
(SDIO)
（ SDIO)
シリアルデータ異常
Serial
data error
SOERRビット
SOERR bit
RX F/F bit (Receiving flag)
The RX F/F bit detects the receiving of UART or the 3-wire slave. This bit is effective only in slave mode. When
the serial clock receives input or UART when in slave mode, this bit is set to “1”. After receiving is completed, refer
to the received serial data. This bit is reset to “0” by setting the FF Reset bit to “1”.
F/F Reset bit (Internal flag reset)
This bit initializes the internal flag. Each time this bit is set to “1”, the internal flag will be reset.
Serial receiving execution flag (RX F/F), the serial data output error detection flag in the 2-wire mode, and the
serial wait are reset and released.
In the 2-wire mode, the system will enter the wait state after output of the serial output data SOF bit. Usually, the
SOF/SIF bits are used as the acknowledgement of (ACK) bits. After reading the ACK bit input/output, serial
operation will be restarted by execution of the F/F Reset bit.
Internal flag reset (F/F Reset bit)
→ “The internal flag is reset each time this flag is set to “1”.
The wait state is released in the 2-wire mode.
Start and stop operation timing
２ 線式設定時の開始・停止動作タイミング
ストップ
Stop
condition
コンディション
in the 2-wire mode
スタート
Start
condition
コンディション
ストップ
Stop
condition
コンディション
Serial clock
シリアルクロック
(SCK)
（ SCK)
Serial
input/output
シリアル入出力
(SDIO)
（ SDIO)
（ ACK）
STP=
“1” executionTSTA1="1"実行
STP="1"実行
TSTA= “1” execution
シリアル出力
Serial
output
カウンタ
counter
(OTC0
to～
OTC3)
（ OTC0
OTC3)
（ ACK）
TSTA2= “1” execution
TSTA2="1"実行
Execution of
命令の実行
instruction
E
STP= “1”
execution
STP="1"実行
F/FReset=
Reset="1"実行
F/F
“1” execution
７
６
０
F/F Reset= “1” execution
F/F Reset="1"実行
F
７
６
０
F
E
シリアル入力
Serial input counter
(ITC0 to カウンタ
ITC3)
E
７
６
５
０
F
７
６
５
０
F
E
（ ITC0～ ITC3)
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1-2. Examples of Serial Mode Settings
Examples of settings in the 3-wire, 2-wire and UART modes are shown below. Adjust settings according to the required
specifications.
(1)
Example of 3-wire serial mode setting
Setting bit
Condition setting data
M0, M1
3-wire setting (M0 = 0, M1 = 1)
CK0, CK1, OSC0, OSC1
Serial clock frequency setting
Master setting (MASTER = 1): Refer to an example of master operation timing.
MASTER
Slave setting (MASTER = 0): Refer to an example of slave operation timing.
POL
Serial clock stop state = L、
Data output at the rising edge and data input at the falling edge (POL = 0)
NchS
CMOS setting (NchS = 0)
SIS
Setting of SDIO pin to serial input (SIS = 0)
STPS
Setting of stop condition to input counter (STPS = 0)
SWENA
Stop weight disabled (SWENA = 0)
MSB
Output beginning with the least significant bit (MSB = 0)
SOS
Data output: SOS = 1, Data input: SOS = 0
STA0~3
Serial input/output start data: 0h
STP0~3
Serial input/output stop data: 8h
PSEL, SIO
Select CMOS pin (SDIO1, SCK1) (PSEL = 0, SIO = 1)
Example of serial interface timing in the 3-wire master mode
Serial
シリアル入出力
input/output
（ SDIO1)
SO8
2
SO0
SO1
(SDIO1)
8
SO2
SO7
2
SI0
HZ
SI1
０
１
２
STP= “1”
STP="1"実行
execution
７
２
０
７
TSTA= “1”
TSTA1="1"実行
execution
８
１
８
Serial clock stop
シリアルクロック停止
Issue of interruption
割り込み発行
０
１
HZ
SO7
７
１
７
８
Issue of
interruption
割り込み発行
０
SI7
TSTA1= “1”
TSTA1="1"実行
execution
８
8
データ入力
Data
input
Execution of
instruction STP="1"実行
STP= “1” execution
命令の実行
１
データ出力
Data
output
シリアル出力
Serial output
カウンタ
counter
（ OTC0～
(OTC0
toOTC3)
OTC3)
Serial input
シリアル入力
counter
カウンタ
(ITC0
toITC3)
ITC3)
（ ITC0～
3
SOS= “0”
setting
SOS="0"設定
１
シリアルクロック
Serial clock
出力（ SCK1)
output
(SCK1)
SOS="0"設定
SOS=
“0” setting
•
SOS="1"設定
BUSY1
Example of serial interface timing in the 3-wire slave mode
SO8
HZ
SI0
(SDIO1)
SI2
１
SI7
HZ
SO7
2
SO0
０
１
１
２
６
２
７
SO1
７
０
８
０
SOS="1"設定
SOS=
“1”
setting
８
０
FF
FF Reset="1"
Reset= “1”
実行
execution
８
8
SO7
HZ
データ出力
Data
output
SOS= “0”
SOS="0"設定
setting
Execution of
instruction
命令の実行
SI1
8
Dataデータ入力
input
STP= “1”
execution
STP="1"実行
シリアル出力
Serial
output
カウンタ
counter
（ OTC0to
～OTC3)
OTC3)
(OTC0
Serial input
シリアル入力
counter
カウンタ
(ITC0
ITC3)
（ ITC0to
～ ITC3)
3
１
１
６
７
７
８
FF
“1”
FF Reset=
Reset="1"
execution
実行
SOS="0"設定
Serial
シリアル入出力
input/output
（ SDIO1)
2
Issue
of
割り込み発行
interruption
１
シリアルクロック
Serial clock
入力（ SCK1)
output
(SCK1)
Issue of
割り込み発行
interruption
•
BUSY1
RX　F/F
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Example of serial mode setting in the 2-wire mode
Setting bit
Condition setting data
M0, M1
2-wire setting (M0 = 0, M1 = 1)
CK0, CK1, OSC0, OSC1
Serial clock frequency setting
Master setting (MASTER = 1): Refer to an example of master operation timing.
MASTER
Slave setting (MASTER = 0): Refer to an example of slave operation timing.
POL
Serial clock stop state = H、
Data output at the falling edge and data input at the rising edge (POL = 1)
NchS
N-ch open drain setting (NchS = 1)
SIS
Setting of SDIO pin to serial input (SIS = 0)
STPS
Setting of stop condition to input counter
SWENA
Stop weight enabled (SWENA = 1)
MSB
Output beginning with the most significant bit (MSB = 1)
SOS
Data output: SOS = 1, Data input: SOS = 0
STA0~3
Serial input/output start data: 7h
STP0~3
Serial input/output stop data: Eh
PSEL, SIO
Select N-ch open-drain pin
(SDIO2, SCK2) (PSEL = 1, SIO = 1)
ストップ
Stop
Startスタート
condition condition
コンディション
コンディション
０
E
割り込み発行
Issue of interruption
７
６
５
SI6/SO6
SI0/SO0
７
６
０
F
０
F
SIF/SOF（ ACK）
“1” execution
F/F Reset=
Reset="1"実行
マスタ設定時
： SOS="1"設定
Master mode: SOS=
“1” setting
スレーブ設定時
： SOS="0"設定
Slave mode: SOS=
“0” setting
６
SI7/SO7
割り込み発行
Issue of interruption
７
SIF/SOF（ ACK）
TSTA2= “1” execution
TSTA2="1"実行
the master ）mode)
（(in
マスタ設定時
SI0/SO0
F/F
Reset="1"実行
F/F Reset=
“1” execution
SI6/SO6
Data output: ：SOS=
“1” setting
データ出力時
SOS="1"設定
Data input: SOS=
“0” setting
データ入力時
： SOS="0"設定
SI7/SO7
E
ストップ
Stop
condition
コンディション
SCK端子より"L”レベルを出力してシリアル
SCK pin outputs the “L” level to forcibly
クロックを強制停止状態にします
stop the serial clock 。
TSTA1="1"実行
TSTA1= “1” execution
（ マスタ設定時）
(in the master mode)
STP= “1” execution:
Execution
STP="1"実行
： 内部初期化実行
internal initialization
（of
マスタ時はストップコンディション
(Stop condition is outputted in
出力が出力されます）
the master mode)
Execution of
命令の実行
instruction
シリアル出力
Serial
output
カウンタ
counter
（ OTC0to
～OTC3)
OTC3)
(OTC0
シリアル入力
Serial input
カウンタ
counter
（ ITC0to
～ITC3)
ITC3)
(ITC0
マスタ設定時
： SOS="1"設定
Master mode: SOS=
“1” setting
スレーブ設定時
： SOS="0"設定
Slave mode: SOS=
“0” setting
Serial clock
シリアルクロック
(SCK2)
（ SCK2)
シリアル入出力
Serial
input/output
（ SDIO2)
(SDIO2)
(STPS = 1)
７
６
５
０
F
F
STP="1"実行
STP= “1” execution
（(in
マスタ設定時
the master）mode)
(2)
E
E
BUSY1
BUSY2
RX　F/F
Note:
The start condition (STA1 = “1”) cannot be outputted at the ACK input/output timing during
2-wire operation (BUSY2 = “1”) in the master mode. Output the stop condition, and then the
start condition.
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(3)
Example of UART mode setting
Setting bit
Condition setting data
M0, M1
UART setting (M0 = 0, M1 = 1)
CK0, CK1, OSC0, OSC1
Transmission rate setting
MASTER
Master setting (MASTER = 0)
POL
Serial clock stop state = H、
Data output at the falling edge and data input at the rising edge (POL = 0)
NchS
N-ch open drain setting (NchS = 1)
SIS
Setting of serial data pin to RX pin (SIS = 0)
(STPS = 1)
STPS
Setting of stop condition to input counter
SWENA
Stop weight disabled (SWENA = 0)
MSB
Output beginning with the least significant bit (MSB = 0)
SOS
Data output (SOS = 1)
STA0~3
Serial input/output start data: 0h
STP0~3
Serial input/output stop data: 9h
PSEL, SIO
Select N-ch open-drain pin (TX2, RX2) (PSEL = 1, SIO = 1)
tsck
Receiving (RX)
受信（ RX）
SI0
Maximum tsck/8
最大tsck/8
Sending
(TX)
送信（ TX
）
SI5
SI6
Receiving
(RX)
受信(RX)
tsck
SO6 SO7 SO8 SO9
=1 =1
SO0 SO1
SO9=1
SI1
Pulse
widths of tsck/4 or below is not considered
as received
tsck/4以下のパルス幅は受信と判断しません
。
Sending
(TX)
送信(TX)
STP=1STP=1実行
execution
F/F Reset=1
TSTA1=1実行
TSTA1=1 execution
割り込み発行
Issue of interruption
シリアル出力
Serial output
カウンタ
counter
(OTC0
（ OTC0to
～OTC3)
OTC3)
９
シリアル入力
Serial input
counter
カウンタ
(ITC0
（ ITC0to
～ITC3)
ITC3)
９
０
１
６
７
８
Issue割り込み発行
of interruption
９
０
１
６
７
８
９
BUSY1
RX F/F
Note:
When a pulse width of tsck/4 or below is inputted during receiving (RX), the start of receiving will
be cancelled.
Note:
The UART circuit has a data judgment circuit. When receiving starts, the data judgment circuit
outputs a 3-pulse data judgment pulse in the data position to judge the RX pin state. When at
least two of these pulses record the same data, the received data is read as the serial data
input. In other words, if noise occurs in one pulse in the pulse output position, the data can be
received normally.
tsck
Receiving (RX)
受信（ RX）
SI0
SI1
データ判定パルス
Data judgment pulse
Note:
This example shows sending and receiving without parity. The SO8 bit output is outptted as the
stop bit. In the specification with parity, the SO8/SI8 bits can be assigned to parity. However, if
transmission (TX) starts immediately after the issue of interruption, the stop bit width cannot be
secured. In this case, after the interruption is issued, allow the operation to wait for a stop bit
width or more before sending is executed.
Note:
UART of this product supports the full/duplex specification. If sending and receiving operations
are executed at the same time, they can be carried out normally. However, interruption is issued
when either operation is completed and the BUSY1 bit becomes “0”. Determine receiving
operation using the RX F/F bit.
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1-3. Serial Clock Timing
TpL
Serial clock
シリアルクロック
(SCK)
（ SCK)
シリアル出力
Serial output
（(SDIO)
SDIO)
TpHL
TpLH
TpH
シリアルクロック
Serial clock
（ SCK)
(SCK)
シリアル出力
Serial output
（(SDIO)
SDIO)
TpLH
TpHL
・最小パルス幅
TpL/TpH)
： 2.5μs最小
Minimum（pulse
width
(TpL/TpH):2.5µs (minimum)
・伝達遅延時間(TpLH/TpHL)
： 50ns標準
Transmission delay time
(TpLH/TpHL): 50 ns (standard)
2. Serial Interface Configuration
～
高速発振器
High-speed
oscillator 低速発振器75kHz
Low-speed oscillator M0, M1, OSC0, OSC1, SWENA
M0,M1,OSC0,OSC1,SWENA
クロック(Xout2)
clock (Xout2)
75(Xout1)
kHz (Xout1)
TSEL, SIO, STP, FFReset
Reset
TSEL,SIO,STP,FF
Matched signal
一致信号
Serial clock generator/
シリアルクロックジェネレータ/
Timing circuit
タイミング回路
BUSY1,BUSY2
BUSY1,
BUSY2
SOERR
SOERR
SO0~9, SOE/F
SO0~9,SOE/F
Comparator
コンパレータ
STPS
STPS
MASTER
Selector
セレクタ
OCT0-OCT3
OCT0-OCT3
SCK/RX
SCK/RX
SOS
RX
RX UART
UART
circuit
回路
RX
RX
F/F
F/F
MSB
SDIO/TX
SDIO/TX
STA0-STA3
STA0-STA3
Selector
セレクタ
Serial output counter
シリアル出力カウンタ
POL
POL
STP0-STP3
STP0-STP3
シリアル入力カウンタ
Serial input counter
ICT0-ICT3
ICT0-ICT3
セレクタ
Selector
SI
デコーダ
Decoder
I/O
control
シリアル入力ラッチ
Serial input latch
SIS UART
UART
Output data
出力データ
Input data
入力データ
SI0~9,
SIE/F
SI0~9,SIE/F
～
Note:
When the serial interface function is working, the serial input-only pin (SI) can be used as an I/O port.
To use it as the SI pin, you need to set the I/O port to input.
Note:
All the serial interface pins are Schmitt input.
Note:
When the serial interface function is used and the I/O port input is enabled to break, the wait or clock
stop instruction will be released due to changes in serial input. Note that this requires input setting from
the I/O port control and reading of the I/O port input before execution of the instruction. When the clock
stop is released, CPU execution will be started after 100 ms of standby.
Note:
When the serial interface function is used, I/O port 3 can be set to a pull-up/pull-down state.
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Pulse Counter
The pulse counter is the 8-bit up/down counter that can detect the clock number through the CMOS input from PCTRin
(P3-3) pin. It can be used for counting and detection of tape running.
1. Pulse counter control ports and data ports
Pulse counter control 1
パルスカウンタコントロール
１
Y1
Y2
Y4
Y8
φL2B
POS
NEG
DOWN
*
Up/down
setting of 8-bit up and down counter
8ビットのアップダウンカウンタのアップ/ダウン設定
0: Up
count operation
0： アップカウント動作
1: Down count operation
1： ダウンカウント動作
Counter input edge setting for input pin (PCTRin pin)
入力端子(PCTRin端子)のカウンタ入力エッジ設定
POS
NEG
P3-3/PCTRin
0
0
P3-3
1
0
0
1
1
1
Input edge
入力エッジ
Rising
edge
立ち上がり
PCTRin
立ち下がり
Falling
edge
Both
edges
両エッジ
パルスカウンタコントロール
２
Pulse
counter control 2
Y1
φL2C
Y2
CTR OVER
RESET RESET
Y4
Y8
*
*
Overflow detection F/F reset
オーバフロー検出F/Fのリセット
OVER F/F is reset each time “1” is set
"1"をセットするたびにOVER F/Fがリセットされる。
パルスカウンタのリセット
Pulse
counter reset
8-bit up and down counter is reset each time “1” is set
"1"をセットするたびに8ビットのアップダウンカウンタがリセットされる。
φK2B
Y1
Y2
PＣ 0
PＣ 1
Y4
Y8
PＣ 2
PＣ 3
φK2C
Y1
Y2
PＣ 4
20
LSB
PＣ 5
Y4
Y8
φK2D
Y1
Y2
PＣ 6
PＣ 7
OVER
0
Y4
Y8
0
0
27
MSB
Pulse counter data
パルスカウンタデータ
オーバフロー検出
Overflow detection
8
0：Counter
カウンタ計測値≦2
-1
≤ 28-1
0:
measured value
8 ≤ 28 (Overflow state)
1:
Counter
measured
value
1： カウンタ計測値≧2 (オーバーフロー状態)
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The pulse counter measures the number of pulses of the input of PCTR in the (P3-3) pin.
The POS and NEG bits specify the input pin clock edge from the rising edge, the falling edges and both edges. This bit is
fixed in the normal operation.
The DOWN bit sets the up or down of the 8-bit counter. When this bit is set to “0”, the up count operation becomes
active. When this bit is set to “1”, the down count operation becomes active. Up and down counts can be switched freely.
If the clock edge is inputted during execution of the switch instruction, this count will be cancelled, please remain aware
of this.
8
The OVER F/F bit is set to “1” when an edge of 2 or higher is inputted. To activate a count operation of 8 bits or more,
this OVER F/F bit is detected to add or subtract the number of times of overflow on the data memory. After detection is
carried out by this bit, set the OVER RESET bit to “1” to reset OVER F/F.
The CTR RESET bit resets the 8-bit counter only. The counter will be reset each time this bit is set to “1”.
Counter data is loaded into the data memory in binary format.
Pulse counter control and data loading are accessed by the OUT2/IN2 instruction with [CN = BH~DH] specified in the
operand.
2. Pulse Counter Circuit Configuration
OVER RESET
CTR RESET
POS
Input enable
signal
NEG
DOWN
F/F
OVER F/F
～
CPU operation
clock
8-bit
8 bitup/down
up/downcounters
counter
Edge
Edge Detection
Detection
Selector
Selector
40
P3-3/PCTRin
～
PC0 ～PC7
3. Example of Pulse Counter Timing
パルスカウンタ制御ビット
Data set to pulse
へのデータセット
counter control bit
OVER
OVER
RESETexecution
実行
RESET
CTR/OVER
CTR
/OVER
RESET
RESETexecution
実行
DOWNビット
DOWNビット
Set DOWN
bit “1”
"1"をセット
Pulse width 30 us (minimum)
(in 75
kHz CPU operation)
パルス幅最小30us
（75kHz
CPU動作時
）
DOWN bit
CTR in入力
CTR in input
カウンタデータ
Counter data
01H
02H
03H
FFH
00H
01H
02H
N
N+1
N-1
N-2
OVER F/F
OVER F/F
Note: The CTRin input pin is the Schumitt input.
Note: The pulse counter uses the CPU operation clock (75 kHz of low-speed clock) to determine the sampling
and edges. Input a pulse width of at least twice the CPU operation clock.
Note: When the pulse counter function is used and the I/O port input is enabled to break, the wait or clock stop
instruction will be released due to changes in serial input. Note that this requires input setting from the
I/O port control and reading of the I/O port input before execution of the instruction. he first pulse is not
counted. When the clock stop is released, CPU execution will be started after 100 ms of standby.
Note: When the pulse counter function is used, I/O port 3 can be set to the pull-up/pull-down state.
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Buzzer Output
Buzzer output can be used for emitting beeps for acknowledgement and alarm purposes during key operations and when
in tuning scan mode. The type of buzzer can be selected from combinations of four output modes and eight frequencies.
1. Buzzer Control Ports
ブザー出力コントロール
１
Buzzer output control 1
Y1
Y2
Y4
Y8
φL15(0)
BF0
BF1
*
BEN
Buzzer frequency
ブザー周波数の選択データ
selection data
Buzzer
output enable bit
ブザー出力許可ビット
0: Buzzer
output Prohibitiond (“L” level when POL= “0”, “H” level
when POL= “1”)
0： ブザー出力停止(POL="0"のとき"L"レベル
、 POL="1"のとき"H"レベル)
1: Buzzer output enabled
1： ブザー出力許可
BF1
0
0
1
1
BF0
0
1
0
1
Buzzer
frequency
ブザー周波数
1kHz
1.56kHz
2.08kHz
3kHz
Duty
デューティ
2/3
1/2
2/3
2/3
注： ２／３
デューティは
Note:
2/3 duty
has the ratio 、
ofPOL="0"のとき"H”レベルと"L”レベルの比が
“H” level to “L" level of 2:1 when POL= “0”.
It isとなります
reversed when
POL= “1”.
２：１
。 POL="1"のときは反転します
。
Buzzer output control 2 ２
ブザー出力コントロール
Y1
Y2
Y4
Y8
φL15(1)
BM0
BM1
BUZR
ON
POL
Buzzer output mode
ブザー出力モード
Buzzer
output logic setting
ブザー出力論理設定
logic output.
The buzzer frequency is outputted in the positive logic from
00:：Positive
正論理出力
。 "L"レベルからブザー周波数が正論理で出力される
。
the “L” level.
11:：Negative
負論理出力
。 "H"レベルからブザー周波数が負論理で出力される
。
logic output.
The buzzer frequency is outputted in the negative logic from
the “H” level.
Selection
of I/O port 4 P4-2 or buzzer output
I/Oポート4のP4-2とブザー出力の選択
I/O port 4 (P4-2)
00:
：Select
I/Oポート4(P4-2)選択
1: Select buzzer output
1： ブザー出力選択
BM1
0
0
1
1
Y1
φK26
Y2
Y4
BM0
0
1
0
1
Buzzer output mode
ブザー出力モード
Continuous
output
連続出力
Mode A
モードA
Mode B
モードB
10H
ｚ 断続出力
モードC
10-Hz
intermittent
output
Mode C
10-Hz
outputｚat間隔出力
1 Hz intervals モードD
Mode D
10Hintermittent
ｚ 断続の1H
Single
output
単発出力
Y8
BUZR
10Hz
Buzzer
dedicated 10-Hz timing operation monitor
ブザー専用10Hzタイミング動作モニタ
Note:
When the BEN bit is set to “1”, 10 Hz operates at the base clock of 100 Hz.
注： BENビットに"1"を設定するとベースクロック100Hzにて10Hzが動作
Refer to the 10-Hz timer when Mode D is selected.
します。 ただし、 モードD設定時は、１０ Hzタイマを参照してください。
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The buzzer output is also used as the P4-2 I/O port. It can be switched to buzzer output by setting the BUZR ON bit to
“1” and setting the P4-2 I/O control port to output.
Once the buzzer frequency, mode and logic are specified, set the buzzer enable bit to “1”, and the buzzer will be emitted.
Set the buzzer enable bit to “0” for condition setting.
In the continuous output mode (Mode A), when the buzzer enable bit is set to “1”, the buzzer frequency will be outputted
continuously. Set the bit to “0” to stop the buzzer output.
In the single output mode (Mode B), a 50-ms buzzer will be outputted and stopped each time the buzzer enable bit is set
to “1”. In this mode, the buzzer output time can be extended by 50 ms to issue a 100-ms buzzer by setting the buzzer enable
bit to “1” again during output of the 50-ms buzzer. The buzzer output time can be further extended to 150 ms by setting the
bit to “1” again during extended 50 ms. This facilitates adjusting the buzzer output time.
In the 10-Hz intermittent output mode (Mode C), the cycle of 50-ms buzzer ON and OFF respectively will be repeated
continuously by setting the buzzer enable bit to “1”. Set the bit to “0” to stop the buzzer output.
In the 10-Hz intermittent output mode at 1Hz intervals (Mode D), when the buzzer enable bit is set to “1”, the cycle of
50-ms buzzer ON and OFF respectively will be outputted for 500 ms, the buzzer will be stopped for 500 ms and again the
cycle of 50-ms buzzer ON and OFF will be outputted for 500 ms. These cycles are repeated until the buzzer output is
stopped by setting the bit to “0”.
In Modes B, C and D, a 50 ms buzzer will be outputted and stopped even if the enable bit is set to “0” to stop the buzzer
in the buzzer output state. The buzzer output state can be checked based on the details of the BUZR 10 Hz bit. When the
BUZR 10 Hz bit is set to “0”, it shows the buzzer output state. When the bit is “1”, it shows the buzzer is stopped. Refer to
the 10 Hz timer in Mode D.
Buzzer control can be accessed at OUT1 instruction data port 6.
2.
Buzzer Circuit Configuration
～
1０Hz
BUZR10Hz
Selector
Selector
１00Hz
Divider
Divider
(1/10)
(1/10)
ModeD
1Hz
1kHz
~
Selector
Selector
BUZR
circuit
BUZR output
output circuit
40 BUZER(P4-2)
3kHz
BF0, BF1
BM0~BM2
BEN
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TC9349AFG
3.
Buzzer Output Timing
Buzzer
frequency
ブザー周波数
"1"
"1"
"0"
Data
set to BEN bit
ＢＥＮ
ビットへのデータセット
ブザー出力(モードA)
Buzzer output
(Mode A)
BUZR 10 BUZR
Hz 10Hｚ
最大10ms
10 ms max.
ブザー出力(モードB)
Buzzer output (Mode B)
Extended
by 50 ms Ｅ
byNビットに"1"を再度セットすると50ms延長される
setting the BEN bit again to “1”
ブザー出力中にB
。
during buzzer output
50ms
BUZR 10 BUZR
Hz 10Hｚ
10 ms max.
最大10ms
ブザー出力(モードC)
Buzzer output
(Mode C)
Buzzer frequency
50ms
ブザー周波数出力期間
output period
Stop period
休止期間
モードCでの出力状態
ブザー出力(モードD)
Buzzer output (Mode D)
500ms
Stop
休止期間
period
500ms
出力期間
Output
period
Note: To output the buzzer, set P4-2 to the output state (set the I/O control port to “1”).
Note: The buzzer is stopped compulsory by setting BEN = 0.
Note: When the frequency setting is changed during buzzer output in Mode B, it will be updated and the 10-Hz
timing change points changed.
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LCD Driver
The LCD driver is also used as an I/O port, and it allows a maximum of 72 segments to turn on. When the LCD driver is
enabled, I/O port 10 is switched to COM1 to COM4 pins and I/O port 12 is switched to S1 to S4 pins. Each of the 14 pins
of I/O ports 13, 14, 15 and 16 can be set to segment pin output.
The driving method of the LCD driver can be selected from 1/4 duty, 1/2 bias (frame frequency 62.5 Hz) and 1/3 bias
drive (frame frequency 125 Hz).
The LCD driver is built-in the constant voltage for display (VEE = 1.5 V) and the doubler circuit (VLCD = 3.0 V) that
increases the display voltage. The LCD driver ensures a stable LCD display; even if the supply voltage fluctuates. (→ Refer
to the section on the CD driver doubler circuit.)
In the 1/2 bias mode, the LCD driver provides common output at three potentials VLCD, VLCD × 1/2 and GND, and
provides segment output at two potentials VLCD, GND. In the 1/3 bias mode, the LCD driver provides common and
segment outputs at four potentials VLCD, VLCD × 2/3, VLCD × 1/3 and GND.
1. LCD Driver Ports
LCD
control
LCDdriver
ドライバコントロール
φL17
φL/K1A
Y1
Y2
SEL1
SEL2
Y1
Y2
Y4
Y8
DISP
OFF
LCD
OFF
BIAS
*
Y4
Y8
SEL4
SEL8
Selection
of LCD drive method
LCD
ドライブ方式選択
1/2 bias
0：1/2 0:
バイアス
1：1/3 1:
バイアス
1/3 bias
LCD off
control bit
オフ制御ビット
0：LCD ドライバ
I/O port
1：I/O 1:
ポート
off control bit
LCD display
表示オフ制御ビット
0：設定データ出力
0: Set data output
1：オフデータ出力
1: Off data output
0: LCD driver
Data select
データセレクト
φL13 (Data port 4)
φL13(データポート4)
Y1
Y2
Y4
Y8
φL14 (Data port 5)
φL14(データポート5)
Y1
Y2
Y4
Y8
COM1 COM2 COM3 COM4
COM1 COM2 COM3 COM4
(4)
(5)
(6)
Ｓ１
Ｓ２
Ｓ３
COM1 COM2 COM3
(F)
(0)
(1)
(2)
(3)
(4)
COM4
(5)
Ｓ１３
Ｓ１４
Ｓ１５
Ｓ１６
Ｓ１７
Ｓ１８
Segment
data
セグメントデータ
0: Turn
off
０： 消灯
1: Turn
on
１： 点灯
Ｓ１２
セグメントセレクト
Segment
select
Switching between the segment
output and I/O port
セグメント出力とI/Oポートの切り替え
0: 0:I/Oポート
I/O port
1: 1:セグメント出力
Segment output
Note:
Ｓ６
Ｓ７
Ｓ８
(C) Ｓ５
(D) Ｓ９ Ｓ１０ Ｓ１１ Ｓ１２
(E) Ｓ１３ Ｓ１４
＊
＊
(F) Ｓ１５ Ｓ１６ Ｓ１７ Ｓ１８
Segment data controls the segments on/off corresponding to the common and segment outputs.
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The LCD driver control ports are assigned to data control ports 4 and 5; as selected at the select port. These ports are
accessed by using the OUT1 instruction with [CN = 3H, 4H] specified in the operand.
LCD driver segment data
The LCD driver segment data is specified at data ports 4 and 5 (φL13 and φL14). When the segment data port is set
to “0”, the LCD display turns off. When the port is set to “1”, the LCD display turns on.
LCD OFF bit
The LCD OFF bit controls switching between the LCD output pin and the I/O port. After a reset, the pin that serves
as both an I/O port and LCD driver is in the I/O port state. Set this bit to “0” when using the LCD driver function.
When the LCD driver function is enabled, four of the I/O port pins P10-0 to P10-3 are switched to the COM1 to
COM4 output pins, and four pins P12-0 to P12-3 are switched to the S1 to S4 output pins.
Note:
This bit is set to “1” after a system reset.
DISP OFF bit
The DISP OFF bit allows all the LCD display to turn off without setting segment data. Setting this bit to “1” turns
all the LCD display off. At this time, the segment data is retained. When the DISP OFF bit is set to “0”, the previous
display will appear on the LCD as it is.
Note:
Segment data can be rewritten during DISP OFF.
Note:
After the CKSTP instruction is executed, the DISP OFF bit is set to “1”. After the CKSTP
instruction is released, set the DISP OFF bit to “0” as required.
Note:
This bit is reset to “0” after system reset.
BIAS bit
The BIAS bit selects the liquid crystal driving method. Set this bit to “0” to select the 1/2 bias method (frame
frequency 62.5 Hz) or set to “1” to select the 1/3 bias method (frame frequency 125 Hz)
Note:
In the 1/3 bias mode, the consumption current becomes about 100 µA larger than that in the 1/2
bias mode.
Note:
This bit is reset to “0” after a system reset.
Segment select port
Each of the 14 pins of I/O ports 13 to 16 can be switched to a segment pin. Set the bit corresponding to each
segment to “1” to use the pin for segment output, or set to “0” to use the pin as an I/O port. The S5 to S8 bits
correspond to pins P13-0 to P13-3 respectively. The S9 to S12 bits correspond to pins P14-0 to P14-3 respectively.
The S13 and S14 bits correspond to pins P15-0 and P15-1 respectively. The S15 to S18 bits correspond to pins P16-0
to P16-3 respectively.
Note:
Segment output and I/O port setting can be made regardless of the LCD off control bit (LCD
OFF). However, the pins that have been set to segment output require setting of the LCD off
control bit to the LCD driver to enable segment output.
Note:
Pins S21 and S22 are also used as high-speed oscillator pins. When they are set to high-speed
oscillator pins, the high-speed oscillator function has priority and this port becomes to “don't
care” state.
Note:
This bit is reset to “0” after a system reset.
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C3
C4
VLCD
VEE
VCPU
P10-0/COM1
P10-1/COM2
P10-2/COM3
P10-3/COM4
P12-0/S1
P12-1/S2
P16-0/S15
P16-1/S16
P16-2/S17/Xin2
P16-3/S18/Xout2
6
7
8
9
10
15
16
17
18
19
20
33
34
35
36
Constant-voltage
circuit
定電圧回路
VLCD
VLCD昇圧回路
doubler
circuit
1ｋＨｚ
DISP OFF
I/Oポート10
I/O
port 10
I/Oポート12
I/O port 12 ～
to 16
16
Common
コモン出力回路
output circuit
Segment driver
セグメントドライバ
VLCD
×1/2
High-speed
高速発振器
oscillator
Segment data
セグメントデータ
LCD OFF
VLCD
～
～
2. LCD Driver Configuration
VLCD×1/3
VLCD×2/3
VEE
BIAS
Bias circuit
バイアス回路
Note:
After a system reset, all the pins that also serve as the LCD driver pins will be the I/O port input
state.
Note:
The LCD driver pins are also used as I/O ports and high-speed oscillator pins.
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3. LCD Driver Operation Timing
LCD output waveform in the 1/2 bias mode (BIAS bit= “0”)
In the 1/2 bias mode, the potential of the LCD driver waveform is outputted as VLCD and GND and the VEE level
is outputted at a frame frequency of 62.5 Hz.
Example of segment data
セグメントデータ例
Segment data 1(φL13, φL14)
セグメントデータ1(φL13
、 φL14)
Y1
Y2
Y4
Y8
COM1
COM2
COM3
S1
S2
COM4
0
(S1)
COM1 COM2 COM3 COM4
1
(S2)
COM1 COM2 COM3 COM4
1
1
0
1
1
0
0
1
データセレクト(φL/K1A)
Data select(φL/K1A)
DISP OFF
2ms
16ms(62.5Hz)
VLCD(3V)
COM1
VEE(1.5V)
GND
VLCD(3V)
COM2
VEE(1.5V)
GND
VLCD(3V)
COM3
VEE(1.5V)
GND
VLCD(3V)
COM4
VEE(1.5V)
GND
VLCD(3V)
S1
GND
VLCD(3V)
S2
GND
VLCD
COM1-S1
COM1-S1
(ON waveform)
GND
(ON波形)
-VLCD
VLCD
COM2-S1
COM2-S1
(Off(OFF波形)
waveform)
GND
-VLCD
Note:
Setting the DISP OFF bit to “L” causes the common output to revert to the VLCD × 1/2 level and
turns all the display off.
Note:
All the common and segment outputs are fixed to the “L” level in the clock stop mode and for
100 ms after this is released.
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LCD output waveform in the 1/3 bias mode (BIAS bit= “1”)
The potential of the LCD driver waveform is outputted as VLCD and GND, and the intermediate potential levels,
1/3 and 2/3 of potential VLCD are outputted at a frame frequency of 125 Hz.
セグメントデータ例
Example of segment data
セグメントデータ1(φL13
φL14)
Segment data 1(φL13,、φL14)
Y1
Y2
Y4
Y8
COM1
COM2
COM3
S1
S2
COM4
0
(S1)
COM1 COM2 COM3 COM4
1
(S2)
COM1 COM2 COM3 COM4
1
1
0
1
1
0
0
1
Data select(φL/K1A)
データセレクト(φL/K1A)
DISP OFF
8ms(125kHz)
1ms
COM1
VLCD
VLCD×2/3
VLCD×1/3
GND
COM2
VLCD
VLCD×2/3
VLCD×1/3
GND
COM3
VLCD
VLCD×2/3
VLCD×1/3
GND
COM4
VLCD
VLCD×2/3
VLCD×1/3
GND
S1
VLCD
VLCD×2/3
VLCD×1/3
GND
S2
VLCD
VLCD×2/3
VLCD×1/3
GND
VLCD
VLCD×1/3
GND
－ VLCD×1/3
COM1-S1
COM1-S1
(ON
waveform)
(ON波形)
－ VLCD
VLCD
VLCD×1/3
GND
－ VLCD×1/3
COM2-S1
COM2-S1
(Off
waveform)
(OFF波形)
－ VLCD
Note:
Setting the DISP OFF bit to “1” outputs unselected waveforms as common and segment
outputs.
Note:
All the common and segment outputs are fixed to the “L” level in the clock stop mode and for
100 ms after this is released.
Note:
In the 1/3 bias mode, the frame frequency is twice as high as that in the 1/2 bias mode.
Note:
In the 1/3 bias mode, the consumption current becomes about 100 µs larger than that in the 1/2
bias mode.
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A/D Converter
The A/D converter has four channels with 6-bit resolution, and can be used for measuring electrical field strength,
measurements of battery and cell voltages and key input using ladder resistance.
1. A/D Converter Control Port and Data Port
φL23
Y1
Y2
Y4
Y8
AD
SEL0
AD
SEL1
AD
SEL2
STA
A/D converter start bit
A/D conversion is implemented each time this is set to “1”
Selection of A/D input pin
φK20
SEL2
SEL1
SEL0
AD input
0
0
0
ADin1
0
0
1
ADin2
0
1
0
ADin3
0
1
1
ADin4
1
*
*
VEE/2
φK21
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
AD0
AD1
AD2
AD3
AD4
AD5
BUSY
0
A/D converter operation monitor
LSB
A/D conversion data
MSB
0: A/D operation finished
1: A/D converting
The A/D converter operates using a serial comparison system with 6-bit resolution. The standard voltage for A/D
conversion is the internal power supply (VDD), which is divided into 64 parts. The divided voltage is compared to the A/D
input voltage and the data is outputted to the A/D conversion data port. The A/D conversion input uses the multiplex
method; consisting of four channels of external input pins (ADin1 to ADin4 pins) and the half potential of the VEE pin
voltage. The desired method can be selected by the AD SEL0 to 2 bits.
The A/D converter carries out A/D conversion each time the STA bit is set to “1”, and finishes operation after 6 machine
cycles (240 µs). Completion of the A/D converter operation can be determined by checking the BUSY bit. Once the A/D
conversion is finished, the A/D conversion data is taken into the data memory.
The results of the A/D conversion can be obtained by performing the following calculation:
VDD ×
n − 0.5
64
(63 >
=n>
= 1) <
= A/D input voltage <
= VDD ×
n + 0.5
64
(62 >
=n>
= 0)
(n: A/D conversion data value [decimal scale])
VEE/2 for A/D input is used for battery detection. The VEE potential is normally 1.5 V. The half potential of the VEE pin
voltage, 0.75 V, is selected for A/D input. Through the A/D conversion of this potential, the reference potential, VDD, can
be detected. When the VDD potential is 1.5 V, the A/D conversion data is 20H. As the VDD potential becomes lower, the
A/D data becomes higher. When the VDD potential is 0.75 V, the A/D conversion data is 3FH.
This control is accessed by using the OUT2/IN2 instructions with [CN = 3H, 4H] specified in the operand.
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2. A/D Converter Circuit Configuration
Sample
hold
VDD
SEL0~2
11
ADin1 (P6-0)
12
ADin2 (P6-1)
13
ADin3 (P6-2)
14
ADin4 (P6-3)
9
VEE
R 3R/2
BUSY
Control
circuit
R
R
STA BUSY
Decoder
AD5
A/D conversion latch
AD0
~
A/D conversion data
Comparator
R/2
VDB
(VDD doubled voltage)
VEE constant-voltage
circuit
BUSY
The A/D converter consists of a 6-bit D/A converter, a sample hold, a comparator, an A/D conversion latch and a control
circuit. The 6-bit D/A converter and the comparator operate only when the BUSY bit is “1”. Therefore, the A/D converter
consumes no current when it is not operating. The half potential of VEE constant voltage can be selected as the A/D input.
The A/D converter operates on the doubled voltage VDB (VDD × 2).
Note: Set to “1” the I/O port –6 (N-ch open-drain) output data corresponding to the A/D input pin to be used, to
use the pin in the input state.
Note: The VEE contant-voltage potential is used for the LCD driver driving voltage and the reference voltage of
reduced-voltage detection circuit for the DC-DC converter for CPU and VT.
Note: Voltage of 0 V to VDB pin level can be applied to the A/D input pin.
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Programmable Counter
The programmable counter consists of a 2-modulus pre-scalar, a 4-bit and 12-bit programmable counter and a port that
controls these elements.
The programmable counter stops operation in the PLL off mode, and operates in the PLL on mode respectively. The
radiation and consumption current can be reduced when the programmable counter is used in combination with the 1-chip
tuner with a built-in 1/16 pre-scaler.
The frequency divided by the programmable counter is inputted to the phase comparator, and the phase difference from
the reference frequency is outputted from the phase comparator. The internal clock of the programmable counter can also be
used to detect phase difference of the phase comparator and the doubler clock for DC-DC converter for VT.
(→ Refer to the sections on Reference frequency divider, DC-DC converter for VT and Phase comparator.)
1. Program Counter Control Port
The PLL mode selection port is used for setting the frequency dividing method, while the programmable counter port is
used for setting the frequency division number.
Selection of PLL mode
φL15(8)
Y1
Y2
Y4
Y8
HF
∗
∗
O
Setting the frequency dividing method
0：LF mode
1：HF mode
Programmable counters 1 to 4
φL15(B)
φL15(A)
φL15(C)
φL15(D)
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11
LSB
φL16(F)
φΚ11(F)
Y8
Y1
Y2
Y2
Y4
Y8
TA0
TA1
TA2
TA3
PLL amplifier setting register
Y8
P12 P13 P14 P15
Setting the frequency division number of the programmable counter
Y1
Y4
MSB
Set ALL “1” (FH)
The selection of the PLL mode and setting of the frequency division number of programmable counter are assigned to
data port 6 that has been selected at the select port. These controls are accessed by using the OUT1 instruction with [CN =
5H] specified in the operand.
There are two types of frequency division methods; the direct frequency division method (LF mode) and the pulse
swallow method (HF mode). Select a method depending on the frequency to be used and the frequency division number
that has been set.
The programmable counter has 12 bits (P4 to P15) in the LF mode and 16 bits (P0 to P15) in the HF mode. The
frequency division number is specified by writing it to the MSB bit (φL15(D). Once the MSB bit is set, all the data of P0 to
P15 will be updated. Therefore, the MSB bit must be accessed and specified last, even when part of the data is changed.
The PLL input (OSCin) has an input amplifier. Set this amplifier gain at the PLL amplifier setting registers. Set all of
these registers to “1” (FH).
Note:
Set the Y8 bit of the PLL mode select port (φL15(8)) to “0”.
Note:
All the PLL amplifier setting registars are set to “1” after a system reset.
Note:
In the PLL amplifier setting registers, the TA0 and TA1 bits are for the OSCin input amplifier gain
setting and the TA2 and TA3 bits are for the IFin input amplifier gain setting respectively.
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2. Setting the Frequency Dividing Method and Gain of The Programmable Counter
Using the HF bit, select the pulse swallow or direct frequency division methods; depending on the received frequency.
The programmable counter is used in combination with the 1-chip tuner with a built-in 1/16 or 1/8 pre-scaler. Usually,
use the tuner to input the local oscillation frequency, which is then inputted to the OSCin input in the MW/LW/SW
wavebands. The tuner local oscillation frequency is divided into 16 or 8 parts and the divided frequency is inputted to the
OSCin input in the FM/TV band mode.
The OSCin input has an input amplifier that allows small-amplitude operation. The input amplifier has the registers
(φL16(F), φK11(F)) to adjust the amplifier gain. Set all of these registers to “1” (FH).
Mode
HF
Frequency dividing
method
OSCin operation input
frequency range
Example of
receive band
Frequency dividing
range
LF
0
Direct frequency
dividing method
0.5~4 MHz
MW/LW
10H~FFFH
(16~4095)
HF
1
Pulse swallow method
(1/15･16)
1~30 MHz
SW/FM/TV
210H~FFFFH
(528～65535)
Note: The local oscillation input is common to each mode and is inputted to the OSCin pin.
3. Setting the Frequency division number
Set the frequency division number for the programmable counter at P0 to P15 bits in the binary format.
• Pulse swallow method (16 bits)
MSB
LSB
P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
15
2
P0
0
2
Frequency division setting range (n = 210H~1FFFFH (528~65535))
• Direct frequency division method (12 bits)
MSB
LSB
P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
P5
P4
11
2
P3
P2
P1
P0
0
Frequency division setting range (n = 10H~1FFFH (16~4095))
2
don’t care
Note:
Set the frequency division value in consideration of the tuner pre-scaler frequency division.
Note:
Set the frequency division number by writing it into the MSB bit (φL15(D)).
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4.
Programmable Counter Circuit Configuration
The circuit consists of an amplifier, 1/15･16 2-modulus pre-scaler, a 4-bit swallow counter and a 12-bit binary
programmable counter. When the HF mode is selected, the 1/15･16 pre-scaler, the 4-bit swallow counter and the 12-bit
binary programmable counter are used. When the LF mode is selected, only the 12-bit binary programmable counter is
used.
The OSCin input clock is supplied to the DC-DC converter for VT, and used as the doubler clock. The clock divided
by the programmable counter is also supplied to the phase comparator and the IF counter.
(→ Refer to the sections on DC-DC converter for VT and Phase comparator.)
P0~P3
VPLL 50
OSCin
0.01 µF
51
TA0, TA1
Amplifier
4-bit
swallow counter
1/16
HF
Preset
1/15･16
HF
1/15
12-bit
programmable counter
LF
To phase comparator
P4~P15
To DC-DC converter for VT
To phase comparator
To IF counter
Note: The programmable counter uses the VPLL pin power supply. This power supply can be supplied
regardless of the power supply level of the VDD/VCPU pin. In the PLL off mode, the VPLL pin power
supply can be turned off. The programmable counter setting registers use the VCPU pin power supply, so
that the contents of the registers are retained after the VPLL pin power supply is turned off.
Note: The OSCin pin has an amplifier that allows small-amplitude operation with coupled capacitor. The OSCin
input is subject to high impedance in the PLL off mode.
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Reference Frequency Divider
The external 75 kHz crystal oscillation frequency is divided to generate the following ten types of PLL reference
frequency signals; 1 kHz, 1.39 kHz, 1.56 kHz, 2.78 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz and 25 kHz
respectively. These signals can be selected by the reference port data.
The selected signal is supplied as a reference frequency for the phase comparator as described below. The PLL on/off is
controlled by the contents of the reference port.
1. Reference Port
This is an internal port for selecting ten types of reference frequency signals. This port is located in data port 6 as selected
at the select port, and can be accessed by using the OUT1 instruction with [CN = 5H] specified in the operand. When the
reference port is set to all “1”, all the programmable counters, IF counters, reference counters and the phase comparator will
be stopped and enter the PLL off mode. When the reference port setting is set, the frequency division setting data for the
programmable counter will be updated. Therefore, the frequency division number of the programmable counter must be
determined before setting the reference port.
φL15(E)
Y1
Y2
Y4
Y8
R0
R1
R2
R3
Reference frequency select code
Oscillation
frequency
R3
R2
R1
R0
0
0
0
0
0
1 kHz
0
0
0
1
1
1.3889 kHz
0
0
1
0
2
1.5625 kHz
0
0
1
1
3
2.7778 kHz
0
1
0
0
4
3 kHz
0
1
0
1
5
3.125 kHz
0
1
1
0
6
5 kHz
0
1
1
1
7
6.25 kHz
1
0
0
0
8
12.5 kHz
1
0
0
1
9
25 kHz
1
0
1
0
A
Prohibition
1
0
1
1
B
Prohibition
1
1
0
0
C
Prohibition
1
1
0
1
D
Prohibition
1
1
1
0
E
Prohibition
1
1
1
1
F
PLL off mode
Note:
After a system reset, this port is set to all “1” and becomes to PLL off mode.
Note:
When the ΙΝΗ pin input permission is set by using the ΙΝΗ ENA bit, the PLL off mode becomes the
ΙΝΗ input or the PLL off mode as shown above.
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Phase Comparator and Lock Detection port
The phase comparator compares the reference frequency supplied from the reference frequency divider and the
programmable counter divided frequency output to determine the phase difference and outputs errors. It then controls the
voltage control oscillator (VCO) through the low-pass filter to match the frequency and phase difference of these two
signals.
There are two pins available for the phase comparator, each including individually adjustable output resistance. This
resistance can be set to three types, namely 5, 50 and 100 kΩ. It also includes automatic switching by detection of the phase
difference, the N-channel transistor for an LFP amplifier that withstands 5.5 V and the external charge pump output mode.
The phase comparator and the charge pump output use the DC-DC converter power supply (VDB: VDD × 2) for CPU.
Note that the phase comparator output pins (DO1/2) can be used as general-purpose output ports by using the DO control
port.
1. Phase Comparator (DO) Control Port and Unlock Detection Port
DO1 control
DO1コントロール
Y1
Y2
Y4
φL24
R0
R1
M0
DO1/DO2
output state setting
DO1/DO2出力状態の設定
Y8
M1
M0
0
0
0
1
1
0
1
1
M1
出力状態
Output
state
位相比較器出力
Phase
comparator output
"L"レベル出力
“L”
level output
OT
OT出力
output
"H"level
レベル出力
“H”
output
ハイインピーダンス
High impedance
DO1/DO2
output resistance setting
DO1/DO2出力抵抗設定
DO2
control
1
DO２
コントロール
１
Y1
φL25
R0
Y2
R1
Y4
M0
DO output
resistance
DO出力抵抗
R1
R0
0
0
0Ω
0
1
5kΩ
1
0
50kΩ
1
1
100kΩ
Y8
M1
DO2 control 2
DO２ コントロール２
Y1
Y2
Y4
φL26
AUTO
ENA
CK0
Y8
CK1
Selection of DO2 output resistance phase
DO2出力抵抗の位相差検出クロックの選択
difference detection clock
CK1
CK0
Phase difference
位相差検出クロック(fd)
detection clock (fd)
0
0
OSCin/2
0
1
OSCin/4
1
0
OSCin/8
1
1
OSCin/16
Permission of phase difference
位相差検出動作の許可
detection
0： 禁止
0: Prohibition
1： 許可
1: Enabled
0: Prohibition
0： 禁止
DO2 output resistance automatic
DO2出力抵抗自動切り替え制御
1: Enabled
switching control
1： 許可
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φL27
UNLOCK
RESET
PN
POL
LPF
ON
Built-in LPF control
内蔵LPF制御
0： オフ 0: Off
1： オン 1: On
0: Positive logic
0： 正論理
Selection of PN output logic
PN出力論理選択
1： 負論理
1: Negative logic
PN
output control
PN出力制御
0： 禁止 0: Prohibition
1： 許可 1: Enabled
Unlock F/F and Unlock enable are reset each
Unlock
reset
アンロックリセット・・・データ"1"をセットするたびにアンロックF/Fとアンロック
time the data is set to “1”.
イネーブルをリセットする。
φK27
Note:
Y1
Y2
F/F
ENA
Y4
Y8
（Unfixed
不定） （Unfixed
不定）
Unlock enable
アンロックイネーブル
0：0:PLLアンロック検出待ち状態
PLL unlock detection standby
1：1:PLLアンロック検出が可能
PLL unlock detection enabled
Unlock detection bit
アンロック検出ビット
PLL lock state
0：0:PLLロック状態
PLL unlock state
1：1:PLLアンロック状態
Y4/Y8 bits of the unlock port (φK27) become unfixed.
The phase comparator control port and the unlock detection ports are accessed by using the OUT2 instruction with [CN =
4H, 5H, 6H, 7H] and the IN2 instruction with [CN = 7H] specified in the operand. These control bits are reset to “0” after a
system reset.
Output mode setting (M0 and M1 bits)
The M0 and M1 bits are used for setting the phase comparator output (DO1/2 output pin) state. The phase
comparator output, the “H” and “L” levels and high impedance (HZ) state can be set.
Note:
If the PLL off mode is selected, the “HZ” will be retained in the phase comparator output state,
and the “H”/”L” level will be retained when the “H”/“L” level is selected.
Note:
When PN = “1” is selected, the PN output mode has the priority.
Output resistance setting (R0 and R1 bits)
The R0 and R1 bits are used for setting the output resistance of the phase comparator output individually for DO1
and DO2 pins. They can be set to four states; the normal output buffer state, 5 kΩ, 50 kΩ and 100 kΩ.
Note:
The output resistance is set regardless of the output mode (M0, M1) and the PN output mode.
Therefore, set these bits to “0” when the “H”/“L” level or the PN output mode is selected.
Note:
When the DO2 pin is set to the automatic phase difference switching mode, the R0/R1 bits of
DO2 control 1 becomes to the “don’t care” state.
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Automatic phase difference switching mode (DO2 control 2 port: AUTO, ENA, CK0 and CK1 bits)
The DO2 pin has an automatic phase difference switching mode that switches the output resistance automatically;
depending on the phase difference. In this mode, the output resistance becomes higher as the phase difference pulse
becomes shorter, and vice versa. In other words, the system operates with a higher resistance in the lock state and
conversely, with a lower resistance in an unlocked state. By using this mode, the lock up time can be improved.
When the ENA bit is set to “1”, the phase difference detection operation is enabled. When the AUTO bit is set to
“1”, the DO2 output resistance switching is implemented.
Phase difference detection is implemented using the operation clock from the programmable counter circuit. This
clock counts the unlock state in the binary format. Four types of OSCin input, 1/2, 1/4, 1/8 and 1/16 can be selected
for this clock. The output resistance setting time can be switched by switching the clock. This control selects the
clock frequency using the CK0 and CK1 bits. Select the clock frequency depending on the lock up time. After locking,
turn off automatic switching and set the output resistance to fixed settings (R0 and R1 bits) as needed.
基準周波数（ｆｒ）
Reference frequency (fr)
プログラマブル
カウンタ出力（ｆｓ）
Programmable
counter
output (fs)
DO出力
DO output
位相誤差 Phase error
td=1/fd
位相差検出クロック
Phase difference
detection clock
5
kΩ
DO2 output
resistance state
DO2出力抵抗の状態
0kΩ
100kΩ
50kΩ
＜ タイミング例ー１＞
＜Timing example 1＞
Output
resistance
出力抵抗値
＜ タイミング例ー２＞
＜Timing example 2＞
Phase difference
resistance period
位相差抵抗期間
CK1
CK0
Phase difference
位相差検出クロック(fd)
detection clock (fd)
value
ｆｒ＜ｆｓ（
例－１）
fr＜fs
(Example-1)
fr＞fs
(Example-2)
ｆｒ＞ｆｓ（
例－２）
0
0
OSCin/2
100kΩ
ー
0～ td/2
0
1
OSCin/4
50kΩ
0～ 0.5×ｔｄ
0～ 1.5×td
1
0
OSCin/8
5kΩ
0.5×ｔｄ～ｔｄ
td～ 2.5×ｔｄ
1
1
OSCin/16
0kΩ
td～ 2×ｔｄ
2×td～ 2.5×ｔｄ
Note:
When PN = “1” is selected, the PN output mode has priority.
Note:
Effective only when the DO2 output mode setting is in the phase comparator output state.
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PN output mode (PN and POL bits)
The PN output mode is available using an external charge pump. When this mode is selected, the two DO1/2 pins
are switched to the P- and N-output pins. The P/N output logic can be reversed by using the POL bit.
An example of the use of an external charge pump is shown below. Configure the circuit depending on your
desired characteristics.
ＤＣ－ＤＣ
DC-DC
コンバータ
converter
VVDB
DB
～
P
Reference frequency
基準周波数
プログラマブル
Programmable
カウンタ出力
counter output
53
Phase
位相比較器
comparator
VT
N
VCOの
To vari-cap of VCO
バリキャップへ
54
POL
～
Example外部チャージポンプ使用回路例
of use of the external charge
pump (when
（ PN="1"設定
） PN= “1”)
Note:
Set the POL bit to “0” unless the PN output mode is selected.
Note:
When the PN output mode is selected, the output will be CMOS output and the “H” level will be
the VDB pin level outputp.
Built-in LPF amplifier (LPF ON bit)
This amplifier incorporates the N-channel FET transistor for LPF. This transistor withstands 5.5 V and it can
configure the voltage control oscillator (VCO) that can vary the VT within a range of 0 to 5.5 V.
Setting the LPF ON bit to “1” turns the built-in LPF on. Pins DO2 and P9-1 are then switched to the FET gate
input (Tin) and the FET drain pin (Tout) respectively. The DO2 phase comparator output is connected to the FET
gate pin. The LPF can be configured only by connecting an external filter resistor and capacitor.
1000pF
VVDB
DB
V
VDB
DB
基準周波数
Reference
frequency
プログラマブル
Programmable
カウンタ出力
Tout
Phase
位相比較器
comparator
54
4.7kΩ
55
0.47uF
～
Tin
VT
10kΩ
VCOの
To vari-cap of VCO
バリキャップへ
0.01uF
counter output
～
R0,R1
Voltage
of DC-DC converter for VT
VT用DC-DCコンバータ電圧
内蔵ローパスフィルタアンプアンプの構成（ LPF ON="1"設定）
Configuration of built-in low-pass filter amplifier (when LPF ON= “1”)
Note:
When the built-in LPF is used, the DO2 output mode, resistor setting and the automatic phase
difference switching mode are available.
Note:
The Tout output withstands up to 5.5 V. Do not use voltages exceeding this limit.
Note:
Set the resistance values for R0 and R1 depending on your desired characteristics.
Note:
The filter circuit constants shown above are for reference only. Examine and design actual
circuits according to the system band configuration and your desired characteristics.
Note:
The Tout pin is also used as pin P9-0. When the built-in LPF is used, the P9-0 output data will
be invalid.
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TC9349AFG
Unlock detection port (UNLOCK RESET, UNLOCK F/F and ENA bits)
The unlock F/F detects the phase difference between the programmable counter frequency-divided output and the
reference frequency at the timing with a phase shift of about 180°. If the phases do not match, or are in an unlocked
state, the unlock F/F will be set. Each time the unlock reset bit is set to “1”, the unlock F/F will be reset.
To detect the phase difference during the reference frequency cycle, it is necessary to provide an unlock F/F reset
time no shorter than the reference frequency cycle before the unlock F/F is accessed. The enable bit is provided for
this purpose. Make sure that the unlock enable is set to “1” before the unlock F/F is accessed.
2. Phase Comparator and Unlock Port Timing
Reference
基準周波数
frequency
プログラマブル
Programmable
カウンタ出力
counter output
High
impedance
ハイインピーダンス
DO出力DO output
"H"
“H”レベル(VDB)
level
"L"レベル(GND)
“L” level
Phase difference
位相誤差
ロック検出ストローブ
Lock
detection strobe
アンロックリセット
Unlock reset execution
の実行
When
PN=、“1”
and POL= “0”
PN="1"
POL="0"設定時
アンロックF/F
Unlock F/F
アンロックイネーブ
Unlock enable
ル
"H" レベル(VDB)
“H”
level (VDB)
P出力(DO1端子)
P
output (DO1 pin)
“L”
level (GND)
"L"レベル(GND)
"H" レベル(VDB)
“H”
level (VDB)
N
output (DO2 pin)
N出力(DO2端子)
"L"レベル(GND)
“L”
level (GND)
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3. Phase Comparator and Unlock Port Circuit Configuration
VVDB
DB
～
Reference
frequency
基準周波数
デコーダ
Decoder
VVDB
DB
Phase
位相比較器
comparator
Programmable
counter
プログラマブル
カウンタ出力
output
53 DO1/OT1/P
R0,R1
PN
、 POLビット
PN
and POL bits
UNLOCK
ENABLE
UNLOCK
F/F
VVDB
DB
デコーダ
Decoder
UNLOCK RESET
セレクタ
Selector
Phase difference
位相差カウンタ
counter
Selector
セレクタ
Programmable
プログラマブル
カウンタクロック
counter
clock
54 DO2/OT2/N/TIN
R0,R1
LPF ON
55 P9-0/Tout
AUTO
CK0,CK1
P9-0
output data
P9-0出力データ
～
Note: The phase comparator circuit block uses the VDB power supply. Therefore, the VDB power supply level
is outputted as the “H” level of the phase comparator output pin (DO).
～
470pF
VCOのTo vari-cap
of VCO
バリキャップへ
10KΩ
1uF
VT
Tin
54
Tout
10kΩ
0.01uF
4.7KΩ
54
220pF
0.01uF
1KΩ
VT
55
DO2
注
Note
～
To vari-cap
VCOの
of VCO
バリキャップへ
4.7kΩ
Power
電源
電源supply
（(V
VDD)
DD)
1000pF
0.47uF
～
DC-DC
DC-DC
コンバータ
converter
DC-DC
DC-DC
コンバータ
converter
～
Example 外部ローパスフィルタアンプ回路例
of external low-pass filter amplifier circuit
内蔵ローパスフィルタアンプ回路例
Example of built-in
low-pass filter amplifier circuit
Note: The phase comparator pin has a built-in resistor. Add an output resistor if needed.
Note: For details of the DC-DC converter, refer to the section on the DC-DC converter for VT. When the DCK1
internal doubler transistor is used for the DC-DC converter voltage, design the tuner circuit to widen the
variable range of the tuning voltage (VT).
Note: In the PLL off mode, the phase comparator output (DO1/2) will be “Hz”. When the external low-pass filter
(LPF) is used, the external LPF base potential will be unfixed, and the consumption current will increase
from the power supply (VDD) through the transistor. In the tuner off state (PLL off mode), fix the phase
comparator output (DO1/2) to the “L” level output.
Note: The filter circuit constants shown above are for reference only. Examine and design actual circuits
according to the system band configuration and your desired characteristics.
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TC9349AFG
DC-DC Converter for VT
This product incorporates the DC-DC converter for the PLL low-pass filter.
The DC-DC converter increases voltage by using coil induced electric power. There are two methods for increasing
voltage; using the built-in N-channel transistor and using the external transistor. Select either method depending on the
voltage to be increased. This product also a VT clamps function to prevent exposure to voltage exceeding a certain limit.
The clamp function is helpful for reducing the consumption current and protecting this product.
1. Control Port of DC-DC Converter for VT
Control
1 for DC-DC converter for VT
VT用DC-DCコンバータコントロール
１
φL15(5)
Y1
Y2
Y4
Y8
VDET
SEL
0
VDET
ENA
*
Permission of detection voltage input
DC-DCコンバータ用検出電圧入力許可
for DC-DC converter
Selection of detection voltage for
DC-DCコンバータ用検出電圧選択
DC-DC converter
0: Prohibition
0:禁止
1:許可
1: Enabled
0： 検出電圧0.75V
0: Detection
voltage 0.75 V
1： 検出電圧1.00V
1: Detection
voltage 1.00 V
Control
2 for DC-DC converter for VT
VT用DC-DCコンバータコントロール
２
φL15(6)
Y1
Y2
Y4
Y8
DD0
DD1
DD2
DD3
Selection
of clock output frequency for DC-DC converter
DC-DCコンバータ用クロック出力周波数選択
Output
出力周波数
frequency
Remarks備考
DD3
DD2
DD1
DD0
0
0
0
0
0
クロック停止
Clock stop
POL=0
、POL=1
→→
DDCK出力"H”または"HZ”
POL=0→
→DDCK出力"L”
DDCK output “L”,
POL=1
DDCK output “H” or “HZ”
0
0
0
1
1
PCTRin
External clock can be used from the P3-3/PCTRin pin input.
(Note)
P3-3/PCTRin端子入力より外部クロックの使用が可能
。注
0
0
1
0
2
75kHz
0
0
1
1
3
fosc/2
0
1
0
0
4
fosc/4
0
1
0
1
5
fosc/8
0
1
1
0
6
fosc/16
0
1
1
1
7
fosc/32
1
0
0
0
8
fXT2
1
0
0
1
9
fXT2/2
1
0
1
0
A
fXT2/4
1
0
1
1
B
fosc/3
注
fosc/3 Note
1
1
0
0
C
fosc/6
1
1
0
1
D
fosc/12
1
1
1
0
E
fosc/24
1
1
1
1
F
fosc/48
75 kHz low-speed oscillator clock
75kHz低速発振器クロック
Programmable counter clock
プログラマブルカウンタクロック
Note: fosc is the OSCin input clock frequency.
注： foscはOSCin入力クロック周波数です。
High-speed oscillator clock
高速発振器クロック
Note: Enable the high-speed oscillator when it is used.
注
： 高速発振器を使用するときは、 高速発振器を許可してください。
プログラマブルカウンタクロック
Programmable counter clock
注
： fosc/3のデューティは
Note:
The duty of fosc/3, 、
orPOL="0"のとき"H”または"HZ”レベルと
the ratio of the “H” or “HZ” level to the “L”
level is 2:1 when
POL=
The ratio is reversed when POL=
"L”レベルの比が
２：１
です“0”.
。 POL="1"のときは反転します
。
“1”.
注
： foscはOSCin入力クロック周波数です
。
Note:
fosc is the OSCin input clock frequency.
注： fosc/3クロック以外のクロックは、 すべてデューティ50%です。
注： PCTRin入力クロックを使用するときは、 パルスカウンタ機能を許可状態にしてください。
Note: Any clocks other than the fosc/3 clock have a duty of 50%.
Note: Enable the pulse counter function when using the PCTRin input clock
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Control
for DC-DC
converter for VT
VT 用3 DC-DC
コンバータコントロール
３
Y1
φL15(7)
Y2
DDCK DDCK
SEL
ENA
Y4
Y8
POL
*
Clock
output logic setting
クロック出力論理設定
0: 0：負論理…出力停止時“H”または“HZ”出力
Negative logic
“H” or “HZ” output when the output is
stopped
1：正論理…出力停止時“L”出力
1: Positive logic
Permission
of clock output
クロック出力の許可
Selection
of clock output pin
クロック出力端子の選択
“L” output when the output is stopped
0:
Prohibition
port function)
0：禁止
(I/O (I/O
ポート機能)
1：許可
(DC-DC
1:
Enabled
(DC-DCコンバータ出力機能)
converter output function)
0:
Use the DDCK1
pin (internal
N-ch transistor)
0：DDCK1
端子 (内部
Nch トランジスタ)
を使用
1:
Use the DDCK2
pin (external transistor)
1：DDCK2
端子 (外部トランジスタ)
を使用
The DC-DC converter for VT outputs the double clock using the DDCK1 (also used as pin P8-1) or the DDCK2 (also
used as pin P9-2). Setting the DDCK ENA bit to “1” enables the doubler operation. The DDCK SEL bit is used to select the
pin to be used.
The clamp function is provided to keep the doubled voltage at or below a certain voltage. The clamp is controlled by the
doubler detection voltage pin VDET (also used as pin P8-1). The doubled voltage is divided by resistance and the resultant
potential is inputted into the VDET pin. When the VDET pin potential becomes lower than 0.75 V or 1.00 V, the doubler
clock will operate. When the potential becomes higher than these values, the doubler clock will be stopped. The detection
voltage can be selected from 0.75 V and 1.00 V and the detection operation is enabled by setting the VDET ENA bit to “1”.
The doubler clock can be selected from 15 types. Select a frequency that is a little influence by the tuner beat or other
factors.
The control port for the DC-DC converter for VT is assigned to data port 5, and is accessed by using the OUT1
instruction with [CN = 4H] specified in the operand. These control bits are reset to “0” after system reset.
Note: Set the Y2 bit of the Control 1 for the DC-DC converter for VT (φL15 (5)) to “0”.
Note: When the doubler clock pin (DDCK1/2) and the doubler detection voltage input (VDET) are selected, the
I/O port output data and control data of the same pins will be in “don’t care” state.
Note: The DC-DC converter detection voltage input (VDET ENA bit) must be disabled (“0”) in the PLL off mode
or when it is not being used; otherwise it will increase the consumption current.
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2. Setting of DC-DC Converter for VT
Example of using the DDCK1 internal doubler transistor
The DDCK1 pin includes an N-ch transistor for the DC-DC converter, and it can drive the coil directly. This
transistor can withstand 6 V and no voltage over this level is permitted. Usually, the doubler clamp function is used to
keep the limit the voltage. Set the POL bit to “0” when the DDCK1 pin is used.
Shown below is an example of a DC-DC converter circuit using the DDCK1 pin.
The clock output of the DDCK1 pin supplies coil-induced pulses through the diode to increase the voltage. The
increased voltage is then supplied to the low-pass filter as the doubled voltage for VT.
In the following example, pin P8-2, composed of pins 60, controls the turning the divided resistance on/off. When
the doubler is on, the program outputs the I/O port “L” level to turn the resistance division on. When the doubler is
off, the output is set to “HZ” (input setting) to disconnect the resistance division. Alternately, you can use the GND
rather than the 60-pin connection. However, when the GND connection is used, the current from the VDD power
supply is always consumed through the coil and the divided resistance in the doubler off state. This way, this control
function prevents the current from being consumed in the doubler system circuit when the doubler is off. Note that
this control is unnecessary and the GND connection may be used instead, when the power supply used turns off in the
tuner off state or when it doesn’t matter if the consumption current is increased in the system.
DC-DC converter voltage for VT
VDB
～
Power
supply
100uH
58 VDET
100Ω
59
Note
（VDD)
0.75V
+
Note
0.1uF
+
220kΩ
VLCD
DDCK1
DC-DC converter clock for VT
60
10uF
(1)
39kΩ
～
P8-2(ON:"L"output, OFF:HZ)
Example of internal DC-DC transistor doubler circuit
Note:
Use the low-VF shot key diode for the diode shown above.
Recommended diode: 1SS357
Note:
Determine the doubler coil constant depending on the DC-DC converter clock frequency and
the doubler current capacity.
Note:
Connect as required, when the output resistance 100 Ω of the DDCK1 pin shown above or the
clock output affects the tuner characteristics.
Note:
It doesn’t matter if a zener diode of 5.5 V or below is used as a substitute for the clamp circuit
(VDET). Using the zener diode eliminates the need to use the VDET and doubler on/off control
pins.
Note:
When the clamp circuit is used, operation is stopped if the doubled voltatge exceeds the
specified level. If the doubled voltage is supplied exceeding the specified voltage while the
voltage of DC-DC converter for VT is supplied, the doubler function operates intermittently and
may affect the tuner characteristics. To prevent this, it is recommended that doubler and
low-pass filter load capacities that will not exceed the detection voltage be determined during
tuner operation.
Note:
The N-ch transistor buffer gate signal for the DDCK1 pin uses the VLCD (3 V) power supply.
This allows stable doubler operation, even if the VDD power supply is reduced.
Note:
When this product is used as shown above, design the tuner circuit to widen the variable range
of the tuning voltage (VT).
Note:
The filter circuit constants shown above are for reference only. Examine and design the actual
circuits according to your desired characteristics.
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TC9349AFG
Example of using the DDCK2 external doubler transistor
The DDCK2 pin outputs the DC-DC converter clock in the CMOS type. The external transistor is used to increase
the voltage like the DDCK1 pin. The doubled voltage can be set freely by using the external transistor. When the
DDCK2 pin is used, set the POL bit to “1”.
Shown below is an example of a DC-DC converter circuit using the DDCK2 pin. Determine the R1/R2 resistance
according to your desired doubled voltage. The P8-0 pin control is the same as for the DDCK1 pin.
Voltage
of DC-DC converter for VT
VT用DC-DCコンバータ電圧
Note
注
0.01uF
Power電源
supply
電源
DD)
（(V
VDD)
100uH
VLCD
VLCD
～ DDCK2
57
VT用DC-DCコンバータクロック
Clock
of DC-DC converter for VT
4.7kΩ
58 VDET
+
-
59
+
-
0.1uF
60
10uF
(2)
R1
0.75V
VDB
VDB
R2
～
P8-2 (ON: "L" output,
OFF: HZ)
P8-2(ON:"L"出力
、OFF:HZ)
外部DC-DCトランジスタ昇圧回路例
Example of external DC-DC transistor doubler circuit
Note:
Determine the doubler coil constant depending on the DC-DC converter clock frequency and
the doubler current capacity.
Note:
It doesn’t matter if a zener diode is used as a substitute for the clamp circuit (VDET). Using the
zener diode eliminates the need to use the VDET and doubler on/off control pins (P8-2).
Note:
Add the charge up capacitor for the base input of the external transistor when the doubler
capacity is insufficient.
Note:
When the doubler function is turned off by using pin P8-2, turn it off when the voltage of the
DC-DC converter for VT has decreased sufficiently. A high voltage is applied to pin P8-2, and
this may cause damage.
Note:
The prebuffer power supply for the DDCK2 pin output uses a VLCD (3 V) pin power supply,
allowing stable doubler operation, even if the VDD power supply is reduced. Note that the VDD
power supply level is outputted as the “H” level of the DDCK2 pin output.
Note:
The filter circuit constants shown above are for reference only. Examine and design actual
circuits according to your desired characteristics.
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3. Configuration of DC-DC Converter for VT
P9-2出力データ
P9-2
output data
DDCK2
75kHz
DC-DC
DC-DCコンバータクロック
converter clock
POL
57
DDCK ENA・DDCK SEL
VDB
VDB
VDET ENA
58 VDET
+
-
PCTRin(P3-3)
Selector
セレクタ
VLCD
VLCD
～
カウンタ
Counter
fXT2(高速発振器)
fXT2
(high-speed oscillator)
カウンタ
Counter
OSCin(fosc)
DD0～ DD3
0.75V
1.00V
VDET ENA
VDET SEL
V
LCD
VLCD
DDCK ENA・DDCK SEL
59
DDCK1
POL
～
P8-1
output data
P8-1出力データ
Note: Comparison voltage for the doubler detection voltage (VDET) is the divided voltage of the VEE constant
voltage (1.5 V) pin voltage.
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TC9349AFG
Electronic Volume
This product incorporates 2-channel 32-step (0 to −78 dB, −∞ dB) electronic volume. This allows digitization of volume
control of headphone amplifier and reduction of parts.
The electronic volume pins are also used as I/O port 5 and I/O port pin P4-3. Channels can be switched between channels
1 and 2, which support monaural and stereo sound. The attenuation of the electronic volume is in –2 db steps within the
range of –0 to –40 db and in –4 db steps in a range of –40 db to –78 db.
1. Electronic Volume Data Port and Control Port
φL15(2)
Y1
Y2
VR0
VR1
Y4
Y8
VR2
VR3
φL15(3)
Y1
Y2
VR4
*
Y4
Y8
*
*
Electronic
volume data
電子ボリュームデータ
STEP
Attenua減衰量
tion
-∞dB
VR4
VR3
VR2
VR1
VR0
1
*
*
*
*
*
0
0
0
0
0
0
2
0
0
0
0
0
1
-78dB
3
0
0
0
0
1
0
-74dB
4
0
0
0
0
1
1
-70dB
5
0
0
0
1
0
0
-66dB
6
0
0
0
1
0
1
-62dB
7
0
0
0
1
1
0
-58dB
8
0
0
0
1
1
1
-54dB
1
-∞dB
9
0
0
1
0
0
0
-50dB
10
0
0
1
0
0
1
-46dB
11
0
0
1
0
1
0
-42dB
12
0
0
1
0
1
1
-40dB
13
0
0
1
1
0
0
-38dB
14
0
0
1
1
0
1
-36dB
15
0
0
1
1
1
0
-34dB
16
0
0
1
1
1
1
-32dB
17
0
1
0
0
0
0
-30dB
18
0
1
0
0
0
1
-28dB
19
0
1
0
0
1
0
-26dB
20
0
1
0
0
1
1
-24dB
21
0
1
0
1
0
0
-22dB
22
0
1
0
1
0
1
-20dB
23
0
1
0
1
1
0
-18dB
24
0
1
0
1
1
1
-16dB
25
0
1
1
0
0
0
-14dB
26
0
1
1
0
0
1
-12dB
27
0
1
1
0
1
0
-10dB
28
0
1
1
0
1
1
-8dB
29
0
1
1
1
0
0
-6dB
30
0
1
1
1
0
1
-4dB
31
0
1
1
1
1
0
-2dB
32
0
1
1
1
1
1
-0dB
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TC9349AFG
Electronic
volume control
電子ボリュームコントロール
φL15(4)
Y1
Y2
VR
CH1
VR
CH2
Y4
Y8
VR
-∞dB
MUTE
--∞dBビット
∞ dB bit
0: Normal operation (Electronic volume data attenuation)
0： 通常動作（ 電子ボリュームデータ減衰量）
1:1：--∞dB(ミュート)
∞ dB (Mute)
0:禁止
1:許可
0: prohibition
Permission
of - ∞ dB bit
MUTEビットによる-∞dBビット制御許可
control by the MUTE bit
1: Enabled
Electronic
volume pin setting
電子ボリューム端子設定
CH1
CH2
0
0
1
0
0
1
1
1
P4-3/
VRout1
P5-0/
VRin1
P5-1/
VRcom
P5-2/
VRin2
P5-3/
VRout2
I/Oポート
I/O port
電子ボリューム
Electronic
volume
I/Oポート
I/O port
I/Oポート
I/O port
電子ボリューム
Electronic
volume
電子ボリューム
Electronic
volume
The electronic volume pins are also used as port 5 and port P4-3 pins.
These pins are switched to electronic volume pins by using the VR CH1 and VR CH2 bits. Set this bit to “1” to use the
pin as an electronic volume pin. The electronic volume has two channels. Channel 1 (VR CH1 bit) and Channel 2 (VR CH2
bit); corresponding to VRout1/VRin1 and VRout2/VRin2 pins respectively, and the channels are individually adjustable.
The electronic volume attenuation is set by the electronic volume data, which has 5 bits. Setting the most significant bit
updates the lower 4 bits of the electronic volume data, meaning the most significant bit must be accessed; even if only the
lower bits are changed.
The volume can be muted only by setting the −∞dB bit. When this bit is set to −∞dB, the electronic volume data will be
retained, and the previous attenuation recovered when −∞dB is released again. Note that the −∞dB state obtained by setting
all the electronic volume data to “0” is the same operation as the state obtained by the −∞dB bit setting.
The electronic volume can also be set to −∞dB, depending on changes in the I/O port input. When there are changes in
the inputs of the I/O port that has been enabled to break and the MUTE bit is set to “1”, the volume will be in muted
(−∞dB) state. This is used for quick muting, for example, when band switching. This setting is enabled be setting the VR
MUTE bit to “1”. This is set by the internal MUTE bit, it is also effective to set the MUTE/P9-1 pin as the I/O port.
(→ Refer to the sections on MUTE output.)
The electronic volume control port is assigned to data port 5, and is accessed by using the OUT1 instruction with [CN
= 4H] specified in the operand. The electronic volume control port is reset to “0” after a system reset.
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2. Electronic Volume Configuration and Circuit Example
The electronic volume is configured by connecting the tuner and headphone amplifier as shown below.
～
44
チューナ
Tuner
～
1uF
R channel
output
Rチャネル出力
45
VRcom
1uF
～
～
46
47
R channel input
Rチャネル入力
1uF
L channel input
Lチャネル入力
48
リファレンス出力
Reference output
VRin1
ボリュームデータ
Lチャネル出力
L channel
output
VRout1
Volume data
1uF
VRin2
VRout2
～
～
Headphone amplifier
ヘッドホンアンプ
Example of electronic volume connection circuit
電子ボリューム接続回路例
The electronic volume reference voltage (VRcom) is usually connected to the reference output pin of the headphone
amplifier. When the reference output pin is not available, connect this potential to the GND level or the VEE pin (1.5 V
constant voltage). If the reference voltage (VRcom) is connected to GND, the distortion factor becomes 0.1% or below
when the input level (VRin) is 0.2 Vp-p or below. Caution must be taken as the distortion will be worse when this input
level is exceeded.
Note: The circuit shown above is for reference only. Examine and design actual circuits according to your
desired characteristics.
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3. Electronic Volume Configuration
The electronic volume is composed of a decoder, analog switches and resistors and the control circuit. The decoder,
analog switches and resistors are powered by the VLCD pin (3 V) power supply, which allows stable operation, even if the
VDD pin power supply fluctuates.
～
VRout1 44
VRin1
45
VVLCD
LCD
MUTE
32
VR MUTE
-∞dB
31
30
30kΩ
デコーダ
Decoder
1
0
VRcom 46
1
VR1
VR2
VR3
Volume data
ボリュームデータ
VR0
VR4
30kΩ
30
31
32
VRin2
47
VRout2 48
～
Note: The analog circuit in the electronic volume circuit is powered by the VLCD pin (3 V) power supply.
Therefore, up to 3 V can be inputted to VRin1/2. The logic section is powered by the VCPU pin power
supply.
Note: Volume switching by the zero cross detection is unavailable, hence noise may occur when the
attenuation is switched.
Note: The VRin1/2 input total resistance is 30 kΩ (typ.).
Note: The electronic volume distortion factor is 0.05% at the typical and 0.1% at the maximum (with VRin = 0.4
Vp-p input).
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IF Counter
This is a 20-bit general-purpose counter that counts the intermediate frequency (IF) of FM or AM during auto tuning and
can be used to detect auto stop signals. It can also measure the VCO of the analog tuner and detect the received frequency.
4. IF Counter Control Ports and Data Ports
IF counter control 1
φL16(0)
Y1
Y2
Y4
Y8
NC
IFin
Prescaller
IN
0
Setting of OSCin pre-scaler input to IF counter
0: IFin pin input setting
1: OSCin pin input setting
0: Input port (IN) setting
1: IF input setting
Selection between IF input
and input port
Setting of IF input nose cancel circuit
IF input operating frequency range
0.35 MHz to 12 MHz
0: Invalid
1: Valid (Noise cancel operation)
0.03 MHz to 1 MHz
Note: When the input port setting is selected, frequency detection can be carried out by CMOS input to the IF
counter.
Note: When the IF input setting is selected, the IF input amplifier turns off when in the PLL off mode. To use
the IF counter in the PLL off mode, select the input port setting (CMOS input).
Note: When the counter input is set to the prescaler input, the 1/15･16 prescaler is fixed to 16 frequency
divisions in the pulse swallow method and this frequency is inputted to the IF counter.
Note: For the input frequency range when the prescaler input setting is selected, refer to the section on
Programmable counter.
Note: Set the Y8 bit of the IF control 1 port (φL16 (0)) to “0”.
IF counter control 2
Y1
φL16(1)
Y2
STA/ STP MANUAL
Y4
Y8
G0
G1
Selection of gate time for frequency measurement
(Measurement time)
G1
G0
Gate time
0
0
1 ms
0
1
4 ms
1
0
16 ms
1
1
64 ms
Selection of automatic or manual frequency measurement
0: Auto mode (Take measurements during the gate time listed above)
1: Manual mode (Start and stop measurements according to the
STA/ STP bit.)
IF counter start/stop control bit
0: Counter stop
1: Counter start
φL16(F)
φΚ11(F)
Y1
Y2
Y4
Y8
TA0
TA1
TA2
TA3
PLL amplifier setting register
Set all “1” (FH)
Note: In the PLL amplifier setting register, the TA0 and TA1 bits are used for setting the OSCin input amplifier,
and the TA2 and TA3 bits are used for setting the IFin input amplifier.
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IF monitor
φK17
Y1
Y2
Y4
Y8
BUSY
MANUAL
OVER
0
φK12
20
<
=2 −1
20
>
= 2 (overflow state)
Overflow detection
0: IF counter measured value
1: IF counter measured value
Operation mode
0: IF counter automatic mode
1: IF counter manual mode
Operation monitor
0: IF counter measurement finished
1: IF counter measuring
φK13
φK14
φK15
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10 F11
0
Y8
Y1
φK16
Y2
Y4
Y8
F12 F13 F14 F15
Y1
Y2
Y4
Y8
F16 F17 F18 F19
219
2
LSB
IF counter data
MSB
The IF counter calculates the IF signals usually from the tuner and detects the auto stop signal. When the IFin bit is set to
“1”, the IFin input amplifier will operate and the IF counter will be enabled. The gain of the input amplifier can be
changed by the amplifier setting register port (φL16 (F), φK11 (F)). Set this register to all “1”. In the PLL off mode, this
amplifier is disabled and the IFin input becomes high impedance.
The IF input frequency range varies depending on the NC bit. When the NC bit is set to “1”, the internal noise cancel
circuit operates. When the NC bit is “0”, the frequency range is 0.35 to 12 MHz. When the NC bit is “1”, the noise cancel
circuit operates and the frequency range is 0.03 to 1 MHz. Set this bit depending on the IF frequency to be detected.
The IF counter has two counting methods; namely the automatic and manual IF counter modes respectively. Counting is
carried out using the following methods:
(1)
Automatic IF counter mode
To select the automatic mode for the IF counter, set the MANUAL bit to “0”, and specify the gate time depending
on the frequency band to be measured. When the STA/ STP bit is set to “1”, the IF counter will start operation, the
clock will be inputted during the specified gate time, the number of these input pulses will be counted, and the
counter will stop the operation. Whether or not the IF counter has finished counting can be checked by referring to
20
the BUSY bit. The OVER bit becomes “1” when there is a pulse input a measured value of 2 or over.
The frequency being inputted can be measured by checking that the BUSY and OVER bits are set to”0” and
loading the IF data of F0 to F19.
(2)
Manual IF counter mode
Use this mode when the frequency is measured by controlling the gate time using the internal time base (for
example, 10 Hz). Set the MANUAL bit to “1” to activate the manual mode. At this time, the gate time setting reverts
to “don’t care” state. Counting starts by setting the STA/ STP bit to “1”. By setting the STA/ STP bit to “0”,
counting is finished and the data is loaded in binary format.
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5. IF Counter Configuration
The IF counter is composed of an input amplifier, a gate time control circuit and a 20-bit binary counter. The OSCin
prescaler clock can be inputted as the IF counter input.
TA2/3
IFin
0.01 µF
IFin
Prescaler IN
F0~F19
Noise
Cancel
49
OVER
20-bit binary counter
OVER
Gate
NC
STA/STP
VPLL
1 kHz
50
Gate time
control circuit
Manual
G0
G1
PSC
OSCin
0.01 µF
Amplifi
1/15･16
51
To programmable counter
HF
TA0/1
Prescaler
IN
Note: All the binary counters of the IF counter operate at the rising edge.
Note: When the OSCin prescaler clock is counted by the IF counter, 1/15･16 is fixed to the 1/16 frequency
division by setting the PLL mode to HF mode. The clock is directly inputted when in LF mode.
Note: The IF counter input amplifier, the OSCin input amplifier and the programmable counter are powered by
the VPLL pin power supply. This power supply level can be supplied regardless of the VDD/VCPU pin
power supply level. In PLL off mode, the VPLL pin power supply can be turned off. The IF counter control
register and the IF counter power supply use the VCPU pin power supply. Therefore, the contents of the
register will be retained after the VPLL pin power supply is turned off.
Note: The IFin pin has a built-in amplifier that allows small-amplitude operation by linking to the capacitor.
PLL off mode, the IFin input becomes high impedance.
In
IF counter input
“1”
Data set to STA/ STP bit
BUSY bit
1 kHz
Gate
Binary counter input
Example of operation timing in automatic IF counter mode
Note: The IF counter ues the 1 kHz clock. There is a delay of up to 1 ms from the time when the start
instruction is executed to the time when the gate opens.
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Test Port
This is the internal port used to test the device functions. These ports are assigned to data port 7 and can be accessed by
using the OUT1 instruction with [CN = 6H] specified in the operand. Set all to “0” in the normal program.
φL16(2)
φL16(3)
Y1
Y2
Y4
Y8
Y1
#0
#1
#2
#3
#4
Y2
Y4
Y8
Test port
Setting the following data to test ports #3 to #0 enables various signals to be output from the MUTE pin.
MUTE pin output
0
0
0
0
0
MUTE output
0
0
0
1
1
Programmable counter
frequency
0
0
1
0
2
Reference frequency
0
0
1
1
3
2 Hz
0
1
0
0
4
~
Data
~
#0
~
#1
~
#2
~
#3
1
1
1
1
F
Prohibition
Note: The MUTE pin is also used for pin P9-1. This pin must be set as the MUTE pin when you need signals to
be output from the MUTE pin.
Application to Emulator Chip
When the RESET pin is at the “L” level and pulses are inputted to the TEST pin, various kinds of test modes will be
activated and the device will operate as an emulator chip. Three types of test modes are available, and the software
development tool can be configured by using three devices.
You can confirm the radio operation while developing software by connecting this software development tool to the tuner
IC.
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Absolute Maximum Rating (Ta = 25°C)
Characteristics
Supply voltage
(Note 1)
Symbol
Rating
Unit
VDD
−0.3 ~ 4.0
V
Output withstand voltage 1 (Note 2)
VO1
(*)
−0.3 ~ VDB + 0.3
V
Output withstand voltage 2
VO2
(*)
−0.3 ~ 6.0
V
(Note 2)
Input voltage 1
(Note3)
VIN1
(*)
−0.3 ~ VLCD + 0.3
V
Input voltage 2
(Note3)
VIN2
(*)
−0.3 ~ VCPU + 0.3
V
Input voltage 3
(Note3)
VIN3
(*)
−0.3 ~ 6.0
V
Input voltage 4
(Note3)
VIN4
(*)
−0.3 ~ VPLL + 0.3
V
Input voltage 5
(Note3)
VIN5
(*)
−0.3 ~ VDD + 0.3
V
Input voltage 6
(Note3)
VIN6
(*)
−0.3 ~ VDB + 0.3
V
Power dissipation
PD
100
mW
Operating temperature
Topr
−10 ~ 60
°C
Storage temperature
Tstg
−65 ~ 150
°C
Note 1:
The supply voltage (VDD) indicates the maximum rating of five pins, VDD, VCPU, VDB, VPLL and VLCD.
The relationship of the potentials is as follows: VDD ≤ VLCD, VDD ≤ VDB, VDD ≤ VCPU, VCPU ≤ VLCD
Note 2:
Each output voltage corresponds to the following pin:
VO1: I/O port 6 pin, VO2: DDCK1, Tout, I/O port 8 pin
Note 3:
Each input voltage corresponds to the following pin:
VIN1: All I/O port pins except for those listed below
VIN2: RESET pin
VIN3: I/O port 8 pin, P9-0 pin
VIN4: OSCin and IFin pins
VIN5: Xin1 pin
VIN6: I/O port 6 and Tin pins
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Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = VPLL = 1.5 V, VDB
= VCPU =3.0 V)
Characteristics
Operating supply voltage range
(Note 1)
Memory retention voltage range
Operating supply current
Symbol
Test
Circuit
VDD
⎯
(VDD)
VCPU
⎯
VPLL
⎯
VHD
Test Condition
Min
Typ.
Max
(*)
0.9
~
1.8
(VCPU)
(*)
1.2
~
3.6
(VPLL) PLL operation
(*)
0.9
~
1.8
⎯
(VCPU) Backup mode
(*)
0.75
~
3.6
IDD1
⎯
PLL operation, OSCin = 30
MHz
⎯
1.0
1.5
IDD2
⎯
During operation of CPU only
(PLL off and LCD driver
operating)
⎯
150
300
IDD3
⎯
In the hard wait mode
(Crystal oscillation only)
⎯
120
⎯
IDD4
⎯
In the soft wait mode
(CPU intermittent operation
only)
⎯
140
⎯
IHD1
⎯
(VDD, VPLL)
When the CKSTP instruction is
executed
⎯
0.1
10
⎯
(VCPU) VCPU = 1.2 ~ 3.6 V,
When the CKSTP instruction is
executed (Power supply
detectin is set to OFF),
VDD off (Power supply detectin
is set to ON)
⎯
0.01
0.5
Unit
V
mA
(Note 2)
Memory retention current
IHD2
µA
Note 1:
Use supply voltage in the range of VDD ≤ VLCD, VDD ≤ VDB, VDD ≤ VCPU and VCPU ≤ VLCD.
Note 2:
The operating supply current is the total current of the VDD, VCPU and VPLL pin power supplies.
Crystal Oscillator (Xin1, Xout1)
Symbol
Test
Circuit
Crystal oscillation frequency
fXT1
⎯
(Xin1, Xout1)
Crystal oscillation start time
tst1
⎯
(Xin1, Xout1) fXT1 = 75 kHz
Xin1 amplifier feedback resistance
RfXT1
⎯
(Xin1 - Xout1)
Xout1 output resistance
ROUT1
⎯
(Xout1)
Characteristics
Test Condition
(*)
Min
Typ.
Max
Unit
⎯
⎯
75
⎯
kHz
⎯
1.0
s
⎯
20
⎯
MΩ
50
100
200
kΩ
Min
Typ.
Max
Unit
300
⎯
600
kHz
High-speed Oscillator (Xin2, Xout2)
Symbol
Test
Circuit
High-speed oscillation frequency
range
fXT2
⎯
(Xin2, Xout2)
High-speed oscillation start time
tst2
⎯
(Xin2, Xout2)
fXT2 = 300 ~ 600 kHz
⎯
⎯
100
ms
Xin2 amplifier feedback resistance
RfXT2
⎯
(Xin2 - Xout2)
⎯
1
⎯
MΩ
Xout2 output resistance
ROUT2
⎯
(Xout2)
1
2
4
kΩ
IXT2
⎯
(Xin2 - Xout2)
⎯
50
⎯
µA
Characteristics
Oscillation operating current (Note 3)
Test Condition
(*)
Note 3: This value increases when high-speed oscillator is used.
*: Guaranteed when VDD = VPLL = 0.9 - 1.8 V, VCPU = 1.2 - 3.6 V, and Ta = −10 to 60°C.
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Constant Voltage Output (VEE), Voltage Doubled Output (VLCD)
Characteristics
Doubled output
Symbol
Test
Circuit
VDB1
⎯
Min
Typ.
Max
(VDB) GND reference
Clamp off, Charge pump
voltage
⎯
VDD ×
2
⎯
VDB2
(VDB) GND reference
Clamp voltage = 2.0 V setting
⎯
2.0
⎯
VDB3
(VDB) GND reference
Clamp voltage = 2.5 V setting
⎯
2.5
⎯
VDB4
(VDB) GND reference
Clamp voltage = 3.0 V setting
⎯
3.0
⎯
(VLCD) GND reference
⎯
VEE ×
2
⎯
(VDB) When the charge pump
pressure is increased
⎯
⎯
0.05
VLCD
Clamp doubled voltage setting error
⎯
Test Condition
VEE = 1.5 V
∆VDB
VEE
⎯
(VEE) GND reference
V
V
(VDB) When the switching
regulator pressure is increased
VEE = 1.5 V
Constant voltage
Unit
(*)
⎯
⎯
±0.05
1.46
1.50
1.54
V
Unit
Programmable Counter, IF Counter Operating Frequency Range
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
HF mode
f HF
⎯
(OSCin) VIN = 0.1 ~ 0.6 Vp-p (*)
1.0
~
30
LF mode
f LF
⎯
(OSCin) VIN = 0.1 ~ 0.6 Vp-p (*)
0.5
~
4
(*)
0.35
~
12
(*)
0.03
~
1
Characteristics
Operating frequency
range
Input amplitude range
IFin1
f IF1
⎯
(IFin) VIN = 0.1 ~ 0.6 Vp-p
NC = 0 setting
IFin2
f IF2
⎯
(IFin) VIN = 0.1 ~ 0.6 Vp-p
NC = 1 setting
HF mode
VHF
⎯
(OSCin) fIN = 1.0 ~ 30 MHz (*)
0.1
~
0.6
LF mode
VLF
⎯
(OSCin) fIN = 0.5 ~ 4 MHz
(*)
0.1
~
0.6
(*)
0.1
~
0.6
(*)
0.1
~
0.6
MHz
IFin1
VIF1
⎯
(IFin) fIN = 0.35 ~ 12 MHz
NC = 0 setting
IFin2
VIF2
⎯
(IFin) fIN = 0.03 ~ 1 MHz
NC = 1 setting
RfIN1
⎯
(OSCin)
250
500
1000
kΩ
RfIN2
⎯
(IFin)
250
500
1000
kΩ
Input amplifier feedback resistance
Vp-p
*: Guaranteed when VDD = VPLL = 0.9 - 1.8 V, VCPU = 1.2 - 3.6 V, and Ta = −10 to 60°C.
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I/O Ports 1 to 6 (P1-0 to P16-3) , Serial Interface (SCK1/2, RX1/2, SDIO1/2, TX1/2) (Note 4)
Characteristics
Symbol
Test
Circuit
IOH1
⎯
IOH1L
Min
Typ.
Max
VDD = 0.9 V, VLCD = 3.0 V,
VOH = VDD − 0.2 V
(except for I/O ports 6,8 and P9-0)
−0.4
−0.8
⎯
⎯
VDD = 0.9 V, VLCD = 3.0 V,
VOH = VDD − 0.2 V
(except for I/O ports 6,8 and P9-0)
⎯
−0.5
⎯
IOL1
⎯
VDD = 0.9 ~ 1.8 V,
VLCD = 3.0 V, VOL = 0.2 V
(except for I/O port 8 and P9-0)
0.4
0.8
⎯
IOL2
⎯
VDD = 0.9 ~ 1.8 V,
VLCD = 3.0 V, VOL = 0.2 V
(P8-0 to P8-3)
2
4
⎯
IOL3
⎯
VDD = 0.9 ~ 1.8 V,
VLCD = 3.0 V, VOL = 0.2 V
(P9-0)
⎯
20
⎯
⎯
VIH = VDD, VIL = 0 V
(except for I/O ports 6,8 and P9-0)
⎯
VIH = VDB, VIL = 0 V
(P6-0 to P6-3)
⎯
⎯
±1.0
⎯
VIH = 5.5 V, VIL = 0 V
(P8-0 to P8-3, P9-0)
⎯
(except for I/O ports 6,8 and P9-0)
VDD
× 0.8
~
VLCD
⎯
(P6-0 to P6-3)
VDD
× 0.8
~
VDB
⎯
(P8-0 to P8-3, P9-0)
VDD
× 0.8
~
5.5
VIL
⎯
⎯
0
~
VDD
× 0.2
Input pull-up/pull-down resistance
R IN1
⎯
When P3-0 to P3-3 are set to
pull-down or pull-up
25
50
100
kΩ
Input pull-down resistance
R IN2
⎯
(TEST) when RESET = “L”
⎯
10
⎯
kΩ
SCK input frequency
fSIO
⎯
When SCK1/SCK2 are set to serial
clock input
⎯
⎯
200
kHz
Unit
“H” level
Output current
“L” level
Input leak current
ILI
“H” level
VIH
Test Condition
Unit
mA
µA
V
Input voltage
“L” level
Note 4: The electrical characteristics in serial interface conditions are the same as for the I/O ports.
LCD Driver Output (COM1 to COM4 , S1 to S18)
Symbol
Test
Circuit
“H” level
IOH4
⎯
“L” level
IOL4
1/3 VLCD level
Characteristics
Min
Typ.
Max
VLCD = 3.0 V,
VOH = VLCD − 0.2 V
⎯
−0.2
⎯
⎯
VLCD = 3.0 V, VOL = 0.2 V
⎯
0.5
⎯
VBS2
⎯
VLCD = 3 V, no load,
when the 1/3 bias type selected
0.85
1.00
1.15
1/2 VLCD level
VBS3
⎯
VLCD = 3 V, VEE = 1.5 V, no load, when
the 1/2 bias selected
1.35
1.5
1.65
2/3 VLCD level
VBS4
⎯
VLCD = 3 V, no load,
when the 1/3 bias selected
1.85
2.00
2.15
ILCD2
⎯
No load,
when the 1/2 bias selected
⎯
5
⎯
ILCD3
⎯
No load,
when the 1/3 bias selected
⎯
100
⎯
Output current
Bias voltage
LCD driver operating current
(Note 5)
Test Condition
mA
V
µA
Note 5: This value increases when the LCD driver circuit is used.
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Electronic Volume (VRout1, VRin1, VRcom, VRin2, VRout2)
Symbol
Test
Circuit
Volume resistance
RVR
⎯
Analog switch ON resistance
RON
⎯
Attenuation error
∆ATT
⎯
Symbol
Test
Circuit
Analog input voltage range
VAD
⎯
Resolution
VRES
⎯
⎯
Total conversion error
⎯
⎯
⎯
Analog input leak
ILI
⎯
Characteristics
Test Condition
Min
Typ.
Max
Unit
IN ~ GND resistor
15
30
60
kΩ
Analog switch on resistor
⎯
500
800
Ω
⎯
⎯
0
±2.0
dB
Test Condition
Min
Typ.
Max
Unit
0
~
VDB
V
⎯
6
⎯
bit
⎯
±0.5
±1.0
LSB
⎯
⎯
±1.0
µA
Min
Typ.
Max
Unit
−0.8
⎯
A/D Converter (ADin1 to ADin4)
Characteristics
(ADin1 ~ ADin4)
VIH = VDB, VIL = 0 V
(ADin1 to ADin4)
Phase Comparator (DO1/OT1/P, DO2/OT2/N)
Characteristics
“H” level
Symbol
Test
Circuit
IOH5
⎯
VDB = 3.0 V,
VOH = VDB − 0.2 V
when the output resistance is
off
−0.4
IOL5
⎯
VDB = 3.0 V,
VOL = 0.2 V
when the output resistance is
off
0.4
0.8
⎯
ROUT1
⎯
(DO1, DO2)
⎯
5
⎯
ROUT2
⎯
(DO1, DO2)
⎯
50
⎯
ROUT3
⎯
(DO1, DO2)
⎯
100
⎯
⎯
(DO1, DO2) VDB = 3.0 V,
VTLH = 3.0 V, VTLL = 0 V
⎯
⎯
±100
Output current
“L” level
Output resistance
Tristate leak current
ITL
Test Condition
126
mA
kΩ
nA
2006-02-24
TC9349AFG
DC-DC Converter Voltage Doubler for VT (VDET, DDCK1, DDCK2)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Doubled voltage range
VOUT
⎯
⎯
0
~
5.5
V
Doubled voltage detection setting
error
∆VDET
⎯
(VDET) VEE = 1.5 V
⎯
⎯
±0.05
V
IDET
⎯
(VDET)
⎯
10
⎯
µA
IOH1
⎯
(DDCK2) VOL = 0.2 V
when DDCK2 is selected
−0.4
−0.8
⎯
IOL1
⎯
(DDCK2) VOL = 0.2 V,
when DDCK1 is selected
0.4
0.8
⎯
IOL2
⎯
(DDCK1) VOL = 0.2 V,
when DDCK1 is selected
2
4
⎯
IOFF
⎯
(DDCK1) VIH = 5.5 V,
when DDCK1 is selected
⎯
⎯
±1.0
µA
Min
Typ.
Max
Unit
20
⎯
mA
Characteristics
Detection operating current (Note 6)
“H” level output current
“L” level output current
Output off leak current
Note 6:
mA
This value increases when the tdoubled voltage detection circuit is used.
Transistor for Low-pass Filter (Tout, Tin)
Symbol
Test
Circuit
Test Condition
“L” level output current
IOL3
⎯
(Tout) VOL = 0.2 V, Tin = 1.5 V
Output off leak current
IOFF
⎯
(Tout) VOH = 5.5 V, Tin = 0 V
⎯
⎯
±1.0
µA
ILI
⎯
(Tin) VOB = VIH = 3.6 V
VIL = 0 V
⎯
⎯
±1.0
µA
Characteristics
Symbol
Test
Circuit
Min
Typ.
Max
Unit
Input leak current
ILI
⎯
⎯
⎯
±1.0
µA
“H” level
VIH
⎯
⎯
VCPU
× 0.8
~
VCPU
“L” level
VIL
⎯
⎯
0
~
VCPU
× 0.2
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
∆VBL
⎯
⎯
⎯
±0.03
V
ILI
⎯
⎯
20
⎯
µA
Characteristics
Input leak current
Reset Signal Input ( RESET )
Test Condition
VIH = VCPU, VIL = 0 V
Input voltage
V
Reduced Voltage Detection Circuit
Characteristics
Reduced voltage detection setting
error
Reduced voltage detection operating
current
(Note 7)
Note 7:
(VDD) VEE = 1.5 V
⎯
This value increases when the detection circuit is used.
127
2006-02-24
TC9349AFG
Package Dimensions
Weight: 0.32 g (standard)
128
2006-02-24
TC9349AFG
129
2006-02-24