INTEGRATED CIRCUITS DATA SHEET TDA9888TS; TDA9889TS DVB selective AGC amplifier Product specification Supersedes data of 2002 Oct 23 2004 Nov 02 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS • Tuner Automatic Gain Control (TAGC) detector for independent tuner gain control loop applications FEATURES • Applicable for terrestrial and cable TV reception • TAGC operating as peak-sync detector, fast reaction time due to additional speed-up detector • 70 dB variable gain wide-band Intermediate Frequency (IF) amplifier (AC-coupled) • TAGC switch for feed-through of TAGC signal from analog TV demodulator (e.g. TDA9886) in case of hybrid (analog and digital TV demodulation) application • Gain control via external control voltage (0 to 3 V) • 2 V (p-p) differential low IF (downconverted) output for direct Analog-to-Digital Converter (ADC) interfacing • Stabilizer circuit for ripple rejection and to achieve constant output signals • Digital Video Broadcast (DVB) downconversion with integrated selectivity (allows to use one SAW filter applications) • Electrostatic discharge (ESD) protection for all pins. • Integrated anti-aliasing tracking low-pass filter GENERAL DESCRIPTION • Fully integrated synthesizer controlled oscillator with excellent phase noise performance The TDA9888TS; TDA9889TS is an AGC amplifier circuit with integrated selectivity. The device provides downconversion and filtering without alignment for all DVB standards. The filtering considers the tough neighbouring channel conditions. • Synthesizer frequencies for a wide range of world wide DVB standards (for IF centre frequencies of 36, 44 and 57 MHz) with different channel bandwidths (6, 7 and 8 MHz) are possible; see Tables 1 and 2 • 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator ORDERING INFORMATION TYPE NUMBER TDA9888TS PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 5.3 mm TDA9889TS 2004 Nov 02 2 VERSION SOT338-1 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT VP supply voltage 4.5 5 5.5 V IP supply current 46 55 64 mA Vo(LIF)(p-p) typical low IF operating output voltage (peak-to-peak value) − 2 − V GIF(max) maximum conversion gain output peak-to-peak level to 85 input RMS level ratio 90 − dB GIF(cr) IF gain control range see Fig.3 60 70 − dB fosc synthesizer controlled oscillator frequencies see Tables 1 and 2 − 31 − MHz − 31.5 − MHz − 32 − MHz − 40 − MHz φN(synth) synthesizer phase noise performance note 1 MIN. − 53 − MHz at 1 kHz 89 99 − dBc at 10 kHz 89 97 − dBc 98 102 − dBc αLIF low IF band amplitude characteristic 0 dB at middle of band (standard independent) −0.9 − +0.9 dB αN−1 low-pass filter attenuation 8 MHz band; at 15.75 MHz 15 − − dB αN+1 suppression of IF input frequencies below wanted band at low IF output input frequency between 21 and 31 MHz; referenced to 36 MHz 30 − − dB C/N carrier-to-noise ratio at low IF at ∆f > 1 MHz; see Fig.5 112 116 − dBc/Hz PSRR power supply ripple rejection [residual ripple AM, modulation factor m at 2 V (p-p) low IF signal] fripple = 70 Hz; see Fig.7 − 1.4 − % at 100 kHz Note 1. Some parameters can be decreased at VP = 4.5 V. 2004 Nov 02 3 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS BLOCK DIAGRAM handbook, full pagewidth IF gain control input TAGC TADJ TAGCEXT 10 9 11 TUNER AGC IF1 IF2 S0 1 AGC 6 IF AGC INTERFACE 15 TDA9888TS TDA9889TS DOWNCONVERTER AND COMPLEX FILTERING 16 SYNTHESIZER AND REFERENCE GENERATION SUPPLY 8 LIF2 TRACKING LOW-PASS FILTER 7 LIF1 FILTER REFERENCE CONTROL 12 14 4 2 5 VP GND LFS REF LFLP Fig.1 Block diagram. 4 S2 3 LOGIC CONTROL 4 MHz crystal or external reference 2004 Nov 02 S1 13 MHC094 low IF output 2 V(p-p) differential Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS PINNING SYMBOL PIN DESCRIPTION S0 1 logic switch S0 input (frequency select) REF 2 4 MHz crystal or reference input S2 3 logic switch S2 input (AGC select) LFS 4 loop filter synthesizer PLL LFLP 5 loop filter low-pass control PLL AGC 6 AGC control voltage input LIF1 7 low IF differential output 1 LIF2 8 low IF differential output 2 TADJ 9 tuner AGC TakeOver Point (TOP) adjustment TAGC 10 tuner AGC output TAGCEXT 11 external tuner AGC voltage input VP 12 supply voltage (+5 V) S1 13 logic switch S1 input (frequency select) GND 14 ground supply IF1 15 IF differential input 1 IF2 16 IF differential input 2 handbook, halfpage S0 1 16 IF2 REF 2 15 IF1 S2 3 14 GND LFS 4 13 S1 TDA9888TS LFLP 5 TDA9889TS 12 VP AGC 6 11 TAGCEXT LIF1 7 10 TAGC LIF2 8 9 TADJ MHC093 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Tuner AGC Figure 1 shows the simplified block diagram of the device. The integrated circuit contains the following functional blocks: The tuner AGC is realized by a TakeOver Point (TOP) network and a peak-level detector. The threshold level of the peak detector can be adjusted by an external potentiometer connected to pin TADJ. For IF signals above this threshold the level detector provides a discharge current to pin TAGC. An additional current source is internally connected to this pin providing charge current to the external tuner AGC capacitor. For IF signals of 8 dB below the threshold voltage this current will be increased by a factor of approximately 40 for faster AGC reaction. The ratio of discharge to charge current is normally approximately 2000 and approximately 50 for fast mode. 1. Gain controlled IF amplifier 2. Tuner AGC 3. Reference generation 4. Synthesizer for downconversion 5. Downconversion and complex filtering 6. Tracking low-pass filter with reference control 7. Low IF differential output stage 8. Logic control For use of the device in different applications the charge current can be switched off, for hybrid applications the signal at pin TAGCEXT can be fed via a transmission gate to pin TAGC (TDA9888TS; TDA9889TS combined with analog IF), controlled by the 3-state input pin S2. With an activated transmission gate all internal currents are off. In the event that the tuner AGC is not needed (e.g. TAGC from channel decoder or from an analog IF in hybrid chassis), pin TADJ should be left open-circuit and therefore all internal AGC currents will be switched off. 9. Internal voltage stabilizer. Gain controlled IF amplifier The IF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. Total gain control range is 70 dB (typ.). The differential input impedance is typical 2 kΩ in parallel with 3 pF. 2004 Nov 02 5 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS Reference generation Tracking low-pass filter with reference control The 4 MHz crystal is the reference for the downconversion synthesizer and the filter synthesizer. The low-pass filter is controlled by a reference signal [generated by a frequency synthesizer and can be switched by the standard selection (S0 and S1)]. The downconverted DVB frequency and the frequency adjustment of the integrated filters are dependent on the precision of the reference signal at pin REF. An operation as crystal oscillator is possible as well as connecting this input via a serial capacitor to another low-ohmic reference frequency source. The tracking low-pass filter is designed as a Tschebyscheff filter to guarantee sufficient suppression for the neighbouring picture carrier. An all-pass filter corrects the characteristic to obtain a flat (equivalent ripple) group delay behaviour. The integrated divider-by-8 generates the internally needed 500 kHz reference frequency for the DVB synthesizer and the reference filter. Low IF differential output stage The output amplifier consists of two identical differential operational amplifiers with a high common mode (DC) rejection ratio, to provide a constant DC voltage at the output stage. The amplified Low IF (LIF) signal is available as a differential signal with an amplitude of 2 V (p-p) and DC level of 2 V (typ.) between the output terminals of both amplifiers. Synthesizer for downconversion The PLL synthesizer for downconversion consists of a Voltage Controlled Oscillator (VCO), a divider with a standard dependent divider factor, a frequency phase detector (constructed as a digital 3-state comparator) and a charge pump. Logic control The VCO operates as an integrated low radiation relaxation oscillator at double the conversion frequency. For downconversion the VCO frequency is divided-by-2 to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the VCO frequency. The logic control provides an easy selection of the most common standards for Europe, USA and Japan with the two switches S0 and S1 (frequency selection different for TDA9888TS and TDA9889TS) and controls all internal standard dependent stages. The five available tuner AGC modes can be set via the 3-state input pin S2 and RTOP connection (at pin TADJ). The frequency phase detector compares the down-divided oscillator signal with the 500 kHz reference frequency signal and controls, via the charge pump, the control voltage at the external loop filter connected to pin LFS, which is required to tune the VCO exactly to the wanted frequency. Internal voltage stabilizer The band gap circuit generates a voltage of approximately 2.4 V, independent of the supply voltage and the temperature. A voltage regulator circuit, controlled by this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. The divider, the frequency phase detector and the reference frequency divider are constructed in a low radiation technique to optimize the synthesizer spurious suppression in the downconverted output signal. Downconversion and complex filtering The gain controlled IF signal from the IF amplifier is fed to two identical linear mixers, operating in the ‘in phase’ and ‘quadrature’ mode in accordance to the 0 and 90 degree VCO signal from the synthesizer. With this, the downconverted DVB low IF signal is available as an I and Q signal in the frequency band from 1 to 9 MHz. These signals are fed to the complex filter section. As a result of adding both signals, the unwanted mirror signal will be attenuated (approximately 34 dB). The unwanted frequency components below 1 MHz are attenuated in a high-pass filter. This signal is then fed through a group-delay equalizer circuit. 2004 Nov 02 6 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MAX. UNIT − 5.5 V input voltage at pins 1 to 11, 13, 15 and 16 − VP V tsc short-circuit time to ground or VP − 10 s Tstg storage temperature −25 +150 °C Tamb ambient temperature −20 +70 °C Ves electrostatic handling voltage for all pins note 1 −200 +200 V note 2 −2500 +2500 V VP supply voltage Vi(n) IP = 64 mA; Tamb = 70 °C; maximum chip temperature of 125 °C; Rth(j-a) = maximum MIN. Notes 1. Machine model (class B; SNW-FQ-302B): discharging a 200 pF capacitor via a 0.75 µH inductance. 2. Human body model (class 2; SNW-FQ-302A): discharging a 100 pF capacitor via a 1.5 kΩ series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient 2004 Nov 02 CONDITIONS in free air 7 VALUE UNIT 136 K/W Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS CHARACTERISTICS VP = 5 V; Tamb = 25 °C; 8 MHz system; see Tables 1 or 2, CW test input signal is used for specification; Vi(IF)(rms) = 10 mV frequency fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1; gain controlled amplifier adjusted to low IF differential output of 2 V (p-p); measurements taken in test circuit of Fig.11 with external 4 MHz reference signal of 140 mV (RMS); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; pin VP VP supply voltage IP Ptot note 1 4.5 5 5.5 V supply current 46 55 64 mA total power dissipation − 275 352 mW 85 90 − dB IF amplifier; pins IF1 and IF2; differential GIF(max) maximum conversion gain GIF(min) minimum conversion gain output peak-to-peak level to input RMS level ratio − 20 23 dB GIF(cr) IF gain control range see Fig.3 60 70 − dB BIF(−3dB)(ll) lower limit −3 dB IF bandwidth note 2 − 15 − MHz BIF(−3dB)(ul) upper limit −3 dB IF bandwidth note 2 − 80 − MHz Ri(dif) differential input resistance note 2 − 2 − kΩ Ci(dif) differential input capacitance note 2 − 3 − pF VI DC input voltage − 1.9 − V Low IF output signal; pins LIF1 and LIF2; differential; see Fig.8 Vo(LIF)(p-p) typical low IF operating output voltage (peak-to-peak value) − 2 − V Vclip(u) upper clipping voltage level (single-ended) 2.9 − − V Vclip(l) lower clipping voltage level (single-ended) − − 0.6 V Ro(diff) output resistance (differential) − − 150 Ω VO DC output voltage − 2 − V Ibias(int) internal DC bias current for emitter-follower (single-ended) 0.8 1 − mA 2.5 − − mA note 2 Io(source)(max) maximum AC and DC output source current (single-ended) Io(sink)(max) maximum AC and DC output sink current (single-ended) note 3 0.6 − − mA ZL(diff) differential load impedance note 2 1.7 − − kΩ αLIF low IF band amplitude characteristic 0 dB at middle of band (standard independent) −0.9 − +0.9 dB td(g)(LIF) low IF band group delay ripple from 1 MHz to 2 MHz − − 150 ns from 2 MHz to end of band − − 100 ns 6 MHz band; at 11.75 MHz 15 − − dB 7 MHz band; at 13.75 MHz 15 − − dB 8 MHz band; at 15.75 MHz 15 − − dB any band; at 27 MHz 40 50 − dB αN−1 α27MHz 2004 Nov 02 low-pass filter attenuation low-pass filter attenuation 8 Philips Semiconductors Product specification DVB selective AGC amplifier SYMBOL PARAMETER TDA9888TS; TDA9889TS CONDITIONS MIN. TYP. MAX. UNIT αN+1 suppression of IF input frequencies below wanted band at low IF output input frequency between 21 and 31 MHz; referenced to 36 MHz 30 35 − dB C/N carrier-to-noise ratio at low IF at ∆f = 4.9 MHz; note 4a; see Fig.5 112 116 − dBc/Hz at ∆f = 4.9 MHz; note 4b; see Fig.5 90 100 − dBc/Hz αd3 intermodulation at fLIF1 = 4.1 MHz or fLIF2 = 5.9 MHz fIF1 = fosc + 4.7 MHz and fIF2 = fosc + 5.3 MHz; see Fig.6 35 − − dB αd2 in-band harmonics low IF = multiple of 1.31 MHz up to 7.86 MHz fIF1 = fosc + 1.31 MHz 40 − − dB αH(spur) in-band spurious elements (1 to 9 MHz) AC load: ZL(diff) > 1.7 kΩ 50 − − dB 50 − − dB fripple = 70 Hz; see Fig.7 − − 5 Hz fripple = 1 kHz; see Fig.7 − 25 35 Hz fripple = 10 kHz; see Fig.7 − 1400 2000 Hz fripple = 100 kHz; see Fig.7 − 2700 4000 Hz − 1.4 − % out-band spurious elements (>9 MHz) PSRR power supply ripple rejection [residual ripple FM, peak deviation ∆f at 2 V (p-p) low IF signal] power supply ripple rejection fripple = 70 Hz; see Fig.7 [residual ripple AM, modulation factor m at 2 V (p-p) low IF signal] IF AGC control; pin AGC Ii(sink)(max) maximum input sink current − − 2 µA Vi(max) maximum allowable input voltage − − VP V Gv gain control voltage range 0 − 3 V SAGC negative control steepness ∆GIF/∆Vcon − 45 − dB/V Gv = 0.8 to 2.2 V Tuner AGC; pin TAGC, operating as current output; see Figs 3 and 4 Vi(IF)(min)(p-p) minimum controlled IF input signal voltage between pins IF1 and IF2 (peak-to-peak value) RTOP = 22 kΩ; ITAGC(sink) = 100 µA − 81 84 dBµV Vi(IF)(max)(p-p) maximum controlled IF input signal voltage between pins IF1 and IF2 (peak-to-peak value) RTOP = 0 Ω; ITAGC(sink) = 100 µA 102 106 − dBµV Vi(IF)/∆T variation of AGC controlled IF input voltage with temperature RTOP = 8.2 kΩ; ITAGC(sink) = 100 µA − − 0.07 dB/K Isink sink current (tuner AGC discharge current) VTAGC = 1 V 400 500 600 µA 2004 Nov 02 9 Philips Semiconductors Product specification DVB selective AGC amplifier SYMBOL TDA9888TS; TDA9889TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT normal mode 0.21 0.27 0.33 µA Isource(2) source current (tuner AGC charge current) fast mode activated by internal level detector 8 10 12 µA Vsat(ul) upper limit saturation voltage VP − 0.3 − − V Vsat(ll) lower limit saturation voltage pin operating as current output − − 0.3 V αTH level loss threshold of internal detector for activating fast AGC 0 dB corresponds to RTOP alignment 6 8 10 dB tdet(off) fast AGC detection off time all signal events below αTH 40 60 80 ms Isource(1) External tuner AGC; electronic switch operation; pin TAGC connected to pin TAGCEXT Ron resistance between pins TAGC and TAGCEXT in operation − 900 1200 Ω Vop(I/O) I/O operating voltage range 0 − VP V Tuner AGC takeover point adjust and TAGC operating mode settings; pin TADJ; see Table 3 VRTOP alignment voltage RTOP at pin TADJ = 0 to 22 kΩ 0 − 2 V VTADJ voltage at pin TADJ pin open-circuit − 3.5 − V RTOP resistor connected between pin TADJ and GND for LOW: RTOP at pin TADJ − − 25 kΩ for HIGH: pin open-circuit 1 − − MΩ 1 − 3 V note 5 − 4 − MHz/V 9 − µA/rad Low-pass control PLL; pin LFLP VLFLP loop filter operating range KO VCO steepness: ∆fVCO/∆VLFS KD phase frequency detector steepness: ∆ILFLP/∆ϕFM − Rlf(int) internal loop filter resistor 3.75 4.7 5.65 kΩ Isink/source phase frequency detector I/O current − − 65 µA 1 − 3 V − 25 − MHz/V Synthesizer PLL; pin LFS VLFS loop filter operating range KO VCO steepness: ∆fVCO/∆VLFS KD phase frequency detector steepness: ∆ILFS/∆ϕFM − 16 − µA/rad Isink/source phase frequency detector I/O current − − 100 µA φN(synth) synthesizer phase noise performance at 1 kHz 89 99 − dBc/Hz at 10 kHz 89 97 − dBc/Hz at 100 kHz 98 102 − dBc/Hz at 1.4 MHz 115 119 − dBc/Hz note 5 αspur synthesizer spurious performance multiple of ∆f = 500 kHz 50 − − dBc Ileak(lf) loop filter leakage current synthesizer spurious performance > 50 dBc − − 10 nA 2004 Nov 02 10 Philips Semiconductors Product specification DVB selective AGC amplifier SYMBOL TDA9888TS; TDA9889TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Standard switch S0 and S1; pins S0 and S1; see Tables 1 or 2 Vi input voltage Vfr(S0,S1) free-running voltage at pin S0 or pin S1 Ri input resistance for LOW 0 − 2 V for HIGH 2.5 − VP V pin open-circuit; Ifr(S0,S1) < 0.1 µA − 3.5 − V − 37 − kΩ for LOW 0 − 0.8 V for MID 1.3 − 2 V for HIGH 2.5 − VP V pin open-circuit; Ifr(S2) < 0.1 µA − 1.65 − V − 25 − kΩ Standard switch S2; pin S2; see Table 3 Vi input voltage Vfr(S2) free-running voltage at pin S2 Ri input resistance Reference input; pin REF; note 6 VI DC input voltage 2.3 2.6 2.9 V Ri input resistance 1.5 2 2.5 kΩ Ci input capacitance − 2 − pF Rxtal resonance resistance of crystal operation as crystal oscillator − − 200 Ω Cx pull-up/down capacitance fref frequency of reference signal ∆fref tolerance of reference frequency Vref(p-p) amplitude of reference signal source (peak-to-peak value) Ro(ref) allowed output resistance of external reference source CK decoupling capacitance to external reference source 2004 Nov 02 note 7 depends on crystal type pF − 4 − MHz note 8 − − ±100 × 10−6 operation as input terminal 230 − 1100 mV − − 4.7 kΩ 22 100 − pF operation as input terminal 11 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS Notes 1. Some parameters can be decreased at VP = 4.5 V. 2. This parameter is not tested during production and is only given as application information. 3. For a higher AC load a resistor application is possible. 4. Measured without input signal but AGC adjusted corresponding to following input level a) 10 mV (RMS) b) 0.5 mV (RMS). 5. Calculation of the PLL loop filter by using following formulae, valid under the condition for the damping factor d ≥ 1.2 . KO 1 KO 1 BL –3 dB = ------- -------K D R LFS and d = --- R LFS ------- K D C LFS with the following parameters 2π n n 2 KO = VCO steepness (rad/V) or (2π Hz/V), KD = phase frequency detector steepness (µA/rad), RLFS = synthesizer loop filter serial resistor (Ω), CLFS = synthesizer loop filter serial capacitor (F), BL−3dB = loop filter bandwidth at −3 dB amplitude (Hz), d = damping factor n = divider factor; see Table 4. 6. The reference input at pin S2 is able to operate as a one-pin crystal oscillator as well as an input terminal with external reference signal, e.g. from the tuning system. 7. The value of Cx determines the accuracy of the resonance frequency of the crystal and depends on the crystal type. 8. The tolerance of the reference frequency determines the accuracy of the low IF. The tolerance of fosc is given by ∆f ref ∆f osc = ----------- f osc and the tolerance of fLIF is given by ∆fLIF = −∆fosc. f ref Table 1 Standard switch settings for TDA9889TS S1 S0 fIF(centre) (MHz) fosc (MHz) CHANNEL BANDWIDTH (MHz) REGION HIGH HIGH 36 31 8 Europe HIGH LOW 36 31.5 7 Europe LOW HIGH 44 40 6 USA LOW LOW 36 32 6 Europe 2004 Nov 02 12 Philips Semiconductors Product specification DVB selective AGC amplifier Table 2 TDA9888TS; TDA9889TS Standard switch settings for TDA9888TS S1 S0 fIF(centre) (MHz) fosc (MHz) CHANNEL BANDWIDTH (MHz) REGION HIGH HIGH 36 31 8 Europe HIGH LOW 36 31.5 7 Europe LOW HIGH 44 40 6 USA LOW LOW 57 53 6 Japan Table 3 AGC mode settings S2 RTOP LOW connected MID all charge and discharge currents enabled open-circuit LOW Table 4 all currents off; voltage from pin TAGCEXT switched to pin TAGC charge currents disabled; discharge current enabled HIGH MID/HIGH FUNCTION (PIN TADJ) all currents off; pin TAGC high-ohmic all currents off; voltage from pin TAGCEXT switched to pin TAGC Synthesizer PLL loop filter dimensions for different standards; see note 5 of Chapter “Characteristics” fIF(centre) (MHz) fosc (MHz) n BL−3dB (kHz) d RLFS (kΩ) CLFS (nF) CP(LFS) (pF) 36 31 62 36.1 1.22 5.6 4.7 22 31.5 63 35.6 1.21 32 64 35 1.20 44 40 80 34 1.31 6.8 18 57 53 106 34.4 1.52 9.1 15 2004 Nov 02 13 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS MHC095 handbook, halfpage V handbook, halfpage (µA) 3 MHC096 120 Vi(IF)(rms) (dBµV) ITAGC TAGC (V) 600 100 500 400 90 2 300 80 200 (1) 1 (2) (3) (4) 100 70 0 0 40 60 (1) IF AGC voltage. (2) Ituner; RTOP = 22 kΩ. 80 60 100 120 Vi(IF)(p-p) (dBµV) 0 4 8 12 16 20 24 RTOP (kΩ) (3) Ituner; RTOP = 8.2 kΩ. (4) Ituner; RTOP = 0 Ω. Fig.4 Fig.3 Typical IF and tuner AGC characteristic. Typical tuner takeover point as a function of RTOP. 1 V (p-p) handbook, halfpage 74 dBµV MHC097 120 handbook, halfpage C/N (dBc/Hz) 35.7 36.3 31.0 fosc 110 4.1 4.7 5.3 5.9 fIF input conditions (MHz) fLIF (MHz) output signal Intermodulation MHC098 100 handbook, halfpage 90 80 30 50 70 31.0 32.31 fIF fosc (MHz) input conditions 90 110 Vi(IF)(rms) (dBµV) 0 1.31 2.62 3.93 5.24 6.55 7.86 9.17 fLIF (MHz) output signal Harmonics Fig.5 Typical C/N ratio as a function of IF input voltage. 2004 Nov 02 Fig.6 Intermodulation and harmonics. 14 MHC105 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS MHC100 2 VLIF halfpage handbook, td(g)(LIF) (dB) 1 V = VP + Vripple handbook, halfpage MHC099 (ns) 0 −1 (3) −2 TDA9888TS TDA9889TS −3 −4 VP (V) 150 −6 100 −7 5.050 5.000 4.950 200 (2) −5 50 (1) −8 0 −9 −50 −10 0 2 4 6 8 10 −100 14 16 f (MHz) 12 tolerance scheme: (1) Fig.8 Detailed low IF amplitude and group delay pass band tolerance scheme. Fig.7 Ripple rejection condition. MHC101 −10 −10 −30 −30 −50 −50 (3) −90 −30 MHC102 30 LIF (dB) 10 handbook, V halfpage handbook, halfpage V −70 (3) (1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. t (s) 30 LIF (dB) 10 (2) (2) −25 (3) (2) (1) −70 (1) −20 −15 −10 −5 −90 0 f (MHz) 0 5 10 15 20 25 30 f (MHz) tolerance scheme: tolerance scheme: (1) (2) (1) (3) (2) (3) (1) Channel bandwidth = 6 MHz. (1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz. Fig.9 Fig.10 Low IF amplitude pass band tolerance scheme. Low IF amplitude stop band tolerance scheme. 2004 Nov 02 15 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS TEST AND APPLICATION INFORMATION handbook, full pagewidth TAGC external + VP GND TAGC TADJ 51 Ω H IF input RTOP 22 kΩ L 1:1 S1 10 nF IF input 16 15 14 13 12 11 10 9 6 7 8 AGC LIF1 TDA9888TS TDA9889TS 1 2 S0 L 3 fref S2 L H 10 nF M H 10 nF Cx 4 MHz 100 pF 5 4 CLFS 4.7 nF CLFLP 47 nF RLFS 5.6 kΩ + VP LFS 51 Ω LFLP LIF2 MHC103 external reference input circuit REF Fig.11 Test circuit. 2004 Nov 02 16 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS 100 nF handbook, full pagewidthtuner AGC GND 1 IF input 5 SAW FILTER 51 2 X7253D 4 Ω 3 + VP TADJ 10 nF RTOP 22 kΩ IF input (2) 16 15 14 13 12 (2) 11 10 9 6 7 8 TDA9888TS TDA9889TS 1 2 3 5 4 CP(LFS) 22 pF 100 nF(1) CLFS 4.7 nF Cx 4 MHz CLFLP 47 nF RLFS 5.6 kΩ REF LFS + VP 47 kΩ(1) LFLP CHANNEL DECODER MHC104 fIF = 36 MHz; channel bandwidth = 8 MHz; external AGC from channel decoder; inclusive narrow band tuner AGC. (1) Depends on channel decoder. (2) Open-pin if tuner AGC is not needed. Fig.12 Application circuit. 2004 Nov 02 17 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 2004 Nov 02 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 18 o Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 Nov 02 19 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. 2004 Nov 02 20 Philips Semiconductors Product specification DVB selective AGC amplifier TDA9888TS; TDA9889TS DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Nov 02 21 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R25/03/pp22 Date of release: 2004 Nov 02 Document order number: 9397 750 14249