Features • • • • • • • • • 1024 x 1024 Pixels with Memory Zone Up to 60 Images/Second Built-in Antiblooming Device Providing an Electronic Shutter Function Pixel: 14 µm x 14 µm Image Zone: 14.34 x 14.34 mm² Four Outputs (256 x 1024 pixels) at 20 MHz Each Possible Binning 2 x 2 Optical Shield against Parasitic Reflexions and Stray Light A/R Window in 400 - 700 nm Bandwidth Description The TH7887A is especially designed for high data rate applications (up to 60 pict/s) in medical and industrial fields. This area array image sensor consists of a 1024 x 1024 pixels (14 µm x 14 µm) image zone associated to a memory zone (masked with optical shield). In order to increase data rate, the image zone is divided into four zones (256 x 1024 each) which are read in parallel through 4 different outputs (readout frequency up to 20 MHz/output leading to a total readout frequency of 80 MHz). The TH7887A is designed with antiblooming gates. Moreover, the 2 x 2 binning mode is available on this sensor. In this case, the image size is 512 x 512 with 28 µm x 28 µm pixels. Each output will read 128 x 512 pixels. Area Array CCD Image Sensor 1024 x 1024 Pixels with Antiblooming TH7887A The TH7887A is sealed with a specific anti-reflective window optimized in 400 700 nm bandwidth. Rev. 2146A–IMAGE–05/02 1 Figure 1. TH7887A Organization ΦP 1, 2, 3, 4 ΦM 1, 2, 3, 4 ΦA VA 1024 x 1024 Image Zone 1024 x 1024 Memory Zone ΦM Φ L 1,2 VGS ΦR VDD1 VS1 VDD2 VS2 VDD3 VS3 VDD4 VS4 VOS1 2 VOS2 VOS3 VOS4 TH7887A 2146A–IMAGE–05/02 TH7887A Pin Identification AA ΦR VSS VDDP N.C VOS4 VOS3 VOS2 VOS1 Φ L1 VSS VDR VS4 VS3 W Φ L2 ΦM VS2 VSS V VGS VDD4 VDD3 VDD2 VDD1 VSS C ΦA Φ M4 Φ M3 ΦP3 ΦM2 Φ P2 ΦP1 VA VSS Φ M2 Φ P3 VSS VSS Φ M1 Φ P4 Φ P1 Φ M4 Φ M1 ΦP4 VSS 8 7 VSS 6 Φ P2 Φ M3 5 4 VSS 3 TOP VIEW Pin Number VS1 Symbol 2 B A 1 A1 Index Designation (1) ΦP4 (1) B2, C5 ΦP3 B5, C3(1) ΦP2 A5, C2(1) ΦP1 (1) ΦM1 (1) B7, C4 ΦM2 B4, C6(1) ΦM3 C7, A4(1) ΦM4 V7 ΦM W8 ΦL1 V8 ΦL2 V2 VDD1 V3 VDD2 V4 VDD3 V5 VDD4 W2 VS1 W3 VS2 W4 VS3 W5 VS4 AA6 VDDP Screen voltage AA5 NC Not connected A2, A6 A3, A7 Image zone clocks Memory zone clocks Memory to register clock Readout register clocks Output amplifier drain supply Output amplifier source supply V6 VGS Register output gate bias 3 2146A–IMAGE–05/02 Pin Number Symbol Designation AA1 VOS1 AA2 VOS2 AA3 VOS3 AA4 VOS4 AA8 ΦR Reset clock C8 ΦA Antiblooming gate clock W6 VDR C1 VA Video output signal AA7, V1, W1 VSS W7, A8, B8 VSS Reset bias Antiblooming diode bias Substrate bias B6, B1, A1, B3 VSS Note: 1. Short circuited on package. 4 TH7887A 2146A–IMAGE–05/02 TH7887A Geometrical Characteristics The image zone features 1024 useful lines (+ 20 extra lines) of 1024 pixels. For readout only, the full frame is split into 4 blocks of 256 columns. The video line consists of 256 useful pixels, and 273 elements in total (for each output). Figure 2. Video Line (on each output) 7 dark reference lines 3 isolation lines Image zone 1024 useful pixels 1044 line First pixel 3 isolation lines 1 inactive line 6 dark reference lines Memory zone Vos1 Vos2 Vos3 1044 line Vos4 Pixels 1 to 17 : inactive prescan elements Pixels 18 to 273 : useful elements 5 2146A–IMAGE–05/02 Figure 3. Pixel Layout ΦA VA ΦA ΦA VA ΦA A Φ P1 Φ P2 14 µm Φ P3 Φ P4 Φ P1 A' Aperture 10.3 µm 14 µm Figure 4. Cross-section AA’ Φ P1 Φ P2 Φ P3 Φ P4 Φ P1 14 µm Transfer direction Potential profile during integration time 6 Signal charge for one pixel TH7887A 2146A–IMAGE–05/02 TH7887A Absolute Maximum Ratings* *NOTICE: Storage Temperature .................................... -55°C to + 150°C Operating Temperature............................... -40°C to + 85°C Thermal Cycling.........................................................15°C/mm Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Maximum Applied Voltages: A2, A6, B2, C5, B5, C3, A5, C2, A3, A7, B7, C4 B4, C6, C7, A4, V7, W8, V8, AA8, V6, AA5.......... -0.3V to 15V V2, V3, V4, V5, W2, W3, W4, W5 W6, C1, AA6 ......................................................-0.3V to 15.5V C8 ......................................................................... -0.3V to 12V AA7, V1, W1, W7, A8, B8, B6, B1, A1, B3 ............. Ground 0V Operating Range The operating range defines the limits where function is guaranteed. Electrical limits of applied signals are given in the operating conditions section. Operating Precautions Shorting the video outputs to any other pin, even temporarily, can permanently damage the on-chip output amplifier. Operating Conditions Table 1. DC Characteristics Value Parameter Symbol Min Typ Max Unit VDD1, VDD2, VDD3, VDD4 14.5 15 15.5 V VDDP 14.5 15 15.5 V VDR 14.5 15 15.5 V Antiblooming diode bias VA 14.5 15 15.5 V Register output gate bias VGS 2.2 2.5 2.8 V VS1,2,3,4 – 0 – V VSS – 0 – V Output amplifier drain supply Screen voltage Reset bias Output amplifier source supply Ground 7 2146A–IMAGE–05/02 Timing Diagram The following diagrams are given for: • 20 MHz readout frequency • 1.25 MHz vertical transfer frequency Readout of one image is performed in 2 steps: • image zone to memory zone transfer • memory zone to register transfer and readout of register This last step is also an integration period, the duration of which can also be increased according to the required frame rates. Figure 5. Frame Timing Diagram Image to memory zone Transfer Integration period ΦA Picture readout Memory zone Cleaning period (*) Φ P1 Φ P2 Φ P3 Φ P4 1 5 1044 1044 pulses Φ M1=Φ M Φ M2 Φ M3 Φ M4 See fig. 7 1 5 1044 Φ L1 Φ L2 ΦR See fig. 6 (*) During the cleaning period, memory clocks must be pulsed as during readout time (specially for high temperature applications). 8 TH7887A 2146A–IMAGE–05/02 TH7887A Figure 6. Line Timing Diagram Item fig.8 7To 5To Φ M1=Φ M Φ M2 5To 3To Φ M3 Φ M4 3To See fig. 9 3To 3To 100 ns min. 100 ns min. Φ L1 Φ L2 ΦR Vos 1,2,3,4 1 17 18 273 min 1 2 17 1 1 1 : 17 inactive pre-scan elements 2 : 256 useful video pixels Figure 7. Vertical Transfer During Image to Memory Zone Transfer 20 ns < tr < 2 To 20 ns < tf < 2 To 100 ns min. 100 ns min. ΦA 1 2 1044 Φ P1 Φ P2 Φ P3 Φ P4 Φ M1= Φ M Φ M2 Φ M3 Φ M4 See fig. 8 9 2146A–IMAGE–05/02 Figure 8. Transfer Period from Image Zone to Memory Zone (ΦP and ΦM) for 1.25 MHz Vertical Transfer Frequency (Fv = 1/Tv) Tv=800 ns Φ P1 =Φ M1 tr 3 To tf 5 To 25 ns < tr < To/3 25 ns < tf < To/3 Φ P2 =Φ M2 5 To To = 100 ns Φ P3 =Φ M3 3 To 5 To Φ P4 =Φ M4 3 To To = Tv / 8 Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications 50 ns 16 ns min 16 ns min Φ L1 t1 t1 Φ L2 A 12 ns min 0.3A ΦR t2 Vos 1,2,3,4 t2 td td Signal level Reset feedthrough t1 = 10 ns typ. t2 = 5 ns typ. td = 8 ns typical delay time Cross over of complementary clocks (Φ L1, Φ L2) between 30% and 70% of maximum amplitude. 10 TH7887A 2146A–IMAGE–05/02 TH7887A Binning Mode Operation In this mode, the image is composed of 512 x 512 pixels (28 µm x 28 µm each). Figure 10. Summation in the Readout Register of 2 Adjacent Lines. 15 To Fall times and rise times: see figures 8 & 9 5To 3To 5To Φ M1 5To 3To 5To Φ M2 Φ M3 3To Φ M1 3To 5To 3T0 3To 5To 3To 3To Φ M =Φ M1 100 ns min 100 ns min Φ L1 Φ L2 Figure 11. Summation of 2 Adjacent Pixels Φ L1 Φ L2 Output reset frequency divided by 2 ΦR Vos 1,2,3,4 Pixel i Useful signal Pixel i + Pixel i+1 In binning mode operation maximum level of elementary pixel (14 x 14 µm) is reduced to Vsat/4. 11 2146A–IMAGE–05/02 Exposure Time Reduction The TH7887A allows exposure time control (electronic shutter function). The exposure time reduction is achieved by pulsing all the Φ Pi gates to 0V to continuously remove all photogenerated electrons through antiblooming drain VA. Figure 12. Timing Diagram for Electronic Shutter Image period ΦA 1 µs 1 µs Φ P1 Φ P2 Φ P3 Φ P4 Obturation Transfer Integration Fall times and rise times: see figures 7 & 8 Table 2. Drive Clock Characteristics Value Parameter Symbol Typ Max Unit Remarks ΦP1, 2, 3, 4 Image zone clocks High level Low level 8.5 0 9 0.5 9.5 0.8 V V Typical input capacitance 15 nF See Figure 13 8.5 0 9 0.5 9.5 0.8 V V Typical input capacitance 15.5 nF See Figure 13 8.5 0 9 0.5 9.5 0.8 V V 5.5 0 5.5 0.5 5.5 0.8 V V ΦM1, 2, 3, 4 Memory zone clocks High level Low level Memory to register clocks High level Low level ΦM Antiblooming gate High level (integration) Low level (transfer) ΦA 12 Min Typical input capacitance 10 nF Typical input capacitance 14 nF See Figure 13 and Figure 15 TH7887A 2146A–IMAGE–05/02 TH7887A Table 2. Drive Clock Characteristics (Continued) Value Parameter Symbol Min Typ Max Unit 10 0 11 0.5 12 0.8 V V 8.5 0 9 0.5 9.5 0.8 V V Remarks ΦR Reset gate High level Low level Typical input capacitance 10 pF ΦL1, 2 Readout register clocks High level Low level Φ L1 Φ L2 50 pF 60 pF 75 pF Maximum readout register frequency ΦFH – 20 23 MHz See Figure 9 Image zone to memory zone transfer frequency ΦFV – 1.25 1.7 MHz See Figure 14 Figure 13. Capacitance Network for Drive Clocks Φ P2 Φ P2 0.7 nF 3.4 nF ΦA 2.5 nF Φ P1 3.3 nF 0.5 nF 2.5 nF Φ P3 VA Φ P1 1.4 nF Φ P4 Φ P1 3.2 nF 4.9 nF 4.4 nF Φ P2 ΦA 2.2 nF 4.4 nF 4.4 nF 2.2 nF Φ P4 Φ M1 3.9 nF ΦP3 1.3 nF 0.7 nF ΦP4 0.5 nF 3.4 nF Φ P3 4.4 nF 4.4 nF Φ M2 3.2 nF 4.4 nF 4.4 nF 3.2 nF Φ M4 3.9 nF Φ M3 13 2146A–IMAGE–05/02 Electrical Performances Table 3. Static and Dynamic Electrical Characteritics Value Parameter Symbol Min Typ Max Unit Remarks Output amplier supply current IDD – 8.5 – mA per amplifier Output impedance ZS 200 225 250 Ω DC output level VREF – 11.5 – V Output conversion factor CVF 7.8 8 8.2 µV/ e- Electro-optical Performances • General test conditions: – Top = 25°C (package back temperature). – Light source: 2854K with 2 mm BG38 filter (unless specified) + F/3.5 optical aperture. – 60 images per second mode (unless specified). – Typical operating conditions. • Readout on each output. • Measurements exclude dummy elements and blemishes. Table 4. Electro-Optical Performance Characteristics Value Parameter Symbol Min Typ Max Unit VSAT 1.6 2 2.4 V Responsivity at 640 nm Responsivity with BG38 filter R 7 – 8 12 – – V/µJ/cm2 mV/lux Quantum efficiency at 640 nm QE – 14 – % Gain dispersion between outputs ∆G – 1 2 % Photo response non-uniformity (1σ) PRNU – 1.3 1.7 % VOS Dark signal non-uniformity (1σ) DSNU – 0.14 0.2 mV (2) VDS – – 1 2 1.5 2.8 mV mV (3) Average dark signal Temporal RMS noise in darkness (Last line) VN – 200 – µV (5) Dynamic range D – 80 – dB (6) Saturation output level 14 Remarks (1) See Figure 17 (4) TH7887A 2146A–IMAGE–05/02 TH7887A Table 4. Electro-Optical Performance Characteristics (Continued) Value Parameter Symbol Min Typ Max Unit Horizontal modulation transfer function at 500 nm MTF – 70 – % Vertical charge transfer inefficiency VCTI – – 2.10-5 (8) Horizontal charge transfer inefficiency HCTI – – 7.10-5 (9) Notes: Remarks (7) 1. Pixel saturation (full well) as a function of vertical transfer frequency (see Figure 14) and antiblooming adjustment (see Figure 15). 2. After subtraction of dark signal slope due to memory readout time. 3. First line level referenced from inactive prescan elements (17 samples). 4. Last line level referenced from inactive prescan elements(17 samples). 5. Measured with Correlated Double Sampling (CDS) including 160 µV readout noise and dark current noise in the general test conditions. 6. Saturation to RMS noise in darkness ratio. 7. At Nyquist frequency. 8. VSAT/2 measurement and 1.25 MHz vertical transfer frequency. 9. VSAT/2 measurement and 20 MHz horizontal transfer frequency. Figure 14. Saturation Level by full well with antiblooming out (ΦA high = 0V) vs the Vertical Transfer Frequency 3.5 3 Saturation Output Level (Volts) Readout stage limit 2.5 2 1.5 1 0.5 0 200 700 1200 1700 Vertical Transfer Frequency (KHz) 15 2146A–IMAGE–05/02 Figure 15. Saturation Level Limitation by the Antiblooming Effect on the Pixel 3 Saturation Output Level (Volts) Readout stage limit 2.5 Inefficient antiblooming 2 Efficient antiblooming 1.5 1 0.5 1.2 MHz vertical transfer frequency 0 2 3 4 5 7 6 8 9 ΦA High Clock Level (Volts) Figure 16. Smearing Effect 100 60 images / sec. 1.2 MHZ vertical tranfer frequency Smearing/Vsat (%) 80 Vertical smearing Overillumination 60 100xEsat 40 a b 20 Smearing level 10xEsat a,b signal line 0 0 1 2 3 4 5 6 7 8 9 10 Overilluminated Zone (% Image Height) 16 TH7887A 2146A–IMAGE–05/02 TH7887A Figure 17. Spectral Response Quantum efficiency (%) 20 15 10 5 0 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Lambda (mm) Image Quality Grade Blemish Max area of 2 x 2 defective pixels. Clusters Less than 7 contiguous defects in a column. Columns More than 7 contiguous defects in a column. General Measurement Conditions Room temperature 25°C Frequency 60 images/second typical operating conditions Considered image zone 1024 x 1024 Light source 2854 K with BG38 filter + F/3.5 optical aperture Table 5. At VOS = 0.7 Vsat. Type White Black Blemishes/clusters α > 20% VosS êα ï > 30% Vos Columns α > 10% Vos êα ï > 10% Vos Table 6. In darkness, T = 25°C, 60 images/second Blemishes/clusters α > 10 mV(1) Columns α > 5 mV(1) Note: 1. Reference is Vo : average darkness signal 17 2146A–IMAGE–05/02 Number of Defects Total pixel number affected by blemishes and clusters 100 Maximum number of clusters 10 Maximum number of columns 5 α : amplitude of video signal of defect with respect to mean output voltage Vos Ordering Code 18 TH7887AVRH TH7887A 2146A–IMAGE–05/02 TH7887A Outline Drawing TOP VIEW 55.88 28.5 25 x 2.54±0.25 1.75 y 33.5 42.5 x = 0.45 ± 0.10 y = 7.17 ± 0.10 36.6 Φ0.46 4.6 0.51 3.64±0.40 1.06±0.1 2.54 32.25 Φ 2.2 ± 0.05 (antireflective coating with 400 - 700 nm transmission: 99%) A1 index Optical shield AA W V C B A 40.64 BOTTOM VIEW 1st useful pixel - readout through Vos1 Photosensitive area Glass window thickness: 1.5 ± 0.1 mm 2.54 typ Φ 2.2 ± 0.04 1 2 3 4 5 6 7 8 14.25 All values in mm Tolerance unless specified ± 1% Reference for first pixel position Optical distance between photosensitive area and - external face of the window: 1.93 ± 0.30 mm - back side of the package: 1.71 ± 0.15 mm Metal plate connected to VSS Parallelism between CCD and back side has a maximum value of 100 µm 19 2146A–IMAGE–05/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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