TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 HIGH-VOLTAGE ADJUSTABLE REGULATOR FEATURES 1 • Output Adjustable From 1.25 V to 125 V When Used With an External Resistor Divider • 700-mA Output Current • Full Short-Circuit, Safe-Operating-Area, and 2 KTE (PowerFLEX) PACKAGE (TOP VIEW) KC (TO-220) PACKAGE (TOP VIEW) IN OUT ADJ KTT (TO-263) PACKAGE (TOP VIEW) IN IN OUT OUT OUT • • • Thermal-Shutdown Protection 0.001%/V Typical Input Voltage Regulation 0.15% Typical Output Voltage Regulation 76-dB Typical Ripple Rejection OUT OUT ADJ ADJ DESCRIPTION/ORDERING INFORMATION The TL783 is an adjustable three-terminal high-voltage regulator with an output range of 1.25 V to 125 V and a DMOS output transistor capable of sourcing more than 700 mA. It is designed for use in high-voltage applications where standard bipolar regulators cannot be used. Excellent performance specifications, superior to those of most bipolar regulators, are achieved through circuit design and advanced layout techniques. As a state-of-the-art regulator, the TL783 combines standard bipolar circuitry with high-voltage double-diffused MOS transistors on one chip, to yield a device capable of withstanding voltages far higher than standard bipolar integrated circuits. Because of its lack of secondary-breakdown and thermal-runaway characteristics usually associated with bipolar outputs, the TL783 maintains full overload protection while operating at up to 125 V from input to output. Other features of the device include current limiting, safe-operating-area (SOA) protection, and thermal shutdown. Even if ADJ is disconnected inadvertently, the protection circuitry remains functional. Only two external resistors are required to program the output voltage. An input bypass capacitor is necessary only when the regulator is situated far from the input filter. An output capacitor, although not required, improves transient response and protection from instantaneous output short circuits. Excellent ripple rejection can be achieved without a bypass capacitor at the adjustment terminal. ORDERING INFORMATION (1) PACKAGE (2) TJ 0°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING PowerFLEX™ – KTE Reel of 2000 TL783CKTER TL783 TO-263 – KTT Reel of 500 TL783CKTTR TL783C TO-220 – KC Tube of 50 TL783CKC TL783C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerFLEX, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1981–2008, Texas Instruments Incorporated TL783 SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 ............................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM VI − IN Error Amplifier ǒ Ǔ VO [ Vref 1 ) R2 R1 + VO OUT Protection Circuit Vref R1 ADJ R2 Absolute Maximum Ratings (1) over operating temperature range (unless otherwise noted) MIN MAX UNIT Vl – VO Input-to-output differential voltage 125 V TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range 150 °C (1) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Package Thermal Data (1) (1) (2) PACKAGE BOARD PowerFLEX (KTE) High K, JESD 51-5 TO-263 (KTT) High K, JESD 51-5 TO-220 (KC) High K, JESD 51-5 θJC θJP (2) θJA 2.7°C/W 23°C/W 18°C/W 1.94°C/W 25.3°C/W 17°C/W 3°C/W 19°C/W Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. Due to variations in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation. For packages with exposed thermal pads, such as QFN, PowerPAD™, or PowerFLEX, θJP is defined as the thermal resistance between the die junction and the bottom of the exposed pad. Recommended Operating Conditions MIN Vl – VO Input-to-output differential voltage IO Output current TJ Operating virtual junction temperature 2 Submit Documentation Feedback MAX UNIT 125 V 15 700 mA 0 125 °C Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 Electrical Characteristics Vl – VO = 25 V, IO = 0.5 A, TJ = 0°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS (1) TYP MAX TJ = 25°C 0.001 0.01 TJ = 0°C to 125°C 0.004 0.02 Input voltage regulation (2) Vl – VO = 20 V to 125 V, P ≤ rated dissipation Ripple rejection ΔVI(PP) = 10 V, VO = 10 V, f = 120 Hz MIN 66 IO = 15 mA to 700 mA, TJ = 25°C 25 mV VO ≥ 5 V 0.15 0.5 % IO = 15 mA to 700 mA, P ≤ rated dissipation VO ≤ 5 V 20 70 mV VO ≥ 5 V 0.3 1.5 % Output voltage long-term drift 1000 hours at TJ = 125°C, Vl – VO = 125 V Output noise voltage f = 10 Hz to 10 kHz, TJ = 25°C Minimum output current to maintain regulation Vl – VO = 125 V 0.4 % 0.2 % 0.003 715 Vl – VO = 25 V, t = 30 ms 700 900 Vl – VO = 125 V, t = 30 ms 100 250 ADJ input current Change in ADJ input current Reference voltage (OUT to ADJ) (3) Vl – VO = 10 V to 125 V, IO = 15 mA to 700 mA, P ≤ rated dissipation mA 1100 Vl – VO = 15 V, t = 30 ms Vl – VO = 15 V to 125 V, IO = 15 mA to 700 mA, P ≤ rated dissipation % 15 Vl – VO = 25 V, t = 1 ms (2) (3) dB 7.5 Output voltage change with temperature (1) %/V VO ≤ 5 V Output voltage regulation Peak output current 76 UNIT 1.2 mA 83 110 µA 0.5 5 µA 1.27 1.3 V Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. Input voltage regulation is expressed here as the percentage change in output voltage per 1-V change at the input Due to the dropout voltage and output current-limiting characteristics of this device, output current is limited to less than 700 mA at input-to-output voltage differentials of less than 25 V. Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 3 TL783 SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 ............................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ OUTPUT CURRENT LIMIT vs INPUT-TO-OUTPUT VOLTAGE DIFFERENTIAL 2 2 tw = 1 ms 1.6 1.4 1.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ 1 0.8 0.6 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ TJ = 0°C TJ = 25°C 0.4 tw = 30 ms 1.8 1.6 Output Current Limit − A 1.8 Output Current Limit − A OUTPUT CURRENT LIMIT vs INPUT-TO-OUTPUT VOLTAGE DIFFERENTIAL 1.4 1.2 TJ = 0°C 1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.8 0.6 0.4 0.2 0 0 0 25 50 75 100 0 125 Figure 1. 25 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 125 120 100 1.2 Ripple Rejection − dB Output Current Limit − A 100 RIPPLE REJECTION vs OUTPUT VOLTAGE VI − VO = 25 V TJ = 25°C 1.4 75 Figure 2. OUTPUT CURRENT LIMIT vs TIME 1.6 50 VI − VO − Input-to-Output Voltage Differential − V VI − VO − Input-to-Output Voltage Differential − V 1 0.8 0.6 80 60 40 0.4 20 0.2 0 0 0 10 20 30 40 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ VI(AV) − VO = 25 V ∆VI(PP) = 10 V IO = 100 mA f = 120 Hz Co = 0 TJ = 25°C 0 10 20 30 40 50 60 70 80 90 100 VO − Output Voltage − V Time − ms Figure 3. 4 TJ = 25°C TJ = 125°C TJ = 125°C 0.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Figure 4. Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 TYPICAL CHARACTERISTICS (continued) RIPPLE REJECTION vs OUTPUT CURRENT RIPPLE REJECTION vs FREQUENCY 100 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 90 100 80 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Ripple Rejection − dB Ripple Rejection − dB 80 60 40 20 VI(AV) = 25 V ∆VI(PP) = 10 V VO = 10 V f = 120 Hz Co = 0 TJ = 25°C 100 200 300 Co = 10 µF 60 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 50 40 30 10 400 500 600 700 0 0.01 800 0.1 IO − Output Current − mA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 10 100 1000 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ REFERENCE VOLTAGE vs VIRTUAL JUNCTION TEMPERATURE 1.30 VI = 35 V VO = 10 V IO = 500 mA TJ = 25°C 1.29 V ref − Reference Voltage − V Zo − Output Impedance − Ω 101 1 f − Frequency − kHz Figure 6. Figure 5. OUTPUT IMPEDANCE vs FREQUENCY 102 Co = 0 VI(AV) = 25 V ∆VI(PP) = 10 V VO = 10 V IO = 500 mA TJ = 25°C 20 0 0 70 10−1 10−2 VI = 20 V IO = 15 mA 1.28 1.27 1.26 1.25 1.24 10−3 1.23 10−4 101 102 103 104 105 106 107 1.22 −75 −50 −25 0 25 50 75 100 125 150 175 TJ − Virtual Junction Temperature − °C f − Frequency − kHz Figure 7. Figure 8. Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 5 TL783 SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 ............................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INPUT CURRENT AT ADJ vs VIRTUAL JUNCTION TEMPERATURE DROPOUT VOLTAGE vs VIRTUAL JUNCTION TEMPERATURE 25 90 VI = 25 V VO = Vref IO = 500 mA 20 Dropout Voltage − V ADJ Input Current − µ A 88 86 84 82 80 0 25 50 75 100 125 IO = 700 mA IO = 600 mA IO = 500 mA 10 IO = 250 mA 5 IO = 100 mA IO = 15 mA 0 −75 −50 −25 0 25 50 75 100 TJ − Virtual Junction Temperature − °C Figure 9. Figure 10. OUTPUT VOLTAGE DEVIATION vs VIRTUAL JUNCTION TEMPERATURE OUTPUT CURRENT(1) vs INPUT VOLTAGE 125 12 VI = 25 V VO = 5 V IO = 15 mA to 700 mA −0.1 TJ = 0°C 10 I O − Output Current − mA ∆VO − Output Voltage Deviation − % 15 TJ − Virtual Junction Temperature − °C 0 −0.2 −0.3 −0.4 8 TJ = 25°C 6 TJ = 125°C 4 2 0 −0.5 0 25 50 75 100 125 TJ − Virtual Junction Temperature − °C Figure 11. 6 ∆VO = 100 mV 150 0 25 50 75 100 125 VI − Input Voltage − V (1) This is the minimum current required to maintain voltage regulation. Figure 12. Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 TYPICAL CHARACTERISTICS (continued) ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ∆ VO − Output Voltage Deviation − V LOAD TRANSIENT RESPONSE TJ = 25°C 0.4 0.2 0 Co = 0 Co = 10 µF −0.2 1 0.5 0 0 1 2 3 Time − µs 4 I O − Output Current − A Change in Input Voltage − V ∆ VO − Output Voltage Deviation − V LINE TRANSIENT RESPONSE 6 4 2 0 −2 −4 −6 0.8 VI = 35 V VO = 10 V Co = 1 µF TJ = 25°C 0.6 0.4 0.2 0 0 Figure 13. 40 80 120 160 200 240 Time − µs Figure 14. Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 7 TL783 SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 ............................................................................................................................................... www.ti.com DESIGN CONSIDERATIONS The internal reference (see functional block diagram) generates 1.25 V nominal (Vref) between OUT and ADJ. This voltage is developed across R1 and causes a constant current to flow through R1 and the programming resistor R2, giving an output voltage of: VO = Vref (1 + R2/R1) + lI(ADJ) (R2) or VO ≈ Vref (1 + R2/R1) The TL783 was designed to minimize the input current at ADJ and maintain consistency over line and load variations, thereby minimizing the associated (R2) error term. To maintain II(ADJ) at a low level, all quiescent operating current is returned to the output terminal. This quiescent current must be sunk by the external load and is the minimum load current necessary to prevent the output from rising. The recommended R1 value of 82 Ω provides a minimum load current of 15 mA. Larger values can be used when the input-to-output differential voltage is less than 125 V (see the output-current curve in Figure 12) or when the load sinks some portion of the minimum current. Bypass Capacitors The TL783 regulator is stable without bypass capacitors; however, any regulator becomes unstable with certain values of output capacitance if an input capacitor is not used. Therefore, the use of input bypassing is recommended whenever the regulator is located more than four inches from the power-supply filter capacitor. A 1-µF tantalum or aluminum electrolytic capacitor usually is sufficient. Adjustment-terminal capacitors are not recommended for use on the TL783 because they can seriously degrade load transient response, as well as create a need for extra protection circuitry. Excellent ripple rejection presently is achieved without this added capacitor. Due to the relatively low gain of the MOS output stage, output voltage dropout may occur under large-load transient conditions. The addition of an output bypass capacitor greatly enhances load transient response and prevents dropout. For most applications, it is recommended that an output bypass capacitor be used, with a minimum value of: Co (µF) = 15/VO Larger values provide proportionally better transient-response characteristics. Protection Circuitry The TL783 regulator includes built-in protection circuits capable of guarding the device against most overload conditions encountered in normal operation. These protective features are current limiting, safe-operating-area protection, and thermal shutdown. These circuits protect the device under occasional fault conditions only. Continuous operation in the current limit or thermal shutdown mode is not recommended. The internal protection circuits of the TL783 protect the device up to maximum-rated VI as long as certain precautions are taken. If Vl is switched on instantaneously, transients exceeding maximum input ratings may occur, which can destroy the regulator. Usually, these are caused by lead inductance and bypass capacitors causing a ringing voltage on the input. In addition, when rise times in excess of 10 V/ns are applied to the input, a parasitic npn transistor in parallel with the DMOS output can be turned on, causing the device to fail. If the device is operated over 50 V and the input is switched on, rather than ramped on, a low-Q capacitor, such as tantalum or aluminum electrolytic, should be used, rather than ceramic, paper, or plastic bypass capacitors. A Q factor of 0.015, or greater, usually provides adequate damping to suppress ringing. Normally, no problems occur if the input voltage is allowed to ramp upward through the action of an ac line rectifier and filter network. Similarly, when an instantaneous short circuit is applied to the output, both ringing and excessive fall times can result. A tantalum or aluminum electrolytic bypass capacitor is recommended to eliminate this problem. However, if a large output capacitor is used, and the input is shorted, addition of a protection diode may be necessary to prevent capacitor discharge through the regulator. The amount of discharge current delivered is dependent on output voltage, size of capacitor, and fall time of Vl. A protective diode (see Figure 15) is required only for capacitance values greater than: Co (µF) = 3 × 104/(VO)2 8 Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 Care always should be taken to prevent insertion of regulators into a socket with power on. Power should be turned off before removing or inserting regulators. TL783 VI IN OUT VO ADJ R1 Co R2 Figure 15. Regulator With Protective Diode Load Regulation The current-set resistor (R1) should be located close to the regulator output terminal, rather than near the load. This eliminates long line drops from being amplified, through the action of R1 and R2, to degrade load regulation. To provide remote ground sensing, R2 should be near the load ground. VO TL783 VI IN Rline OUT ADJ RL R1 R2 Figure 16. Regulator With Current-Set Resistor Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 9 TL783 SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 ............................................................................................................................................... www.ti.com APPLICATION INFORMATION ǒ VI = 125 V IN VI = 145 to 200 V OUT ADJ 7.5 kΩ, 1 W R1 82 Ω + + 1 µF (see Note A) Ǔ VO + Vref 1 ) R2 R1 TL783 TIP150 10 µF 120 V, 1.5 W R2 0 to 8 kΩ IN OUT ADJ 0.1 µF 125 V R1 82 Ω TL783 + 10 µF R2 8.2 kΩ, 2W A. Figure 18. 125-V Short-Circuit-Protected Off-Line Regulator Needed if device is more than 4 inches from filter capacitor Figure 17. 1.25-V to 115-V Adjustable Regulator VI = 70 to 125 V 125 V 1Ω 10 Ω TIP30C 10 Ω TIPL762 1 kΩ TIPL762 1 kΩ TL783 VO = 50 V at 0.5 A 10 kΩ IN OUT TL783 10 kΩ IN ADJ OUT 82 Ω ADJ + 50 µF 3.3 kΩ, 1W R1 82 Ω ǒ Ǔ VO + Vref 1 ) R2 R1 + 50 µF R2 Figure 19. 50-V Regulator With Current Boost 10 Figure 20. Adjustable Regulator With Current Boost and Current Limit Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 TL783 www.ti.com ............................................................................................................................................... SLVS036M – SEPTEMBER 1981 – REVISED APRIL 2008 VI VI Load TL783 1 µF V I + ref R IN OUT TL783 ADJ R IN OUT I+ ADJ R V ref R Load Figure 21. Current-Sinking Regulator Figure 22. Current-Sourcing Regulator VI = 90 V VCC TL783 IN TL783 1 µF OUT IN ADJ OUT 6.25 Ω OUTPUT ADJ 82 Ω TL783 IN OUT R2 ADJ V+ 82 Ω 48 V − + INPUT TL081 V− 3.9 kΩ ǒ Ǔ VOFFSET + Vref I ) R2 82 Figure 23. High-Voltage Unity-Gain Offset Amplifier Figure 24. 48-V 200-mA Float Charger Submit Documentation Feedback Copyright © 1981–2008, Texas Instruments Incorporated Product Folder Link(s): TL783 11 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TL783CKC OBSOLETE TO-220 KC 3 TBD Call TI Call TI Samples Not Available TL783CKCE3 OBSOLETE TO-220 KC 3 TBD Call TI Call TI Samples Not Available TL783CKCSE3 ACTIVE TO-220 KCS 3 Pb-Free (RoHS) CU SN N / A for Pkg Type Request Free Samples TL783CKTER OBSOLETE PFM KTE 3 TBD Call TI Call TI Samples Not Available TL783CKTTR ACTIVE DDPAK/ TO-263 KTT 3 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR Request Free Samples TL783CKTTRG3 ACTIVE DDPAK/ TO-263 KTT 3 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR Request Free Samples 50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TL783CKTTR Package Package Pins Type Drawing SPQ DDPAK/ TO-263 500 KTT 3 Reel Reel Diameter Width (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.6 15.8 4.9 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL783CKTTR DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPFM001E – OCTOBER 1994 – REVISED JANUARY 2001 KTE (R-PSFM-G3) PowerFLEX PLASTIC FLANGE-MOUNT 0.375 (9,52) 0.080 (2,03) 0.070 (1,78) 0.365 (9,27) 0.360 (9,14) 0.050 (1,27) 0.040 (1,02) 0.350 (8,89) 0.220 (5,59) NOM 0.010 (0,25) NOM Thermal Tab (See Note C) 0.360 (9,14) 0.350 (8,89) 0.295 (7,49) NOM 0.320 (8,13) 0.310 (7,87) 0.420 (10,67) 0.410 (10,41) 1 3 0.025 (0,63) 0.031 (0,79) 0.100 (2,54) Seating Plane 0.004 (0,10) 0.010 (0,25) M 0.005 (0,13) 0.001 (0,03) 0.200 (5,08) 0.041 (1,04) 0.031 (0,79) 0.010 (0,25) NOM Gage Plane 3°– 6° 0.010 (0,25) 4073375/F 12/00 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. The center lead is in electrical contact with the thermal tab. Dimensions do not include mold protrusions, not to exceed 0.006 (0,15). Falls within JEDEC MO-169 PowerFLEX is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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