TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 D D D D D D D D D D Organization . . . 1 048 576 × 16 Single Power Supply (5 V or 3.3 V) Performance Ranges: ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX ’4xx160/P-60 60 ns 15 ns 30 ns ’4xx160/P-70 70 ns 18 ns 35 ns ’4xx160/P-80 80 ns 20 ns 40 ns DGE PACKAGE ( TOP VIEW ) READ OR WRITE CYCLE MIN 110 ns 130 ns 150 ns Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR) Refresh Long Refresh Period and Self-Refresh Option ( TMS4xx160P) 3-State Unlatched Output Low Power Dissipation High-Reliability Plastic 42-Lead (DZ Suffix) 400-Mil-Wide Surface-Mount (SOJ) Package and 44/50-Lead (DGE Suffix) Surface-Mount Thin Small-Outline Package ( TSOP) Operating Free-Air Temperature Range 0°C to 70°C Fabricated Using the Texas Instruments Enhanced Performance Implanted CMOS (EPIC) Technology AVAILABLE OPTIONS DEVICE POWER SUPPLY SELF REFRESH, BATTERY BACKUP TMS416160 TMS416160P TMS418160 TMS418160P TMS426160 TMS426160P TMS428160 TMS428160P 5V 5V 5V 5V 3.3 V 3.3 V 3.3 V 3.3 V — Yes — Yes — Yes — Yes REFRESH CYCLES 4096 in 64 ms 4096 in 128 ms 1024 in 16 ms 1024 in 128 ms 4096 in 64 ms 4096 in 128 ms 1024 in 16 ms 1024 in 128 ms description VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC NC W RAS A11† A10† A0 A1 A2 A3 VCC 1 50 2 49 3 48 4 5 47 46 6 45 7 44 8 43 9 42 10 41 11 40 15 36 16 35 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 DZ PACKAGE ( TOP VIEW ) VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC W RAS A11† A10† A0 A1 A2 A3 VCC 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 11 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS † A10 and A11 are NC for TMS4x8160 and TMS4x8160P. PIN NOMENCLATURE A0 – A11 DQ0 – DQ15 LCAS UCAS NC OE RAS VCC VSS W Address Inputs Data In / Data Out Lower Column-Address Strobe Upper Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe 5-V or 3.3-V Supply‡ Ground Write Enable The TMS4xx160 series is a set of high-speed, 16 777 216-bit dynamic random-access memories (DRAMs) organized as 1 048 576 words of 16 ‡ See Available Options Table. bits each. The TMS4xx160P series is a similar set of high-speed, low-power, self-refresh, 16 777 216-bit DRAMs organized as 1 048 576 words of 16 bits each. Both sets employ state-of-the-art enhanced performance implanted CMOS (EPIC) technology for high performance, reliability, and low power at low cost. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 description (continued) These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS4xx160 and TMS4xx160P are offered in a 44/50-lead plastic surface-mount TSOP (DGE suffix) and a 42-lead plastic surface-mount SOJ (DZ suffix) package. These packages are characterized for operation from 0°C to 70°C. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 logic symbol† RAM 1M × 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 ‡ A11 ‡ 17 18 19 20 23 24 25 26 27 28 16 15 20D8/21D0 A 0 1 048 575 20D15/21D7 20D16 20D17 20D18 20D19 C20[ROW] G23/[REFRESH ROW] RAS LCAS 14 24[PWR DWN] C21 G24 31 & 31 23C22 C21 G34 UCAS 30 & 31 23C32 Z31 24,25EN27 W 13 OE 29 DQ0 2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 3 4 5 7 8 9 10 33 34 DQ9 35 DQ10 DQ11 36 38 DQ12 39 DQ13 40 DQ14 41 DQ15 23,21D 34,25EN37 25 A,22D ∇26,27 A, Z26 A,32D ∇36,37 A, Z36 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. The pin numbers shown correspond to the DZ package. ‡ A10 and A11 are NC for TMS4x8160 and TMS4x8160P. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 functional block diagrams (TMS4x6160/P) RAS UCAS LCAS W OE Timing and Control A0 A1 8 Column Decode Column Address Buffers 256K Array 256K Array A7 A8 – A11 12 4 256K Array R o w 256K Array 32 D e c o d e 32 Row Address Buffers 32 Sense Amplifiers 256K Array 32 I/O Buffers 16 of 32 Selection DataIn Reg. DataOut Reg. 16 16 DQ0 – DQ15 256K Array 12 (a) TMS4x6160, TMS4x6160P functional block diagram (TMS4x8160/P) RAS UCAS LCAS W OE Timing and Control A0 A1 10 Column Decode Sense Amplifiers Column Address Buffers 256K Array 256K Array A9 Row Address Buffers 256K Array R o w 256K Array 32 D e c o d e 32 10 256K Array 32 32 256K Array (b) TMS4x8160, TMS4x8160P POST OFFICE BOX 1443 DataOut Reg. 16 16 DQ0 – DQ15 10 4 I/O Buffers 16 of 32 Selection DataIn Reg. • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 operation dual CAS Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins (DQ0– DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge. All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out (see parameter tCAC) is measured from each individual xCAS to its corresponding DQx pin. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high. For early-write cycles, the data is latched on the first xCAS falling edge. Only the DQs that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP . enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address may be presented immediately after tRAH (row-address hold time) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC maximum (access time from xCAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA (access time from rising edge of the last xCAS). address: A0 – A11 ( TMS4x6160, TMS4x6160P) and A0 – A9 ( TMS4x8160, TMS4x8160P) Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. For the TMS4x6160 and TMS4x6160P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS. For the TMS4x8160 and TMS4x8160P, 10 row-address bits are set up on A0 – A9 and latched onto the chip by RAS. Ten column-address bits are set up on A0 – A9 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. write enable ( W) The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 data in (DQ0 – DQ15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to applying data to the I/O lines. data out (DQ0 – DQ15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied. output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high. RAS-only refresh TMS4x6160, TMS4x6160P A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6160P) to retain data. This can be achieved by strobing each of the 4096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. TMS4x8160, TMS4x8160P A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x8160P) to retain data. This can be achieved by strobing each of the 1024 rows (A0 – A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally. xCAS-before-RAS (xCBR) refresh xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. battery-backup refresh TMS4x6160P A low-power battery-backup refresh mode that requires less than 600 µA (5 V ) or 350 µA (3.3 V ) refresh current is available on the TMS4x6160P. Data integrity is maintained using xCBR refresh with a period of 31.25 µs while holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels ( VIL < 0.2 V, VIH > VCC – 0.2 V ). 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 TMS4x8160P A low-power battery-backup refresh mode that requires less than 600 µA (5 V ) or 350 µA (3.3 V ) refresh current is available on the TMS4x8160P. Data integrity is maintained using xCBR refresh with a period of 125 µs while holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels ( VIL < 0.2 V, VIH > VCC – 0.2 V ). self refresh ( TMS4xx160P) The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and xCAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures the DRAM is fully refreshed. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC: TMS41x160, TMS41x160P . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V TMS42x160, TMS42x160P . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Voltage range on any pin (see Note 1): TMS41x160, TMS41x160P . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V TMS42x160, TMS42x160P . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions TMS41x160 TMS42x160 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 3 3.3 3.6 VCC VSS Supply voltage VIH VIL High-level input voltage 2.4 6.5 2 Low-level input voltage (see Note 2) –1 0.8 – 0.3 Supply voltage 0 0 UNIT V V VCC + 0.3 0.8 V V TA Operating free-air temperature 0 70 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 TMS416160/P electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ’416160 - 60 ’416160P - 60 TEST CONDITIONS† MIN VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1‡§ MAX 2.4 MIN MAX 2.4 ’416160 - 80 ’416160P - 80 MIN UNIT MAX 2.4 V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, xCAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA Read- or write-cycle current VCC = 5.5 V, Minimum cycle 90 80 70 mA 2 2 2 mA 1 1 1 mA 500 500 500 µA VIH = 2.4 V ( TTL), After 1 memory cycle, RAS and xCAS high ICC2 ’416160 - 70 ’416160P - 70 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle cycle, RAS and xCAS high ’416160 ’416160P ICC3§ Average refresh current (RAS-only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, xCAS high (RAS only), RAS low after xCAS low (CBR) 90 80 70 mA ICC4‡¶ Average page current VCC = 5.5 V, RAS low, tPC = MIN, xCAS cycling 90 80 70 mA ICC6# Self-refresh current xCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 500 500 500 µA ICC10# Battery back-up operating current (equivalent refresh time is 128 ms); CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VCC – 0.2 V ≤ VIH ≤ 6.5 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 600 600 600 µA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change while xCAS = VIH # For TMS416160P only 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 TMS418160/P electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PARAMETER ’418160 - 60 ’418160P - 60 TEST CONDITIONS† MIN VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1‡§ MAX 2.4 MIN MAX 2.4 ’418160 - 80 ’418160P - 80 MIN UNIT MAX 2.4 V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, xCAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA Read- or write-cycle current VCC = 5.5 V, Minimum cycle 190 180 170 mA 2 2 2 mA 1 1 1 mA ’418160P 500 500 500 µA VIH = 2.4 V ( TTL), After 1 memory cycle, RAS and xCAS high ICC2 ’418160 - 70 ’418160P - 70 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle cycle, RAS and xCAS high ’418160 ICC3§ Average refresh current (RAS-only refresh or CBR) VCC = 5.5 V, Minimum cycle, xCAS high (RAS only), RAS cycling, RAS low after xCAS low (CBR) 190 180 170 mA ICC4‡¶ Average page current VCC = 5.5 V, RAS low, tPC = MIN, xCAS cycling 100 90 80 mA ICC6# Self-refresh current xCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 500 500 500 µA ICC10# Battery back-up operating current (equivalent refresh time is 128 ms); CBR only tRC = 125 µs, tRAS ≤ 300 ns, VCC – 0.2 V ≤ VIH ≤ 6.5 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 600 600 600 µA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change while xCAS = VIH # For TMS418160P only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 TMS426160/P electrical characteristics over recommended ranges of supply voltage and operating free-air conditions (unless otherwise noted) (continued) PARAMETER ’426160 - 60 ’426160P - 60 TEST CONDITIONS† MIN ’426160 -70 ’426160P -70 MAX MIN ’426160 - 80 ’426160P - 80 MAX MIN UNIT MAX High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS VOL Low-level output voltage IOL = 2 mA IOL = 100 µA LVTTL 0.4 0.4 0.4 LVCMOS 0.2 0.2 0.2 II Input current (leakage) VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, xCAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA ICC1‡§ Read- or writecycle current VCC = 3.6 V, Minimum cycle 90 80 70 mA 1 1 1 mA ’426160 500 500 500 µA ’426160P 200 200 200 µA ICC2 Standby current 2.4 2.4 2.4 V VIH = 2 V (LVTTL), After 1 memory cycle, RAS and xCAS high VIH = VCC – 0.2 V ((LVCMOS), ), After 1 memory cycle, RAS and xCAS high VCC – 0.2 VCC – 0.2 VCC – 0.2 V ICC3§ Average refresh current (RAS-only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, xCAS high (RAS-only refresh) RAS low after xCAS low (CBR) 90 80 70 mA ICC4‡¶ Average page current VCC = 3.6 V, RAS low, tPC = MIN, xCAS cycling 90 80 70 mA ICC6# Self-refresh current xCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 250 250 250 µA ICC10# Battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VCC – 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 350 350 350 µA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change while xCAS = VIH # For TMS426160P only 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 TMS428160/P electrical characteristics over recommended ranges of supply voltage and operating free-air conditions (unless otherwise noted) (continued) PARAMETER ’428160 - 60 ’428160P - 60 TEST CONDITIONS† MIN ’428160 -70 ’428160P -70 MAX MIN ’428160 - 80 ’428160P - 80 MAX MIN UNIT MAX High-level output voltage IOH = – 2 mA LVTTL VOH IOH = – 100 µA LVCMOS VOL Low-level output voltage IOL = 2 mA IOL = 100 µA LVTTL 0.4 0.4 0.4 LVCMOS 0.2 0.2 0.2 II Input current (leakage) VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 3.6 V, xCAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA ICC1‡§ Read- or writecycle current VCC = 3.6 V, Minimum cycle 190 180 170 mA 1 1 1 mA ’428160 500 500 500 µA ’428160P 200 200 200 µA ICC2 Standby current 2.4 2.4 2.4 V VIH = 2 V (LVTTL), After 1 memory cycle, RAS and xCAS high VIH = VCC – 0.2 V ((LVCMOS), ), After 1 memory cycle, RAS and xCAS high VCC – 0.2 VCC – 0.2 VCC – 0.2 V ICC3§ Average refresh current (RAS-only refresh or CBR) VCC = 3.6 V, Minimum cycle, RAS cycling, xCAS high (RAS-only refresh) RAS low after xCAS low (CBR) 190 180 170 mA ICC4‡¶ Average page current VCC = 3.6 V, RAS low, tPC = MIN, xCAS cycling 100 90 80 mA ICC6# Self-refresh current xCAS < 0.2 V, RAS < 0.2 V, Measured after tRASS min 250 250 250 µA ICC10# Battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 125 µs, tRAS ≤ 300 ns, VCC – 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, W and OE = VIH, Address and data stable 350 350 350 µA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change while xCAS = VIH # For TMS428160P only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT Ci(A) Input capacitance, A0 – A11 5 pF Ci(OE) Input capacitance, OE 7 pF Ci(RC) Input capacitance, xCAS and RAS 7 pF Ci(W) Input capacitance, W 7 pF 7 pF CO Output capacitance NOTE 3: VCC = 5 V ± 0.5 V or 3.3 V ÷ 0.3 V (see Table 1), and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’4xx160 - 60 ’4xx160P - 60 MIN MAX ’4xx160 - 70 ’4xx160P - 70 MIN ’4xx160 - 80 ’4xx160P - 80 MAX MIN UNIT MAX tAA tCAC Access time from column address (see Note 4) 30 35 40 ns Access time from xCAS low (see Note 4) 15 18 20 ns tCPA tRAC Access time from column precharge (see Note 4) 35 40 45 ns Access time from RAS low (see Note 4) 60 70 80 ns tOEA tCLZ Access time from OE low (see Note 4) 15 18 20 ns Delay time, xCAS low to output in low-impedance state 0 0 0 ns tOH tOHO Output data hold time (from xCAS) 3 3 3 ns Output data hold time (from OE) 3 3 3 ns tOFF tOEZ Output disable time after xCAS high (see Note 5) 0 15 0 18 0 20 ns Output disable time after OE high (see Note 5) 0 15 0 18 0 20 ns NOTES: 4. Access times for TMS42x160 are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. tOFF and tOEZ are specified when the output is no longer driven. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature tRC tWC Cycle time, read (see Note 6) tRWC tPC ’4xx160 - 60 ’4xx160P - 60 ’4xx160 - 70 ’4xx160P - 70 ’4xx160 - 80 ’4xx160P - 80 MIN MIN MIN MAX MAX UNIT MAX 110 130 150 ns Cycle time, write (see Note 6) 110 130 150 ns Cycle time, read-write (see Note 6) 155 181 205 ns Cycle time, page-mode read or write (see Notes 6 and 7) 40 45 50 ns tPRWC tRASP Cycle time, page-mode read-write (see Note 6) 85 96 105 ns Pulse duration, RAS low, page mode (see Note 8) 60 100 000 70 100 000 80 100 000 ns tRAS tCAS Pulse duration, RAS low, nonpage mode (see Note 8) 60 10 000 70 10 000 80 10 000 ns Pulse duration, xCAS low (see Note 9) 15 10 000 18 10 000 20 10 000 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before xCAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data (see Note 9) 0 0 0 ns Setup time, W high before xCAS low 0 0 0 ns tCWL tRWL Setup time, W low before xCAS high 15 18 20 ns Setup time, W low before RAS high 15 18 20 ns tWCS tCAH Setup time, W low before xCAS low (early-write operation only) 0 0 0 ns Hold time, column address after xCAS low 10 15 15 ns tDH tRAH Hold time, data (see Note 10) 10 15 15 ns Hold time, row address after RAS low 10 10 10 ns tRCH tRRH Hold time, W high after xCAS high (see Note 11) 0 0 0 ns Hold time, W high after RAS high (see Note 11) 0 0 0 ns tWCH tCLCH Hold time, W low after xCAS low (early-write operation only) 10 15 15 ns 5 5 5 ns tRHCP tOEH Hold time, RAS high from xCAS precharge 35 40 45 ns Hold time, OE command 15 18 20 ns tROH tCHS Hold time, RAS referenced to OE 10 10 10 ns – 50 – 50 – 50 ns tCP Delay time, xCAS high (precharge) 10 10 10 ns tAWD Delay time, column address to W low (read-write operation only) 55 63 70 ns tCHR tCRP Delay time, RAS low to xCAS high (xCBR refresh only) 10 10 10 ns Delay time, xCAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to xCAS high 60 70 80 ns 5 5 5 ns tCWD tOED Delay time, xCAS low to W low (read-write operation only) 40 46 50 ns Delay time, OE to data 15 18 20 ns Hold time, xCAS low to xCAS high Hold time, xCAS low after RAS high (self refresh) Delay time, xCAS low to RAS low (xCBR refresh only) NOTES: 6. 7. 8. 9. 10. 11. All cycle times assume tT = 5 ns. To assure tPC min, tASC should be ≥ to tCP . In a read-write cycle, tRWD and tRWL must be observed. In a read-write cycle, tCWD and tCWL must be observed. Referenced to the later of xCAS or W in write operations Either tRRH or tRCH must be satisfied for a read cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’4xx160 - 60 ’4xx160P - 60 ’4xx160 - 70 ’4xx160P - 70 ’4xx160 - 80 ’4xx160P - 80 MIN MAX MIN MAX MIN MAX 30 15 35 15 40 UNIT tRAD tRAL Delay time, RAS low to column address (see Note 12) 15 Delay time, column address to RAS high 30 35 40 tCAL tRCD Delay time, column address to xCAS high 30 35 40 Delay time, RAS low to xCAS low (see Note 12) 20 tRPC tRSH Delay time, RAS high to xCAS low 0 0 0 ns Delay time, xCAS low to RAS high 15 18 20 ns tRWD tCPW Delay time, RAS low to W low (read-write operation only) 85 98 110 ns tRASS tRPS Pulse duration, self-refresh entry from RAS low Delay time, W low after xCAS precharge (read-write operation only) Pulse duration, RAS precharge after self refresh 45 75 ns 100 µs ’4x8160P 130 150 64 64 128 128 128 16 16 16 128 128 128 30 3 30 3 PARAMETER MEASUREMENT INFORMATION VTH VCC RL R1 Output Under Test DEVICE R2 CL = 100 pF (a) LOAD CIRCUIT (b) ALTERNATE LOAD CIRCUIT VCC ( V ) 5 R1 (Ω ) R2 (Ω ) 828 295 VTH ( V ) 1.31 RL (Ω ) 41x160 / P 42x160 / P 3.3 1178 868 1.4 500 Figure 1. Load Circuits for Timing Parameters 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns 64 3 CL = 100 pF ns 68 ’4x8160 Output Under Test ns 60 100 ’4x6160P tT Transition time NOTE 12: The maximum value is specified only to assure access time. 20 60 110 Refresh time interval 52 ns 100 ’4x6160 tREF 20 ns 218 30 ms ms ns TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tT tRP tRCD tCAS UCAS tCLCH (see Note A) tCP tCRP LCAS tCSH tRSH tRAD tRAH tASC tCAL tASR Address tRAL Row Column Don’t Care tRRH tCAH tRCS W tRCH tCAC (see Note B) tAA Don’t Care Don’t Care tOFF tOH tCLZ DQ0 – DQ15 See Note D Valid Data Out See Note C tRAC tOHO tROH OE NOTES: A. B. C. D. Don’t Care tOEZ Don’t Care tOEA To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary. Figure 2. Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tWC tRAS RAS tT tRP tRCD tCAS UCAS tCLCH (see Note A) LCAS tCP tASR tCRP tCSH tRSH tRAH tASC tCAL Address Row tRAL Column Don’t Care tCAH tCWL tRAD tRWL W Don’t Care Don’t Care tWP tDH (see Note B) DQ0 – DQ15 Don’t Care Don’t Care Valid Data In tDS (see Note B) tOED tOEH Don’t Care OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Referenced to the first xCAS or W, whichever occurs last C. xCAS order is arbitrary. Figure 3. Write-Cycle Timing 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tWC tRAS RAS tT tRP tRCD tCSH tCRP tCAS UCAS tRSH tCLCH (see Note A) LCAS tRAD tCP tASR tRAH tASC tCAL tRAL Address Column Row Don’t Care tCAH tWCS tWCH W tCWL tRWL tWP DQ0 – DQ15 Don’t Care Don’t Care Valid Data In tDH tDS OE Don’t Care NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. xCAS order is arbitrary. Figure 4. Early-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRWC tRAS RAS tRP tT tRCD tCAS UCAS tCSH tCRP tCLCH (see Note A) tCP tRSH tRAD LCAS tRAH tASC tASR Address Column Row Don’t Care tCAH tAWD tRWL tCWD tRCS W tCWL tWP Don’t Care Don’t Care tRWD tCLZ See Note B Valid Out DQ8 – DQ15 tAA tRAC Don’t Care tOHO tCAC (see Note C) tDH tDS tOEZ tOEA OE Don’t Care tOED See Note B Valid Out DQ0 – DQ7 NOTES: A. B. C. D. Valid In To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Output can go from a the high-impedance state to an invalid-data state prior to the specified access time. tCAC is measured from xCAS to its corresponding DQx. xCAS order is arbitrary. Figure 5. Read-Modify-Write-Cycle Timing 18 Don’t Care POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tRCD tCRP UCAS tRHCP tRSH tCLCH (see Note A) tPC tCSH tCAS tCP tASR LCAS tRAH tCAL tASC tRAL tCAH Address Row Column Don’t Care Column Don’t Care tRAD W tRRH tRCH Don’t Care Don’t Care tCAC (see Note B) tOH tAA tCPA (see Note C) tRCS tRAC tCLZ tOFF See Note D Valid Out DQ8 – DQ15 tOEZ tAA See Note D Valid Out DQ0 – DQ7 Valid Out tOEA tOHO tOHO OE Don’t Care tOEA Don’t Care To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Access time is tCPA or tAA dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing specifications are not violated. F. xCAS order is arbitrary. NOTES: A. B. C. D. E. Figure 6. Enhanced-Page-Mode Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tRSH UCAS tRHCP tPC tCLCH (see Note A) tRCD tCP tCSH LCAS tCRP tCAS tASR tCAH tASC tCAL tRAH Address tRAL Column Row Don’t Care Don’t Care Column tRAD tCWL tCWL tWP See Note B tDS W tRWL tWCH Don’t Care DQ8 – DQ15 Don’t Care Don’t Care Don’t Care Valid In tDH DQ0 – DQ7 See Note B Valid In Valid In Don’t Care tOED OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Referenced to the first xCAS or W, whichever occurs last C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing specifications are not violated. D. xCAS order is arbitrary. Figure 7. Enhanced-Page-Mode Write-Cycle Timing 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tCSH tRCD tRSH tCRP tPRWC tCAS UCAS tCP tCLCH (see Note A) LCAS tASR tASC tCAH tRAD Address Row Column Column tCWD tAWD tRAH tWP tCWL tRWL tRWD W tCAC tAA tRCS tDS tAA tRAC tCPA (see Note B) tDH (see Note C) tCLZ Valid In DQ0 – DQ15 Valid Out tOEA tOEH Valid Out Valid In tOEH tOEZ tOED OE NOTES: A. B. C. D. E. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Access time is tCPA or tAA dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are not violated. F. tCAC is measured from xCAS to its corresponding DQx. Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tRP tCRP tT xCAS See Note A Don’t Care tASR Address Don’t Care tRPC tRAH Don’t Care Row Don’t Care W Hi-Z DQ0 – DQ15 Don’t Care OE NOTE A: All xCAS must be high. Figure 9. RAS-Only Refresh-Cycle Timing 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Row TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION Refresh Cycle Memory Cycle tRAS tRAS Refresh Cycle tRP RAS tRP tCHR tCAS xCAS tASR tRAH Address tASC tCAH Row Don’t Care Col tRRH tRCS W Don’t Care tCAC tAA tRAC DQ0 – DQ15 tOFF Valid Data tOEZ tCLZ OE tOEA Figure 10. Hidden-Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRC tRP tRAS RAS tRPC xCAS tCSR tCHR tT W Don’t Care Address Don’t Care OE Don’t Care Hi-Z DQ0 – DQ15 NOTE A: Any xCAS can be used. Figure 11. Automatic-CBR-Refresh-Cycle Timing 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 PARAMETER MEASUREMENT INFORMATION tRASS RAS tRPC tRPS tCSR tCHS xCAS tCP Address Don’t Care W Don’t Care OE Don’t Care tOFF DQ0 – DQ15 Hi-Z Figure 12. Self-Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 MECHANICAL DATA DGE (R-PDSO-G44/50) PLASTIC SMALL-OUTLINE PACKAGE 0.018 (0,45) 0.012 (0,30) 0.031 (0,80) 50 0.006 (0,16) M 26 0.471 (11,96) 0.455 (11,56) 0.404 (10,26) 0.396 (10,06) 1 25 0.006 (0,15) NOM 0.829 (21,05) 0.821 (20,85) Gage Plane 0.010 (0,25) 0°– 5° 0.024 (0,60) 0.016 (0,40) Seating Plane 0.047 (1,20) MAX 0.002 (0,05) MIN 0.004 (0,10) 4040070-4 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS SMKS160C – MAY 1995 – REVISED NOVEMBER 1995 MECHANICAL DATA DZ (R-PDSO-J42) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 1.080 (27,43) 1.070 (27,18) 42 22 0.445 (11,30) 0.435 (11,05) 0,405 (10,29) 0.395 (10,03) 1 21 0.032 (0,81) 0.026 (0,66) 0.148 (3,76) 0.128 (3,25) 0.106 (2,69) NOM Seating Plane 0.020 (0,51) 0.016 (0,41) 0.004 (0,10) 0.007 (0,18) M 0.380 (9,65) 0.360 (9,14) 0.008 (0,20) NOM 0.050 (1,27) 4040094-6 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). device symbolization (TMS416160P illustrated) TI P -SS Speed ( - 60, - 70, - 80) Low-Power / Self-Refresh Designator (Blank or P) TMS416160 DZ Package Code W B Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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