TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 2.75-W FIXED GAIN MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER • Wafer Chip Scale Packaging (WCSP) – NanoFree™ Lead-Free (Pb-Free: YZF) FEATURES • • • • • Maximize Battery Life and Minimize Heat – 0.5-µA Shutdown Current – 3.0-mA Quiescent Current – High Efficiency Class-D • 88% at 400mW at 8Ω • 80% at 100mW at 8Ω Three Fixed Gain Versions – TPA2032D1 has a gain of 2 V/V (6dB) – TPA2033D1 has a gain of 3 V/V (9.5dB) – TPA2034D1 has a gain of 4 V/V (12dB) Only One External Component Required – Internal Matched Input Gain and Feedback Resistors for Excellent PSRR and CMRR – Optimized PWM Output Stage Eliminates LC Output Filter – PSRR (–75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a Dedicated Voltage Regulator – Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor – CMRR (–69 dB)Eliminates Two Input Coupling Capacitors Thermal and Short-Circuit Protection Pinout Very Similar to TPA2010D1 APPLICATIONS • Ideal for Wireless Handsets, PDAs, and other mobile devices DESCRIPTION The TPA2032D1 (2V/V gain), TPA2033D1 (3V/V gain), and TPA2034D1 (4V/V gain) are 2.75-W high efficiency filter-free class-D audio power amplifiers, each in an approximately 1.5-mm × 1.5-mm wafer chip scale package (WCSP) that requires only one external component. The pinout is the same as the TPA2010D1 except that the external gain setting input resistors required by the TPA2010D1 are integrated into the fixed gain TPA203xD1 family. Features like –75dB PSRR and improved RF-rectification immunity with a very small PCB footprint (WCSP amplifier plus single decoupling cap) make the TPA203xD1 family ideal for wireless handsets. A fast start-up time of 3.2 ms with minimal pop makes the TPA203xD1 family ideal for PDA applications. In wireless handsets, the earpiece, speaker phone, and melody ringer can each be driven by a TPA203xD1. The TPA203xD1 family has a low 27-µV noise floor, A-weighted. APPLICATION CIRCUIT VDD IN− _ Differential Input PWM 203xD1 CS ~ 2,5 mm VO− H− Bridge 9-BALL WAFER CHIP SCALE, YZF PACKAGE, (TOP VIEW OF PCB) VO+ + IN+ GND SHUTDOWN ~1,7 mm TPA To Battery Internal Oscillator 0402 CS Bias Circuitry TPA2032D1 1,4 mm 1,55 mm IN+ GND A1 A2 VDD PV DD B1 B2 VO− A3 PGND B3 IN− SHUTDWN VO+ C1 C2 C3 1,4 mm 1,55 mm Note: Pin A1 is marked with a “0” . Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE –40°C to 85°C Wafer chip scale packaging – Lead free (YZF) TPA2032D1YZF (1) BPX –40°C to 85°C Wafer chip scale packaging – Lead free (YZF) TPA2033D1YZF (1) BPY TPA2034D1YZF (1) BPZ –40°C to 85°C (1) PART NUMBER Wafer chip scale packaging – Lead free (YZF) SYMBOL The YZF package is only available taped and reeled. To order add the suffix R to the end of the part number for a reel of 3000, or add the suffix T to the end of the part number for a reel of 250 (e.g. TPA2032D1YZFR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPA2032D1, TPA2033D1, TPA2034D1 VDD Supply voltage VI Input voltage In active mode –0.3 V to 6 V In SHUTDOWN mode –0.3 V to 7 V –0.3 V to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature –40°C to 85°C TJ Operating junction temperature –40°C to 125°C Tstg Storage temperature ESD (1) –65°C to 150°C Electro-Static Discharge Tolerance - Human Body Model (HBM) for all pins (2) 2KV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The output pins Vo– and Vo+ are tolerant to 1.5KV HBM ESD (2) RECOMMENDED OPERATING CONDITIONS MIN VDD Supply voltage 2.5 VIH High-level input voltage SHUTDOWN VIL Low-level input voltage SHUTDOWN VIC TA NOM MAX UNIT 5.5 V 1.3 VDD V 0 0.35 V Common mode input voltage range VDD = 2.5 V, 5.5 V 0.5 VDD–0.8 V Operating free-air temperature –40 85 °C PACKAGE DISSIPATION RATINGS (1) (2) 2 PACKAGE DERATING FACTOR (1 / θJA) TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING YZF 4.8 mW/°C (1) 480 mW 264 mW 192 mW YZF 7.5 mW/°C (2) 750 mW 412 mW 300 mW Derating factor measured with JEDEC Low-K board; 1S0P - One signal layer and zero plane layers. Derating factor measured with JEDEC High K board; 1S2P - One signal layer and two plane layers. Please see JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package thermal information. Please see JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm. Submit Documentation Feedback TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS |VOS| Output offset voltage (measured differentially) Inputs AC grounded, VDD = 2.5 V to 5.5 V PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V MIN TYP MAX TPA2032D1 5 25 TPA2033D1 5 25 TPA2034D1 CMRR Common mode rejection ratio VIC = 0.5 V to (VDD –0.8 V) |IIH| High-level input current VDD = 5.5 V, VI = 5.8 V |IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 5 25 –75 -61 VDD = 2.5 V –69 -52 VDD = 3.6 V – 69 -52 VDD = 5.5 V –69 -52 VDD = 5.5 V, no load I(Q) I(SD) rDS(on) f(sw) Quiescent current Shutdown current Static drain-source on-state resistance RPD 5 µA 3 3.7 V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V 0.5 0.8 VDD = 2.5 V 550 VDD = 3.6 V 420 VDD = 5.0 V 350 VDD = 2.5 V to 5.5 V mA VDD = 2.5 V to 5.5 V 300 kΩ 400 TPA2032D1 5.5 6 6.5 TPA2033D1 9.0 9.5 10.0 TPA2034D1 11.5 12 12.5 Resistance of internal pulldown resistor from shutdown pin to GND µA mΩ 2 240 dB 5.7 2.2 Switching frequency dB µA VDD = 2.5 V, no load V(SHUTDOWN) <= 0.35 V mV 50 VDD = 3.6 V, no load Output impedance in SHUTDOWN Gain 4 UNIT 300 kHz dB kΩ OPERATING CHARACTERISTICS TA = 25°C, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS RL = 4 Ω, THD + N = 10%, f = 1 kHz RL = 4 Ω, THD + N = 1%, f = 1 kHz PO Output power RL = 8 Ω, THD + N = 10%, f = 1 kHz RL = 8 Ω, THD + N = 1%, f = 1 kHz Total harmonic distortion plus noise TYP MAX 2.75 VDD = 3.6 V 1.35 VDD = 2.5 V 0.59 VDD = 5 V 2.25 VDD = 3.6 V 1.12 VDD = 2.5 V 0.48 VDD = 5 V 1.68 VDD = 3.6 V 0.85 VDD = 2.5 V 0.38 VDD = 5 V 1.37 VDD = 3.6 V 0.68 VDD = 2.5 V THD+ N MIN VDD = 5 V 0.18% VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz 0.11% VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz 0.10% f = 217 Hz, V(RIPPLE) = 200 mVpp kSVR Supply ripple rejection ratio SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W, RL = 8 Ω, A weighted noise Submit Documentation Feedback W W W W 0.31 VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz VDD = 3.6 V, Inputs AC grounded with CI = 1 µF UNIT –73 dB 100 dB 3 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 OPERATING CHARACTERISTICS (continued) TA = 25°C, RL = 8 Ω (unless otherwise noted) PARAMETER Vn TEST CONDITIONS VDD = 3.6 V, f = 20 Hz to 20 kHz, Inputs AC grounded with Ci = 1 µF Output voltage noise CMRR Common mode rejection ratio RI Input impedance Start-up time from shutdown MIN TYP MAX No weighting 35 A weighting 27 VDD = 3.6 V, VIC = 1.0 Vpp , VCm = 1.8 f = 217 Hz V –69 AV = 2 V/V 30.2 AV = 3 V/V 22.8 AV = 4 V/V 18.5 VDD = 3.6 V 3.2 UNIT µVRMS dB kΩ ms Terminal Functions TERMINAL NAME YZF IN– C1 IN+ VO- I/O DESCRIPTION I Negative differential audio input A1 I Positive differential audio input A3 O Negative BTL audio output VO+ C3 O Positive BTL audio output GND A2 I Analog ground terminal. Must be connected to same potential as PGND using a direct connection to a single point ground. PGND B3 VDD B1 I PVDD B2 I High-current Power supply terminal. Must be connected to same power supply as VDD using a direct connection. Voltage must be within values listed in Recommended Operating Conditions table. SHUTDOWN C2 I Shutdown terminal. When terminal is low the device is put into Shutdown mode. High-current Analog ground terminal. Must be connected to same potential as GND using a direct connection to a single point ground. Power supply terminal. Must be connected to same power supply as PVDD using a direct connection. Voltage must be within values listed in Recommended Operating Conditions table. FUNCTIONAL BLOCK DIAGRAM Input Buffer SC 300 KΩ 4 Submit Documentation Feedback TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Efficiency vs Output power 1, 2 Power dissipation vs Output power 3, 4 Supply current vs Output power 5, 6 IDD Supply current vs Supply voltage 7 I(SD) Shutdown current vs Shutdown voltage PD PO Output power 8 vs Load resistance 9, 10 vs Supply voltage 11 vs Output power 12, 13 THD+N Total harmonic distortion plus noise vs Frequency 14, 15, 16, 17 vs Common-mode input voltage KSVR Supply voltage rejection ratio Supply voltage rejection ratio CMRR 19, 20, 21, 22, 23, 24, 25, 26, 27 vs Frequency GSM power supply rejection KSVR 18 vs Time 28 vs Frequency 29 vs Common-mode input voltage Common-mode rejection ratio 30, 31, 32 vs Frequency 33 vs Common-mode input voltage 34 TEST SET-UP FOR GRAPHS CI TPA2032D1 + Measurement Output IN+ OUT+ Load CI IN − − OUT − + Measurement Input − GND V DD + 30 kHz Low Pass Filter 1mF V DD − (1) CI was shorted for any common-mode input voltage measurement. All other measurements were taken with a 1-µF CI (unless otherwise noted). (2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (100Ω, 47-nF) is used on each output for the data sheet graphs. Submit Documentation Feedback 5 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 EFFICIENCY vs OUTPUT POWER VDD = 2.5 V 90 80 Efficiency - % 1.4 80 1.2 Class AB 4 W VDD = 5 V VDD = 3.6 V 50 Class AB 40 VDD = 3.6 V 60 VDD = 2.5 V 50 40 Class AB 30 30 20 RL = 8 W, 33 μH 0 0.2 0.4 0.6 0.8 1 PO - Output Power - W 1.2 1.4 0.4 VDD = 5 V, RL = 8 W 0.5 1 1.5 2 PO - Output Power - W 0 2.5 0.5 1 1.5 2 2.5 Figure 3. POWER DISSIPATION vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER 650 360 RL = 4 W, 33 μH 600 0.6 IDD - Supply Current - mA VDD = 3.6 V, RL = 4 W Class AB, 8 W 0.3 0.2 500 450 400 VDD = 5 V 350 300 250 VDD = 3.6 V 200 150 0 0.2 0.4 0.6 0.8 1 1.2 PO - Output Power - W 1.4 0 1.6 VDD = 3.6 V 240 VDD = 5 V 200 160 120 VDD = 2.5 V 40 50 VDD = 3.6 V, RL = 8 W 280 80 VDD = 2.5 V 100 0.1 RL = 8 W, 33 μH 320 550 0.5 3 PO - Output Power - W Figure 2. Class AB, 4 W 0 VDD = 5 V, RL = 4 W 0.6 Figure 1. 0.7 0.4 Class AB 8 W 0.8 0 0 0 0 1 0.2 RL = 4 W, 33 μH 10 10 IDD - Supply Current - mA Efficiency - % 60 20 PD - Power Dissipation - W 90 70 VDD = 5 V 70 POWER DISSIPATION vs OUTPUT POWER PD - Power Dissipation - W 100 EFFICIENCY vs OUTPUT POWER 0 0 0.5 1 1.5 2 2.5 PO - Output Power - W 3 0 0.5 0.25 1 0.75 1.5 1.25 1.75 PO - Output Power - W Figure 4. Figure 5. Figure 6. SUPPLY CURRENT vs SUPPLY VOLTAGE SHUTDOWN CURRENT vs SHUTDOWN VOLTAGE OUTPUT POWER vs LOAD RESISTANCE 3.6 RL = 8 W 3.2 IDD - Supply Current - mA IDD - Supply Current - mA 3.4 3.2 3 2.8 RL = 8 W, 33 mH 2.6 No Load 2.4 2.2 2 2.5 3 2.8 VDD = 5 V 2.4 2 1.6 VDD = 3.6 V 1.2 0.8 VDD = 2.5 V 3 4.5 3.5 4 5 VDD - Supply Voltage - V 5.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 Shutdown Voltage - V 2.5 VDD = 5 V, 10% 2 VDD = 3.6 V, 10% 1.5 VDD = 2.5 V, 10% 1 0.5 0.4 Figure 7. 6 3.5 RL = No Load PO - Output Power - W 3.6 0.7 Figure 8. Submit Documentation Feedback 0.8 0 4 9 14 19 24 RL - Load Resistance - W Figure 9. 29 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 3 2.5 4 W THD+N = 10% 2.5 PO - Output Power - W VDD = 5 V, 1% 1.5 VDD = 3.6 V, 1% 1 VDD = 2.5 V, 1% 4 W THD+N = 1% 2 8 W THD+N = 10% 1.5 1 0.5 0.5 0 0 4 9 14 19 24 8 W THD+N = 1% 2.5 29 3 3.5 4 4.5 VDD - Supply Voltage - V 5 20 RL = 4 W 10 VDD = 2.5 V VDD = 3 V VDD = 3.6 V 1 VDD = 5 V 0.1 0.05 10m 100m 1 PO - Output Power - W 3 Figure 11. Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 20 10 RL = 8 W VDD = 2.5 V VDD = 3 V VDD = 3.6 V 1 VDD = 5 V 0.1 0.05 10m 100m PO - Output Power - W 1 2 THD+N - Total Harmonic Distortion + Noise - % Figure 10. 1 RL = 8 W VDD = 5 V PO = 50 mW 0.1 PO = 250 mW PO = 1 W 0.01 20 100 1k f - Frequency - Hz 10k 20k 1 RL = 8 W VDD = 3.6 V PO = 25 mW PO = 125 mW 0.1 PO = 500 mW 0.01 20 100 1k f - Frequency - Hz 10k 20k Figure 13. Figure 14. Figure 15. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs COMMON MODE INPUT VOLTAGE 1 RL = 8 W VDD = 2.5 V PO = 15 mW 0.1 PO = 75 mW PO = 200 mW 0.01 0.005 20 100 1k f - Frequency - Hz Figure 16. 10k 20k THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL - Load Resistance - W THD+N - Total Harmonic Distortion + Noise - % PO - Output Power - W 2 THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE THD+N - Total Harmonic Distortion + Noise - % OUTPUT POWER vs LOAD RESISTANCE 1 RL = 4 W VDD = 5 V VDD = 4 V VDD = 3 V 0.1 VDD = 2.5 V VDD = 3.6 V 0.01 20 100 1k f - Frequency - Hz 10k 20k Figure 17. Submit Documentation Feedback Figure 18. 7 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2033D1 R L = 8 W, -50 -60 Gain = 2 V/V VDD = 2.5 V -70 -80 -90 -100 10 VDD = 3.6 V VDD = 5 V 100 1k f - Frequency - Hz 10 k Gain = 3 V/V VDD = 2.7 V -60 VDD = 2.5 V -70 -80 VDD = 5 V -90 -100 10 100 k VDD = 3.6 V 100 1k 10 k f - Frequency - Hz -40 -50 VDD = 2.5 V -60 -70 VDD = 5 V -80 Inputs ac-grounded, CI = 1 mF, -90 -100 10 100 k VDD = 2.7 V VDD = 3.6 V 100 RL = 8 W, Gain = 4 V/V 10 k 1k f - Frequency - Hz 100 k Figure 21. SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY- TPA2032D1 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY- TPA2033D1 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY- TPA2034D1 R L = 4 W, -50 -60 Gain = 2 V/V VDD = 2.5 V VDD = 3.6 V -70 -80 VDD = 5 V -90 100 1k 10 k f - Frequency - Hz -40 R L = 4 W, -50 -60 Gain = 3 V/V VDD = 2.7 V VDD = 2.5 V -70 -80 -90 -100 10 100 k -30 Inputs ac-grounded, CI = 1 mF, Supply Ripple Rejection Ratio - dB -40 -30 Inputs ac-grounded, CI = 1 mF, VDD = 3.6 V VDD = 5 V 100 1k 10 k f - Frequency - Hz -40 -50 R L = 4 W, Gain = 4 V/V VDD = 2.7 V -60 -70 VDD = 2.5 V -80 VDD = 5 V -90 -100 10 100 k Inputs ac-grounded, CI = 1 mF, VDD = 3.6 V 100 1k 10 k 100 k f - Frequency - Hz Figure 22. Figure 23. Figure 24. SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2032D1 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2033D1 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2034D1 -30 Supply Ripple Rejection Ratio - dB -40 Inputs Floating, R L = 8 W, Gain = 2 V/V -50 -60 VDD = 2.5 V -70 -80 VDD = 2.7 V VDD = 3.6 V -90 -100 10 VDD = 5 V 100 1k 10 k f - Frequency - Hz Figure 25. 100 k -40 -30 Inputs Floating, R L = 8 W, Supply Ripple Rejection Ratio - dB -30 Supply Ripple Rejection Ratio - dB -50 R L = 8 W, Figure 20. -100 10 8 -40 -30 Inputs ac-grounded, CI = 1 mF, Figure 19. -30 Supply Ripple Rejection Ratio - dB Supply Ripple Rejection Ratio - dB -40 -30 Inputs ac-grounded, CI = 1 mF, Supply Ripple Rejection Ratio - dB Supply Ripple Rejection Ratio - dB -30 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2034D1 Supply Ripple Rejection Ratio - dB SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY - TPA2032D1 Gain = 3 V/V -50 -60 VDD = 2.5 V -70 VDD = 2.7 V -80 VDD = 3.6 V -90 -100 10 VDD = 5 V 100 10 k 1k f - Frequency - Hz Figure 26. Submit Documentation Feedback 100 k -40 -50 Inputs Floating, R L = 8 W, Gain = 4 V/V VDD = 2.5 V -60 -70 -80 -90 -100 10 VDD = 2.7 V VDD = 3.6 V VDD = 5 V 100 1k 10 k f - Frequency - Hz Figure 27. 100 k TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 GSM POWER SUPPLY REJECTION vs FREQUENCY 0 -20 -40 -60 -80 -100 -120 -140 VO - Output Voltage - dBV VDD 200 mV/div VOUT 20 mV/div t - Time - 2 mS/div 10 -10 -30 -50 -70 -90 -110 -130 -150 VDD Shown in Figure 22 CI = 1 mF, Inputs ac-Grounded 0 200 400 600 800 1k 1.2k 1.4k 1.6k1.8k 2k f - Frequency - Hz Figure 28. Figure 29. SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE TPA2033D1 SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE TPA2034D1 0 -10 -30 -40 -50 VDD = 2.5 V -60 VDD = 3.6 V VDD = 5 V -70 -80 -90 Supply Ripple Rejection Ratio - dB 0 -10 Supply Ripple Rejection Ratio - dB 0 -10 -20 -30 -40 VDD = 2.5 V VDD = 3.6 V -50 -60 VDD = 5 V -70 -80 0.5 1 1.5 2 2.5 3 3.5 4 4.5 DC Common-Mode Voltage - V 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 DC Common-Mode Voltage - V Figure 30. COMMON-MODE REJECTION RATIO vs FREQUENCY -60 VDD = 3.6 V, -65 VIC = 1 Vpp, RL = 8 W -70 -75 -80 -85 10 VDD = 2.5 V 5 100 1k 10 k f - Frequency - Hz 100 k VDD = 3.6 V -30 -40 -50 VDD = 5 V -60 -70 -80 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 DC Common-Mode Voltage - V Figure 31. Figure 32. COMMON-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE CMRR - Common-Mode Rejection Ratio - dB 0 -20 -90 0 -90 CMRR - Common Mode Rejection Ratio - dB Supply Ripple Rejection Ratio - dB SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE TPA2032D1 -20 VDD - Supply Voltage - dBV GSM POWER SUPPLY REJECTION vs TIME -40 -45 -50 -55 -60 VDD = 5 V VDD = 2.5 V VDD = 3.6 V -65 -70 -75 -80 -85 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VIC - Common-Mode Input Voltage - V Figure 33. Submit Documentation Feedback 5 Figure 34. 9 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 APPLICATION INFORMATION FULLY DIFFERENTIAL AMPLIFIER The TPA2032D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input. The fully differential TPA2032D1 can still be used with a single-ended input; however, the TPA2032D1 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully Differential Amplifiers • Input-coupling capacitors not required: – The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. The inputs of the TPA2032D1 can be biased anywhere within the common mode input voltage range listed in the Recommended Operating Conditions table. If the inputs are biased outside of that range, input-coupling capacitors are required. • Midsupply bypass capacitor, C(BYPASS), not required: – The fully differential amplifier does not require a bypass capacitor. Any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output. • Better RF-immunity: – GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal better than the typical audio amplifier. COMPONENT SELECTION Figure 35 shows the TPA2032D1 typical schematic with differential inputs, while Figure 36 shows the TPA2032D1 with differential inputs and input capacitors. Figure 37 shows the TPA2032D1 with a single-ended input. Decoupling Capacitor (CS) The TPA2032D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the TPA2032D1 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Typically, the smaller the capacitor's case size, the lower the inductance and the closer it can be placed to the TPA2032D1. Input Capacitors (CI) The TPA2032D1 does not require input coupling capacitors if the design uses a differential source that is biased within the common-mode input voltage range. That voltage range is listed in the Recommended Operating Conditions table. If the input signal is not biased within the recommended common-mode input range, such as in needing to use the input as a high pass filter, shown in Figure 36, or if using a single-ended source, shown in Figure 37, input coupling capacitors are required. The same value capacitors should be used on both IN+ and IN– for best pop performance. 1 fc + ǒ2p RICIǓ (1) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speaker response may also be taken into consideration when setting the corner frequency using input capacitors. 10 Submit Documentation Feedback TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 APPLICATION INFORMATION (continued) Equation 2 is reconfigured to solve for the input coupling capacitance. 1 C + I ǒ2p RI f cǓ (2) If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. For a flat low-frequency response, use large input coupling capacitors (1 µF or larger). To Battery Internal Oscillator VDD CS IN− PWM _ Differential Input H− Bridge VO− VO+ + IN+ GND Bias Circuitry SHUTDOWN TPA2032D1 Filter-Free Class D Figure 35. Typical TPA2032D1 Application Schematic With Differential Input for a Wireless Phone To Battery CI Differential Input Internal Oscillator VDD CS IN− _ CI PWM H− Bridge VO− VO+ + IN+ GND SHUTDOWN Bias Circuitry TPA2032D1 Filter-Free Class D Figure 36. TPA2032D1 Application Schematic With Differential Input and Input Capacitors Submit Documentation Feedback 11 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 APPLICATION INFORMATION (continued) CI Single-ended Input To Battery Internal Oscillator VDD IN− _ PWM CS VO− H− Bridge VO+ + IN+ CI GND Bias Circuitry SHUTDOWN TPA2032D1 Filter-Free Class D Figure 37. TPA2032D1 Application Schematic With Single-Ended Input BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 38 and Table 1 show the appropriate diameters for a WCSP layout. The TPA2032D1 evaluation module (EVM) layout is shown in the next section as a layout example. Copper Trace Width Solder Pad Width Solder Mask Opening Copper Trace Thickness Solder Mask Thickness Figure 38. Land Pattern Dimensions 12 Submit Documentation Feedback TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 APPLICATION INFORMATION (continued) Table 1. Land Pattern Dimensions SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK OPENING COPPER THICKNESS STENCIL OPENING STENCIL THICKNESS Nonsolder mask defined (NSMD) 275 µm (+0.0, –25 µm) 375 µm (+0.0, –25 µm) 1 oz max (32 µm) 275 µm x 275 µm Sq. (rounded corners) 125 µm thick NOTES: 1. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. 2. Recommended solder paste is Type 3 or Type 4. 3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating range of the intended application. 4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in thermal fatigue performance. 5. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern. 6. Best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. 7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. Component Location Place all the external components very close to the TPA2032D1. Placing the decoupling capacitor, CS, close to the TPA2032D1 is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. Trace Width Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. Figure 39 shows the layout of the TPA2032D1 evaluation module (EVM). For high current pins (VDD, GND VO+, and VO-) of the TPA2032D1, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device. For input pins (IN–, IN+, and SHUTDOWN) of the TPA2032D1, use 75-µm to 100-µm trace widths at the solder balls. IN– and IN+ traces need to run side-by-side to maximize common-mode noise cancellation. Submit Documentation Feedback 13 TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 75 mm 100 mm 100 mm 100 mm 375 mm (+0, -25 mm) 275 mm (+0, -25 mm) 100 mm Circular Solder Mask Opening Paste Mask (Stencil) = Copper Pad Size 75 mm 100 mm 75 mm Figure 39. Close Up of TPA2032D1 Land Pattern From TPA2032D1 EVM EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the YZF package is shown in the dissipation rating table. Converting this to θJA: 1 q + JA Derating Factor (3) Given θJA (from the Package Dissipation ratings table), the maximum allowable junction temperature (from the Absolute Maximum ratings table), and the maximum internal dissipation (from Power Dissipation vs Output Power figures) the maximum ambient temperature can be calculated with the following equation. Note that the units on these figures are Watts RMS. Because of crest factor (ratio of peak power to RMS power) from 9–15 dB, thermal limitations are not usually encountered. T Max + T Max * q P A J JA Dmax (4) The TPA2032D1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Note that using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. θJA is a gross approximation of the complex thermal transfer mechanisms between the device and its ambient environment. If the θJA calculation reveals a potential problem, a more accurate estimate should be made. Please contact TI for further information. 14 Submit Documentation Feedback TPA2032D1 TPA2033D1 TPA2034D1 www.ti.com SLOS476 – JUNE 2006 WHEN TO USE AN OUTPUT FILTER Design the TPA2032D1 without an output filter if the traces from the amplifier to the speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used without an output filter. The TPA2032D1 passed FCC- and CE-radiated emissions testing with no shielding with speaker trace wires 100 mm long or less. For longer speaker trace wires, a ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter; and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower than rated current values. Please see the EVM User's Guide for components used successfully by TI. Figure 40 shows a typical ferrite-bead output filter. Ferrite Chip Bead VO− 1 nF Ferrite Chip Bead VO+ 1 nF Figure 40. Typical Ferrite Chip Bead Filter Submit Documentation Feedback 15 PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPA2033D1YZFR DSBGA YZF 9 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.65 1.65 0.81 4.0 8.0 Q1 TPA2033D1YZFT DSBGA YZF 9 250 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1 TPA2034D1YZFR DSBGA YZF 9 3000 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1 TPA2034D1YZFT DSBGA YZF 9 250 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA2033D1YZFR DSBGA YZF 9 3000 182.0 182.0 17.0 TPA2033D1YZFT DSBGA YZF 9 250 182.0 182.0 17.0 TPA2034D1YZFR DSBGA YZF 9 3000 182.0 182.0 17.0 TPA2034D1YZFT DSBGA YZF 9 250 182.0 182.0 17.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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