TPS799L www.ti.com SBVS191 – APRIL 2012 200-mA, Low-Dropout Linear Regulator with Built-In Inrush Current Protection FEATURES DESCRIPTION • • The TPS799L family of low-dropout (LDO), low-power linear regulators offers excellent ac performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient response are provided while consuming a very low 40 μA (typical) ground current. 1 23 • • • • • • • • 200mA Low-Dropout Regulator with EN Multiple Output Voltage Versions Available: – TPS799L: Fixed Outputs of 5.2 V to 6.2 V Using Innovative Factory EEPROM Programming – TPS799L57 : 5.7-V Output – TPS799: Output Options Less Than 5.2 V Inrush current Protection with EN Toggle Low IQ: 40 μA High PSRR: 66 dB at 1 kHz Stable with a Low-ESR, 2.0-μF Typical Output Capacitance Excellent Load/Line Transient Response 2% Overall Accuracy (Load, Line, and Temp) Very Low Dropout: 100 mV Package: 5-Bump, Thin, 1-mm × 1.37-mm WCSP The TPS799Lxx is stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a dropout voltage of typically 100 mV at a 200 mA output. The TPS799L uses a precision voltage reference and feedback loop to achieve an overall accuracy of 2% over all load, line, process, and temperature variations. The TPS799L features inrush current protection when the EN toggle is used to start the device, immediately clamping the current. All devices are fully specified over the temperature range of TJ = –40°C to +125°C, and offered in a lowprofile, wafer chip-scale (WCSP) package, ideal for wireless handsets and WLAN cards. APPLICATIONS • • • • TYPICAL APPLICATION CIRCUIT Cellular Phones Wireless LAN, Bluetooth® VCOs, RF Handheld Organizers, PDAs Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN EN TPS799LxxYZY WCSP (TOP VIEW) C3 VEN C1 IN OUT B2 GND A3 NR VOUT OUT TPS799Lxx GND NR 2.2 mF Ceramic Optional bypass capacitor to reduce output noise and increase PSRR. A1 EN 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS799L SBVS191 – APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TPS799Lxx yyy z (1) XX is nominal output voltage (for example, 57 = 5.7V). YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage (2) Current Electrostatic discharge ratings (3) (2) (3) MAX UNIT IN –0.3 +7.0 V EN –0.3 VIN + 0.3 V OUT –0.3 VIN + 0.3 OUT Temperature (1) MIN Internally limited V mA Operating virtual junction, TJ –55 +150 Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Charge device model (CDM) QSS 009-147 (JESD22-C101B.01) °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TPS799L THERMAL METRIC (1) (2) YZY (WCSP) UNITS 5 PINS θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 1.1 θJB Junction-to-board thermal resistance 84.7 ψJT Junction-to-top characterization parameter 3.8 ψJB Junction-to-board characterization parameter 84.4 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) (2) 2 143.3 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS799L www.ti.com SBVS191 – APRIL 2012 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER VIN TEST CONDITIONS MIN V Output voltage range 5.2 6.2 V +1.0 % +2.0 % TJ = +25°C –1.0 VOUT + 0.3 V ≤ VIN ≤ 6.5 V 500 μA ≤ IOUT ≤ 200 mA –2.0 ΔVO(ΔVI) Line regulation (1) VOUT(NOM) + 0.3 V ≤ VIN ≤ 6.5 V ΔVO(ΔIO) Load regulation 500 μA ≤ IOUT ≤ 200 mA VDO Dropout voltage (VIN = VOUT(NOM) – 0.1V) VOUT ≥ 3.3 V, IOUT = 200 mA ILIM Output current limit (2) VOUT = 0.9 × VOUT(NOM) IGND Ground pin current 500 μA ≤ IOUT ≤ 200 mA ISHDN Shutdown current (IGND) VEN ≤ 0.4 V, 2.7 V ≤ VIN ≤ 6.5 V Power-supply rejection ratio VIN = 6.5 V, VOUT = 2.85 V, CNR = 0.01 μF, IOUT = 100 mA VN UNIT 6.5 Output accuracy (1) Over VIN, IOUT, temperature PSRR MAX 2.7 Output accuracy, nominal VOUT TYP Input voltage range (1) Output noise voltage BW = 10 Hz to 100 kHz VOUT = 5.7 V, RL = 28 Ω, COUT = 2.2 μF 220 ±1.0 0.02 %/V 0.002 %/mA 90 160 mV 340 600 mA 40 60 μA 0.15 1.0 μA f = 100 Hz 70 dB f = 1 kHz 66 dB f = 10 kHz 51 dB f = 100 kHz 38 dB CNR = 0.01 μF CNR = none CNR = 0.01 μF 10.5 x VOUT μVRMS 94 x VOUT μVRMS μs 90 TSTR Start-up time VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current, enabled VEN = VIN = 6.5 V 0.03 Tsd Thermal shutdown temperature Shutdown, temperature increasing 165 °C Reset, temperature decreasing 145 °C TJ Operating junction temperature UVLO (1) (2) CNR = none VIN V 0 0.4 V 1.0 μA –40 Undervoltage lockout VIN rising Hysteresis VIN falling μs 95 1.2 1.90 +125 2.20 2.65 70 °C V mV Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. TPS799Lxx has peak current clamp during EN toggle start-up. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS799L SBVS191 – APRIL 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN OUT 400 W 2 mA Current Limit EN Thermal Shutdown Overshoot Detect UVLO Start-Up 1.193-V Bandgap NR 500 kW GND Figure 1. Functional Block Diagram PIN CONFIGURATION YZY PACKAGE WCSP-5 (TOP VIEW) C3 C1 IN OUT B2 GND A3 NR A1 EN PIN DESCRIPTIONS PIN 4 NAME NO. DESCRIPTION EN A1 Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. GND B2 Ground. IN C3 Input supply. NR A3 Noise reduction; connecting this pin to an external capacitor bypasses noise generated by the internal bandgap. This capacitor allows output noise to be reduced to very low levels. OUT C1 Output of the regulator. To assure stability, a small ceramic capacitor (total typical capacitance ≥ 2.0 μF) is required from this pin to ground. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS799L www.ti.com SBVS191 – APRIL 2012 TYPICAL CHARACTERISTICS Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. LOAD REGULATION (VIN = 6.5 V) OUTPUT VOLTAGE vs JUNCTION TEMPERATURE (TPS799Axx) 5.8 IOUT = 10 mA IOUT = 250 mA +125°C +85°C +25°C -40°C 5.75 5.75 VOUT (V) Output Voltage (V) 5.8 5.7 5.7 5.65 5.65 5.6 −40 −25 −10 5.6 0 50 100 150 200 250 5 20 35 50 65 Temperature (ºC) 80 95 110 125 G009 Output Current (mA) Figure 2. Figure 3. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs INPUT VOLTAGE, IOUT = 250mA 140 200 180 120 160 140 VDO (mV) VDO (mV) 100 80 60 40 100 80 60 +125°C +85°C +25°C -40°C 20 120 +125°C +85°C +25°C -40°C 40 20 0 0 0 50 100 150 200 250 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Output Current (mA) VIN (V) Figure 4. Figure 5. GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs OUTPUT CURRENT (VIN = 6.5 V) 60 47 46 Ground Pin Current (mA) 50 IOUT = 200 mA IGND (mA) 40 IOUT = 500 mA 30 20 10 +125°C 45 44 +85°C 43 +25°C 42 41 -40°C 40 0 39 2.5 3.0 3.5 4.0 4.5 5.0 VIN (V) Figure 6. Copyright © 2012, Texas Instruments Incorporated 5.5 6.0 6.5 7.0 0 50 100 150 200 250 Output Current (mA) Figure 7. Submit Documentation Feedback 5 TPS799L SBVS191 – APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT (DISABLED) vs JUNCTION TEMPERATURE 600 POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 6.5 V) 100 VEN = 0.4V 80 70 PSRR (dB) 400 IGND (nA) IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 500 300 200 60 50 40 30 VIN = 6.5V 20 100 0 0 −40 −25 −15 5 20 35 COUT = 2.2 µF CNR = 0.01 µF 10 VIN = 3.2V 50 65 80 95 110 125 10 100 1k 10k 100k Frequency (Hz) 1M 10M G001 TJ (°C) Figure 8. Figure 9. POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 6.2 V) POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 5.95 V) 100 100 IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 80 80 70 PSRR (dB) PSRR (dB) 70 60 50 40 30 10 40 100 COUT = 2.2 µF CNR = 0.01 µF 10 1k 10k 100k Frequency (Hz) 1M 0 10M 10 100 1k G002 10k 100k Frequency (Hz) 1M 10M G003 Figure 10. Figure 11. POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 6.5 V) POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 6.2 V) 100 100 IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 80 80 PSRR (dB) 70 60 50 40 30 60 50 40 30 20 20 COUT = 10 µF CNR = 0.01 µF 10 0 IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 70 PSRR (dB) 50 20 COUT = 2.2 µF CNR = 0.01 µF 10 10 100 COUT = 10 µF CNR = 0.01 µF 10 1k 10k 100k Frequency (Hz) Figure 12. 6 60 30 20 0 IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 Submit Documentation Feedback 1M 10M G004 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M G005 Figure 13. Copyright © 2012, Texas Instruments Incorporated TPS799L www.ti.com SBVS191 – APRIL 2012 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. POWER-SUPPLY REJECTION RATIO vs FREQUENCY (VIN = 5.95 V) TOTAL NOISE vs CNR (VIN = 6 V) 50 100 IOUT = 1 mA IOUT = 100 mA IOUT = 250 mA 90 46 Total Noise (µVrms) 80 PSRR (dB) 70 60 50 40 30 38 34 20 IOUT = 1 mA COUT = 2.2 µF COUT = 10 µF CNR = none 10 0 42 10 100 1k 10k 100k Frequency (Hz) 1M 10M 30 0.01 0.1 Figure 14. Figure 15. TOTAL NOISE vs COUT (VIN = 6 V) INRUSH CURRENT AT EN TURN-ON (CIN = COUT = 20 µF, IOUT = 47 mA) 48 Total Noise (µVrms) 1 CNR (µF) G006 10 G008 IN (2 V/div) 46 EN (1 V/div) VOUT (1 V/div) 44 Input Current (500 mA/div) 42 IOUT = 1 mA CNR = 0.01 µF 40 0 5 10 15 COUT (µF) Figure 16. Copyright © 2012, Texas Instruments Incorporated 20 25 Time (100 ms/div) G007 Figure 17. Submit Documentation Feedback 7 TPS799L SBVS191 – APRIL 2012 www.ti.com APPLICATION INFORMATION The TPS799Lxx family of LDO regulators combines the high performance required of many RF and precision analog applications with ultralow current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is provided to bypass noise generated by the bandgap reference and to improve PSRR, while a quick-start circuit quickly charges this capacitor at start-up. The combination of high performance and low ground current also make these devices an excellent choice for portable applications. All versions have thermal and overcurrent protection, and are fully specified from –40°C to +125°C. The TPS799Lxx family also features inrush current protection with an EN toggle start-up, and overshoot detection at the output. When the EN toggle is used to start the device, current limit protection is immediately activated, restricting the inrush current to the device (see Figure 17). If voltage at the output overshoots 5% from the nominal value, a pull-down resistor reduces the voltage to normal operating conditions (see Figure 1). Figure 18 shows the basic circuit connections. Optional input capacitor. May improve source impedance, noise, or PSRR. VIN VOUT OUT TPS799Lxx VEN GND NR 2.2 mF Ceramic Optional bypass capacitor to reduce output noise and increase PSRR. Figure 18. Typical Application Circuit INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability. 8 OUTPUT NOISE In most LDOs, the bandgap is the dominant noise source. If a noise-reduction capacitor (CNR) is used with the TPS799Lxx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF noise reduction capacitor. To further optimize noise, equivalent series resistance of the output capacitor can be set to approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing total output noise by up to 10%. Noise can be referred to the feedback point; with CNR = 0.01 μF total noise is approximately given by Equation 1: 10.5mVRMS VN = x VOUT V (1) BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE IN EN The TPS799Lxx is designed to be stable with standard ceramic capacitors with values of 2.2 μF or greater. X5R and X7R type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be < 1.0 Ω. Submit Documentation Feedback To improve ac performance (such as PSRR, output noise, and transient response), design the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, connect the bypass capacitor directly to the GND pin of the device. INTERNAL CURRENT LIMIT The TPS799Lxx internal current limit helps protect the regulator during fault conditions. In current limit mode, the output sources a fixed amount of current that is largely independent of the output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time. The PMOS pass element in the TPS799Lxx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited; therefore, if extended reverse voltage operation is anticipated, external limiting may be required. SHUTDOWN The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. Copyright © 2012, Texas Instruments Incorporated TPS799L www.ti.com SBVS191 – APRIL 2012 DROPOUT VOLTAGE TRANSIENT RESPONSE The TPS799Lxx uses a PMOS pass transistor to achieve a low dropout voltage. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and rDS(on) of the PMOS pass element is the input-to-output resistance. Because the PMOS device behaves like a resistor in dropout, VDO approximately scales with the output current. As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude, but increases the duration of the transient response. The transient response of the TPS799Lxx is enhanced by an active pull-down device that engages when the output overshoots by approximately 5% or more when the device is enabled. When enabled, the pull-down device behaves like a 350-Ω resistor to ground. As with any linear regulator, PSRR degrades as (VIN – VOUT) approaches dropout. This effect is shown in Figure 9 through Figure 14 in the Typical Characteristics section. START-UP The TPS799Lxx uses a start-up circuit to quickly charge the noise reduction capacitor, CNR, if present (see Functional Block Diagrams, Figure 1). This circuit allows for the combination of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate for this configuration. Note that for fastest start-up, apply VIN first, and then drive the enable pin (EN) high. If EN is tied to IN, start-up is somewhat slower. The start-up switch is closed for approximately 135 μs. To ensure that CNR is fully charged during start-up, use a 0.01-μF or smaller capacitor. Copyright © 2012, Texas Instruments Incorporated UNDERVOLTAGE LOCKOUT (UVLO) The TPS799Lxx uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 50 μs in duration. MINIMUM LOAD The TPS799Lxx is stable with no output load. To meet the specified accuracy, a minimum load of 500 μA is required. With loads less than 500 μA at junction temperatures near +125°C, the output can drift up enough to cause the output pull-down device to turn on. The output pull-down device limits voltage drift to 5% typically; however, ground current can increase by approximately 50 μA. In typical applications, the junction cannot reach high temperatures at light loads because there is no noticeable dissipated power. The specified ground current is then valid at no load in most applications. Submit Documentation Feedback 9 TPS799L SBVS191 – APRIL 2012 www.ti.com THERMAL INFORMATION THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. front of this data sheet. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heatdissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current time the voltage drop across the output pass element, as shown in Equation 2: P D + ǒVIN*V OUTǓ @ I OUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TPS799Lxx are available from the Texas Instruments' web site at www.ti.com. The YZY package dimensions are shown in Figure 19. The internal protection circuitry of the TPS799Lxx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the device into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the head from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information table near the 10 Submit Documentation Feedback Figure 19. TPS799L57YZY Package Dimensions (in mm) Copyright © 2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 17-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS799L57YZYR ACTIVE DSBGA YZY 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS799L57YZYT ACTIVE DSBGA YZY 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS799L57YZYR DSBGA YZY 5 3000 180.0 8.4 TPS799L57YZYT DSBGA YZY 5 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.08 1.45 0.61 4.0 8.0 Q1 1.08 1.45 0.61 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS799L57YZYR DSBGA YZY 5 3000 210.0 185.0 35.0 TPS799L57YZYT DSBGA YZY 5 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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