TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 3-A, Fast-Transient, Low-Dropout Voltage Regulator FEATURES 1 • • • • • • Wireless Infrastructure: SerDes, FPGA, DSP™ RF Components: VCO, ADC, DAC, LVDS Set-Top Boxes: Amplifier, ADC, DAC, FPGA, DSP Wireless LAN, Bluetooth® PCs and Printers Audio and Visual 1.5 V IN The TPS7A7300 low-dropout (LDO) voltage regulator is designed for applications seeking very-low dropout capability (240 mV at 3A) with an input voltage from 1.5 V to 6.5 V. The TPS7A7300 offers an innovative, user-configurable, output-voltage setting from 0.9 V to 3.5 V, eliminating external resistors and any associated error. The TPS7A7300 has very fast load-transient response, is stable with ceramic output capacitors, and supports a better than 2% accuracy over line, load, and temperature. A soft-start pin allows for an application to reduce inrush into the load. Additionally, an open-drain, power-good signal allows for sequencing power rails. The TPS7A7300 is available in a 5-mm × 5-mm, 20-pin QFN package. 6 3 Output Current Slew Rate: 1A/µs 5 4 Output Current 5.5V to 5.0V 3.3V to 3.0V 3.0V to 2.5V 2.5V to 1.8V 2 1.8V to 1.5V 3 2 1 Output Current (A) APPLICATIONS DESCRIPTION Output Voltage (V) • Low Dropout Voltage: 240 mV at 3A • VIN Range: 1.5 V to 6.5 V • Configurable Fixed VOUT Range: 0.9 V to 3.5 V Adjustable VOUT Range: 0.9 V to 5.0 V • Very Good Load and Line Transient Response • Stable with Ceramic Output Capacitor • 2% Accuracy over Line, Load, and Temperature • Programmable Softstart • Power Good (PG) Output • 5-mm × 5-mm QFN-20 Package 234 PG 1 CIN 1.5V to 1.2V TPS7A7300 1.5V to 1.0V 0 EN OUT SS CSS SNS FB Optional GND 50mV 100mV 1.2 V = 0.5 Vref + 100 mV COUT + 200 mV + 400 mV 0 Time (100µs/div) G312 Load Transient Response with Seven Different Results: 1.5 VIN to 1.0 VOUT, 1.5 VIN to 1.2 VOUT, 1.8 VIN to 1.5 VOUT, 2.5 VIN to 1.8 VOUT, 3.0 VIN to 2.5 VOUT, 3.3 VIN to 3.0 VOUT, and 5.5 VIN to 5.0 VOUT 1.6V 200mV 400mV 800mV Typical Application 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DSP is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT Description TPS7A7300yyyz (1) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage MIN MAX UNIT IN, PG, EN –0.3 +7.0 V SS, FB, SNS, OUT –0.3 VIN + 0.3 (2) V –0.3 VOUT + 0.3 V 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V OUT Current PG (sink current into IC) Temperature Electrostatic Discharge Rating (3) (1) (2) (3) 2 Internally limited A 5 mA Operating virtual junction, TJ –55 +150 Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM, JESD22-A114A) Charged device model (CDM, JESD22-C101B.01) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VIN + 0.3 V or +7.0 V, whichever is smaller. ESD testing is performed according to the respective JESD22 JEDEC standard. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 THERMAL INFORMATION TPS7A7300 (3) THERMAL METRIC (1) (2) RGW (QFN) UNITS 20 PINS Junction-to-ambient thermal resistance (4) θJA (5) 35.7 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (6) 15.2 ψJT Junction-to-top characterization parameter (7) 0.4 ψJB Junction-to-board characterization parameter (8) 15.4 θJCbot Junction-to-case (bottom) thermal resistance (9) 3.8 (1) (2) (3) (4) (5) (6) (7) (8) (9) 33.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 4 × 4 thermal via array. (b) Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), 1.425 V ≤ VIN ≤ 6.5 V, VIN ≥ VOUT(TARGET) + 0.3 V or VIN ≥ VOUT(TARGET) + 0.7 V (1) (2), OUT connected to 50 Ω to GND (3),VEN = 1.1 V, COUT = 10 μF, CSS = 10 nF, and PG pin pulled up to VIN with 100 kΩ, 27 kΩ ≤ R2 ≤ 33 kΩ for adjustable configuration (4), unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER VIN Input voltage range V(SS) SS pin voltage TEST CONDITIONS VOUT Output voltage accuracy (5) (6) Fixed with voltage setting pins 0.9 3.5 Adjustable, 25 mA ≤ IOUT ≤ 3 A –2.0 +2.0 Fixed, 25 mA ≤ IOUT ≤ 3 A –3.0 +3.0 IOUT = 25 mA Load regulation 25 mA ≤ IOUT ≤ 3 A (7) Output current limit 0.01 V V % %/V 0.1 %/A VOUT ≤ 3.3 V, IOUT = 3 A, V(FB) = GND 240 mV 3.3 V < VOUT, IOUT = 3 A, V(FB) = GND 700 mV 4.2 A VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V 3.2 Full load, IOUT = 3 A GND pin current UNIT V 5.0 Line regulation I(GND) 6.5 0.9 ΔVO(ΔIO) I(LIM) MAX Adjustable with external feedback resistors ΔVO(ΔVI) Dropout voltage TYP 0.5 Output voltage range V(DO) MIN 1.425 3.7 3.7 Minimum load, VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA mA 4 mA 5 μA ±0.1 μA 0 0.5 V 1.1 6.5 V 0.96VOUT V Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V 0.1 I(EN) EN pin current VIL(EN) EN pin low-level input voltage (disable device) VIH(EN) EN pin high-level input voltage (enable device) VIT(PG) PG pin threshold For the direction PG↓ with decreasing VOUT Vhys(PG) PG pin hysteresis For PG↑ VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current into device) Ilkg(PG) PG pin leakage current VOUT > VIT(PG), V(PG) = 6.5 V I(SS) SS pin charging current V(SS) = GND, VIN = 3.3 V Vn Output noise voltage BW = 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.2 V, IOUT = 3 A 39.46 μVRMS Tsd Thermal shutdown temperature Shutdown, temperature increasing +160 °C Reset, temperature decreasing +140 °C TJ Operating junction temperature (1) (2) (3) (4) (5) (6) (7) 4 VIN = 6.5 V, V(EN) = 0 V and 6.5 V 0.85VOUT 0.9VOUT 0.02VOUT 3.5 –40 5.1 V 0.4 V 1 μA 7.2 μA +125 °C When VOUT ≤ 3.5 V, VIN ≥ (VOUT + 0.3 V) or 1.425 V, whichever is greater; when VOUT > 3.5 V, VIN ≥ (VOUT + 0.7 V). VOUT(TARGET) is the calculated target VOUT value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V in fixed configuration, or the expected VOUT value set by external feedback resistors in adjustable configuration. This 50-Ω load is disconnected when the test conditions specify an IOUT value. R2 is the bottom-side of the feedback resistor between the FB pin and GND. See Figure 40 for details. When the TPS7A7300 is connected to external feedback resistors at the FB pin, external resistor tolerances are not included. The TPS7A7300 is not tested at VOUT = 0.9 V, 2.7 V ≤ VIN ≤ 6.5 V, and 500 mA ≤ IOUT ≤ 3 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package. V(DO) is not defined for output voltage settings below 1.2 V. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAM Current Limit IN Charge Pump SS CSS UVLO 0.5-V Reference OUT Thermal Protection PG 700-µs Delay 1.2-V Reference 70 kΩ Optional 0.45 V 50 kΩ 50 kΩ SNS 32R FB Hysteresis EN 320R GND 50mV 160R 80R 40R 20R 100mV 200mV 400mV 800mV 10R 1.6V NOTE: 320R = 1.024 MΩ (that is, 1R = 3.2 kΩ). Figure 1. Functional Block Diagram Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com PIN CONFIGURATIONS OUT OUT GND IN IN 20 19 18 17 16 RGW PACKAGE 5-mm × 5-mm QFN-20 (TOP VIEW) OUT 1 15 IN SNS 2 14 EN FB 3 13 SS PG 4 12 NC 50mV 5 11 1.6V 10 800mV 8 GND 9 7 200mV 400mV 6 100mV Thermal Pad PIN DESCRIPTIONS NAME 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V RGW Output voltage setting pins. These pins should be connected to ground or left floating. Connecting these pins to 5, 6, 7, ground increases the output voltage by the value of the pin name; multiple pins can be simultaneously connected to 9, 10, 11 GND to select the desired output voltage. Leave these pins floating (open) when not in use. See the USERCONFIGURABLE OUTPUT VOLTAGE section for more details. EN 14 Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. See the ENABLE AND SHUTDOWN THE DEVICE section for more details. FB 3 Output voltage feedback pin. Connected to the error amplifier. See the USER-CONFIGURABLE OUTPUT VOLTAGE and TRADITIONAL ADJUSTABLE CONFIGURATION sections for more details. GND 8, 18 IN 15, 16, 17 NC 12 OUT 1, 19, 20 PG 4 Active-high power good pin. An open-drain output that indicates when the output voltage reaches 90% of the target. See POWER GOOD for more details. SNS 2 Output voltage sense input pin. See the USER-CONFIGURABLE OUTPUT VOLTAGE and TRADITIONAL ADJUSTABLE CONFIGURATION sections for more details. SS 13 Soft-start pin. Leaving this pin open provides soft-start of the default setting. Connecting an external capacitor between this pin and the ground enables the soft-start function by forming an RCdelay circuit in combination with the integrated resistance on the silicon. See the SOFT-START section for more details. Thermal Pad 6 DESCRIPTION Ground pin. Unregulated supply voltage pin. It is recommended to connect an input capacitor to this pin. See INPUT CAPACITOR REQUIREMENTS for more details. Not internally connected. The NC pin is not connected to any electrical node. It is strongly recommended to connect this pin and the thermal pad to a large-area ground plane. See the Power Dissipation section for more details. Regulated output pin. A 4.7-μF or larger capacitance is required for stability. See OUTPUT CAPACITOR REQUIREMENTS for more details. It is strongly recommended to connect the thermal pad to a large-area ground plane. If available, connect an electrically-floating, dedicated thermal plane to the thermal pad as well. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. LOAD REGULATION (0.9 V, Adjustable) 0.927 0.909 Y−axis scale is 1%Vout/div Y−axis scale is 1%Vout/div 5.1 Output Voltage (V) Output Voltage (V) 5.15 − 40°C 0°C 25°C 85°C 105°C 125°C 0.918 LOAD REGULATION (5.0 V, Adjustable) 0.9 0.891 0.882 0.873 0.5 1 1.5 2 Output Current (A) 2.5 5 − 40°C 0°C 25°C 85°C 105°C 125°C 4.95 4.9 VIN = 1.425 V R1 = 24.1 kΩ, R2 = 30.1 kΩ 0 5.05 4.85 3 0 Figure 3. LOAD REGULATION (0.9 V, Fixed by Setting Pins) LOAD REGULATION (3.5 V, Fixed by Setting Pins) 3.605 − 40°C 0°C 25°C 85°C 105°C 125°C 3.57 Output Voltage (V) Output Voltage (V) 0.918 0.909 0.9 0.873 − 40°C 0°C 25°C 85°C 105°C 125°C 0 0.5 VIN = 1.425 V VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 1 1.5 2 Output Current (A) 2.5 3.535 250 0 0.5 1 G202 VIN = 1.5 V FB = GND 50 300 250 1.5 2 Output Current (A) Figure 6. Copyright © 2012, Texas Instruments Incorporated G205 200 150 100 IOUT = 3 A FB = GND and plot VIN − VOUT 50 1 3 − 40°C 0°C 25°C 85°C 105°C 125°C 350 100 0.5 2.5 DROPOUT VOLTAGE vs TEMPERATURE 150 0 1.5 2 Output Current (A) Figure 5. 200 0 VIN = 3.8 V VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND; 50mV, 100mV pins open Y−axis scale is 1%Vout/div 3.395 3 Dropout Voltage (mV) Dropout Voltage (mV) 300 G005 3.43 400 − 40°C 0°C 25°C 85°C 105°C 125°C 3 3.465 DROPOUT VOLTAGE vs OUTPUT CURRENT 350 2.5 3.5 Figure 4. 400 1.5 2 Output Current (A) Figure 2. Y−axis scale is 1%Vout/div 0.882 1 G002 0.927 0.891 0.5 VIN = 5.3 V R1 = 271 kΩ, R2 = 30.1 kΩ 2.5 3 G012 0 1 2 3 4 Input Voltage (V) 5 5.5 G015 Figure 7. Submit Documentation Feedback 7 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. LINE REGULATION (0.9 V, Adjustable) 0.927 0.909 Y−axis scale is 1%Vout/div Y−axis scale is 1%Vout/div 5.1 Output Voltage (V) Output Voltage (V) 5.15 − 40°C 0°C 25°C 85°C 105°C 125°C 0.918 LINE REGULATION (5.0 V, Adjustable) 0.9 0.891 0.882 0.873 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 5 − 40°C 0°C 25°C 85°C 105°C 125°C 4.95 4.9 IOUT = 25 mA R1 = 24.1 kΩ, R2 = 30.1 kΩ 1 5.05 4.85 6.5 5 LINE REGULATION (0.9 V, Fixed by Setting Pins) LINE REGULATION (3.5 V, Fixed by Setting Pins) 3.605 − 40°C 0°C 25°C 85°C 105°C 125°C Output Voltage (V) Output Voltage (V) 3.57 0.909 0.9 − 40°C 0°C 25°C 85°C 105°C 125°C 1 1.5 2 IOUT = 25 mA VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 3.465 3.395 6.5 5 5.5 6 Input Voltage (V) G206 6.5 G207 Figure 10. Figure 11. OUTPUT VOLTAGE: ACTUAL vs PIN-SETTING OUTPUT VOLTAGE: ACTUAL (Normalized) vs PIN-SETTING 1 Error in Actual Output Voltage (%) Actual Output Voltage (V) 3.5 Y−axis scale is 1%Vout/div 3.2 2.8 2.4 2 1.6 1.2 VIN = 4 V IOUT = 50 mA 1.2 1.6 2 2.4 VOUT(TARGET) (V) Figure 12. 8 3.535 IOUT = 25 mA VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND; 50mV, 100mV pins open 3.43 3.6 0.8 0.8 G007 Figure 9. 0.918 0.873 6.5 Figure 8. Y−axis scale is 1%Vout/div 0.882 5.5 6 Input Voltage (V) G006 0.927 0.891 IOUT = 25 mA R1 = 271 kΩ, R2 = 30.1 kΩ Submit Documentation Feedback 2.8 3.2 3.6 G020 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 VIN = 4 V IOUT = 50 mA −0.8 −1 0.8 1.2 1.6 2 2.4 VOUT(TARGET) (V) 2.8 3.2 3.6 G021 Figure 13. Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. GND PIN CURRENT vs OUTPUT CURRENT − 40°C 0°C 25°C 85°C 105°C 125°C Ground Current (mA) 4 3 2 VIN = 1.8 V VOUT(TARGET) = 1.5 V 200mV, 800mV pins to GND 50mV, 100mV, 200mV, 400mV pins open 0 0.5 1 1.5 2 Output Current (A) 2.5 2 0 3 1 2 3 5.5 G033 4 3 2 VIN = 4 V VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND 50mV, 100mV pins open 1 2 6.5 5 1 1.5 6 EN = GND 50−Ω resistor between OUT and GND 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 0 6.5 0 G032 1 1.5 2 2.5 Forced Output Voltage (V) 3 3.5 G042 POWER-GOOD PIN DRIVE CAPABILITY 1 VOUT(TARGET) = 1.2 V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open 50−Ω resistor between OUT and GND VIN = 1.5 V, − 40 °C VIN = 1.5 V, 25 °C VIN = 1.5 V, 125 °C VIN = 6.5 V, − 40 °C VIN = 1.5 V, 25 °C VIN = 1.5 V, 125 °C 0.8 PG Pin Voltage (V) VIN=1.5V VIN=6.5V 0.5 Figure 17. POWER-GOOD THRESHOLD VOLTAGE vs TEMPERATURE 94 93 92 91 90 89 88 87 86 85 84 −50 5 CURRENT LIMIT vs OUTPUT VOLTAGE (Foldback) 4 96 95 3 3.5 4 4.5 Input Voltage (V) GND PIN CURRENT IN SHUTDOWN vs TEMPERATURE − 40°C 0°C 25°C 85°C 105°C 125°C 1 2.5 Figure 15. Figure 16. Threshould Voltage (%VOUT) 1.5 G031 Figure 14. 5 0 3 IOUT = 25 mA VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 1 Current Limit (A) 0 − 40°C 0°C 25°C 85°C 105°C 125°C 4 1 Shutdown Ground Current (µA) GND PIN CURRENT vs INPUT VOLTAGE 5 Ground Current (mA) 5 0.6 VOUT(TARGET) = 1.2 V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open 50−Ω resistor from OUT to GND Spec limit defined at 1−mA. 0.4 0.2 −25 0 25 50 Temperature (°C) Figure 18. Copyright © 2012, Texas Instruments Incorporated 75 100 125 G050 0 0 0.5 1 1.5 Forced PG Pin Current (mA) 2 G051 Figure 19. Submit Documentation Feedback 9 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. NOISE SPECTRAL DENSITY BY EXTERNAL CAPACITORS 10 Output Spectral Noise Density (µV/ Hz) Output Spectral Noise Density (µV/ Hz) NOISE SPECTRAL DENSITY BY OUTPUT VOLTAGE VOUT(TARGET) = 0.9 V VOUT(TARGET) = 1.2 V VOUT(TARGET) = 3.3 V 1 VIN = VOUT(TARGET) + 0.3 V IOUT = 3 A 100 Hz to 100 kHz RMS Noise 0.9 V: 38.88 µVRMS 1.2 V: 39.46 µVRMS 3.3 V: 75.59 µVRMS 0.1 0.01 10 100 1k Frequency (Hz) 10k 100k 10 VIN = 1.8 V, IOUT = 1 A VOUT(TARGET) = 1.5 V 200mV, 800mV pins to GND 50mV, 100mV, 400mV, 1.6V pins open 1 CSS = 100nF, COUT = 100µF CSS = 100nF, COUT = 10µF CSS = 10nF, COUT = 100µF CSS = 10nF, COUT = 10µF CSS = 1nF, COUT = 100µF CSS = 1nF, COUT = 10µF 0.1 0.01 10 100 1k Frequency (Hz) G062 Figure 20. 10k 100k G063 Figure 21. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 100 VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 90 80 PSRR (dB) 70 VIN=3.8V, IOUT=0.1A VIN=3.6V, IOUT=0.1A 60 50 40 30 VIN=3.6V, IOUT=3A 20 10 0 VIN=3.8V, IOUT=3A 10 100 1k 10k 100k Frequency (Hz) 1M 10M G072 Figure 22. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. LOAD TRANSIENT RESPONSE (VOUT = 1.2 V) 1.2 6 4 Output Voltage 1.1 2 8 Output Current Slew Rate: 1A/µs VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3.4 3.3 4 Output Voltage 3.2 2 Output Current Output Current 1 0 Time (100µs/div) 3.1 0 Time (100µs/div) G315 Figure 23. LINE TRANSIENT RESPONSE POWER-UP/POWER-DOWN (IN = EN) Voltage (V) VIN 4 Voltage (V) IOUT=1A, VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 4.2 3.8 3.6 VOUT 3.4 3.2 Time (20 µs/div) 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 VIN VOUT Time (2 ms/div) G300 TURN-ON RESPONSE (IN = EN) TURN-OFF RESPONSE (IN = EN) 5 4.5 4 4 VIN 3.5 Voltage (V) Voltage (V) IN = EN 50−Ω resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 4.5 VIN 3.5 3 2.5 VOUT 2 0.5 G301 Figure 26. 5 1 VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 50−Ω resistor between OUT and GND Figure 25. 1.5 G318 Figure 24. 4.6 4.4 6 Output Current (A) 1.3 3.5 Output Voltage (V) 8 Output Current Slew Rate: 1A/µs VOUT(TARGET)=1.2V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open Output Current (A) Output Voltage (V) 1.4 LOAD TRANSIENT RESPONSE (VOUT = 3.3 V) IN = EN 50−Ω resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3 2.5 2 VOUT 1.5 1 0.5 0 0 Time (1 ms/div) Figure 27. Copyright © 2012, Texas Instruments Incorporated G302 Time (1 ms/div) G303 Figure 28. Submit Documentation Feedback 11 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-kΩ pull-up resistor, unless otherwise noted. EN PULSE ON RESPONSE (Over Stable VIN) EN PULSE OFF RESPONSE (Over Stable VIN) 5 5 4.5 4.5 VOUT VIN 4 3.5 3 Voltage (V) 3.5 Voltage (V) VIN 4 VEN 2.5 2 1.5 0.5 VOUT VEN 2 50−Ω resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 1.5 50−Ω resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 1 3 2.5 1 0.5 0 0 Time (1 ms/div) Time (1 ms/div) G304 Figure 29. SOFT-START DELAY vs CSS (Enlarged View) SOFT-START DELAY vs CSS (Reduced View) 5 5 VOUT (CSS=0F) 4.5 4 VIN VOUT(TARGET) = 3.3 V 50−Ω resistor from OUT to GND 4.5 4 VIN VOUT (CSS=0F) 3.5 Voltage (V) Voltage (V) 3.5 3 2.5 G305 Figure 30. VEN VOUT (CSS=10nF) 2 VOUT (CSS=100nF) 1.5 3 2.5 VOUT (CSS=10nF) VEN VOUT (CSS=100nF) 2 1.5 1 VOUT (CSS=1µF) 1 VOUT (CSS=1µF) 0.5 VOUT(TARGET) = 3.3 V 50−Ω resistor from OUT to GND 0.5 0 0 Time (5 ms/div) Time (50 ms/div) G306 Figure 31. SOFT-START DELAY vs CSS 1000 Softstart Delay (ms) G307 Figure 32. 0%VOUT to 90%VOUT 50−Ω resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 100 10 1 0.1 1 10 100 CSS (nF) 1000 G308 Figure 33. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 APPLICATION INFORMATION OVERVIEW The TPS7A7300 belongs to a family of new-generation LDO regulators that uses innovative circuitry to offer very-low dropout voltage along with the flexibility of a programmable output voltage. The dropout voltage for this LDO regulator family is 0.24 V at 3 A. This voltage is ideal for making the TPS7A7300 into a point-of-load (POL) regulator because 0.24 V at 3 A is lower than any voltage gap among the most common voltage rails: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V. This device offers a fully userconfigurable output voltage setting method. The TPS7A7300 output voltage can be programmed to any target value from 0.9 V to 3.5 V in 50-mV steps. Another big advantage of using the TPS7A7300 is the wide range of available operating input voltages: from 1.5 V to 6.5 V. The TPS7A7300 also has very good line and load transient response. All these features allow the TPS7A7300 to meet most voltage-regulator needs for under-6-V applications, using only one device so that less time is spent on inventory control. Texas Instruments also offers different output current ratings with other family devices: the TPS7A7100 (1 A) and TPS7A7200 (2 A). USER-CONFIGURABLE OUTPUT VOLTAGE IN IN GND OUT OUT IN IN GND OUT OUT Unlike traditional LDO devices, the TPS7A7300 comes with only one orderable part number; there is no adjustable or fixed output voltage option. The output voltage of the TPS7A7300 is selectable in accordance with the names given to the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V. For each pin connected to the ground, the output voltage setting increases by the value associated with that pin name, starting from the value of the reference voltage of 0.5 V; floating the pin(s) has no effect on the output voltage. Figure 34 through Figure 39 show examples how to program the output voltages. OUT IN OUT IN SNS EN SNS EN FB SS FB SS PG NC PG NC Thermal Pad Thermal Pad 1.6V 1.6V Optional 800mV GND 400mV 100mV 200mV 50mV Optional 800mV GND 400mV 200mV 100mV 50mV VIN VIN FB FB OUT OUT SNS SNS 0.5 V 0.5 V 3.2R 3.2R FB FB 32R 16R 8R 4R 2R 1R 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 0.9 V = 0.5 V + 400 mV 0.5 V is Vref VOUT = 0.5 V ´ (1 + 3.2R/4R) Figure 34. 0.9-V Configuration Copyright © 2012, Texas Instruments Incorporated VOUT = 1.2 V = 0.5 V + 100 mV + 200 mV + 400 mV 0.5 V is Vref VOUT = 0.5 V ´ (1 + 3.2R/2.29R) 2.29R is parallel resistance of 16R, 8R, and 4R. Figure 35. 1.2-V Configuration Submit Documentation Feedback 13 TPS7A7300 IN IN GND OUT OUT IN www.ti.com IN GND OUT OUT SBVS190B – MARCH 2012 – REVISED APRIL 2012 OUT IN OUT IN SNS EN SNS EN FB SS FB SS PG NC PG NC Thermal Pad Thermal Pad 1.6V 1.6V Optional 800mV GND 400mV 100mV 200mV 50mV Optional 800mV GND 400mV 200mV 100mV 50mV VIN VIN FB FB OUT OUT SNS SNS 0.5 V 0.5 V 3.2R 3.2R FB FB 32R 16R 8R 4R 2R 1R 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 1.8 V = 0.5 V + 100 mV + 400 mV + 800 mV VOUT = 2.5 V = 0.5 V + 400 mV + 1.6 V 0.5 V is Vref 0.5 V is Vref 1.23R is parallel resistance of 16R, 4R, and 2R. VOUT = 0.5 V ´ (1 + 3.2R/0.8R) 0.8R is parallel resistance of 4R and 1R. IN IN GND OUT Figure 37. 2.5-V Configuration IN IN GND OUT OUT Figure 36. 1.8-V Configuration OUT VOUT = 0.5 V ´ (1 + 3.2R/1.23R) OUT IN OUT IN SNS EN SNS EN FB SS FB SS PG NC PG NC Thermal Pad Thermal Pad 1.6V 1.6V Optional 800mV GND 400mV 100mV 200mV 50mV Optional 800mV GND 400mV 200mV 100mV 50mV VIN VIN FB FB OUT OUT SNS SNS 0.5 V 0.5 V 3.2R 3.2R FB 16R 8R 4R 2R 1R 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 3.3 V = 0.5 V + 400 mV + 800 mV + 1.6 V 0.5 V is Vref VOUT = 0.5 V ´ (1 + 3.2R/0.571R) VOUT = 3.5 V = 0.5 V + 200 mV + 400 mV + 800 mV + 1.6 V 0.5 V is Vref 0.571R is parallel resistance of 4R, 2R, and 1R. Figure 38. 3.3-V Configuration 14 FB 32R Submit Documentation Feedback VOUT = 0.5 V ´ (1 + 3.2R/0.533R) 0.533R is parallel resistance of 8R, 4R, 2R, and 1R. Figure 39. 3.5-V Configuration Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 See Table 1 for a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.9 V to 3.5 V in 50-mV steps. Figure 12 and Figure 13 shows this output voltage programming performance. NOTE Any output voltage setting that is not listed in Table 1 is not covered in the Electrical Characteristics. For output voltages greater than 3.5 V, use a traditional adjustable configuration (see the TRADITIONAL ADJUSTABLE CONFIGURATION section). Table 1. User Configurable Output Voltage Setting VOUT(TARGET) (V) 50mV 1.6V VOUT(TARGET) (V) 0.90 open open open GND 0.95 GND open open GND open open open open 1.00 open GND open 1.05 GND GND open GND open GND open 1.10 open open GND GND 1.15 GND open GND 1.20 1.25 open GND GND GND 1.30 open 1.35 1.40 1.45 100mV 200mV 400mV 800mV 50mV 100mV 200mV 400mV 800mV 1.6V 2.25 GND GND open open open GND 2.30 open open GND open open GND open 2.35 GND open GND open open GND open 2.40 open GND GND open open GND open open 2.45 GND GND GND open open GND GND open open 2.50 open open open GND open GND GND GND open open 2.55 GND open open GND open GND GND GND open open 2.60 open GND open GND open GND open open open GND open 2.65 GND GND open GND open GND GND open open open GND open 2.70 open open GND GND open GND open GND open open GND open 2.75 GND open GND GND open GND GND GND open open GND open 2.80 open GND GND GND open GND 1.50 open open GND open GND open 2.85 GND GND GND GND open GND 1.55 GND open GND open GND open 2.90 open open open open GND GND 1.60 open GND GND open GND open 2.95 GND open open open GND GND 1.65 GND GND GND open GND open 3.00 open GND open open GND GND 1.70 open open open GND GND open 3.05 GND GND open open GND GND 1.75 GND open open GND GND open 3.10 open open GND open GND GND 1.80 open GND open GND GND open 3.15 GND open GND open GND GND 1.85 GND GND open GND GND open 3.20 open GND GND open GND GND 1.90 open open GND GND GND open 3.25 GND GND GND open GND GND 1.95 GND open GND GND GND open 3.30 open open open GND GND GND 2.00 open GND GND GND GND open 3.35 GND open open GND GND GND 2.05 GND GND GND GND GND open 3.40 open GND open GND GND GND 2.10 open open open open open GND 3.45 GND GND open GND GND GND 2.15 GND open open open open GND 3.50 open open GND GND GND GND 2.20 open GND open open open GND Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com TRADITIONAL ADJUSTABLE CONFIGURATION For any output voltage target that is not supported in the USER-CONFIGURABLE OUTPUT VOLTAGE section, a traditional adjustable configuration with external-feedback resistors can be used with the TPS7A7300. Figure 40 shows how to configure the TPS7A7300 as an adjustable regulator with an equation and Table 2 lists recommended pairs of feedback resistor values. IN IN OUT GND OUT NOTE The bottom side of feedback resistor R2 in Figure 40 should be in the range of 27 kΩ to 33 kΩ in order to maintain the specified regulation accuracy. OUT IN R1 SNS EN R2 FB SS PG NC Thermal Pad 1.6V 400mV Optional 800mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V R1 R2 VOUT = (R1 + R2 ) x 0.500 R2 Figure 40. Traditional Adjustable Configuration with External Resistors Table 2. Recommended Feedback-Resistor Values 16 E96 SERIES R40 SERIES VOUT(TARGET) (V) R1 (kΩ) R2 (kΩ) R1 (kΩ) R2 (kΩ) 1.00 30.1 30.1 30.0 30.0 1.20 39.2 28.0 43.7 31.5 1.50 61.9 30.9 60.0 30.0 1.80 80.6 30.9 80.0 30.7 1.90 86.6 30.9 87.5 31.5 2.50 115 28.7 112 28.0 3.00 147 29.4 150 30.0 3.30 165 29.4 175 31.5 5.00 280 30.9 243 27.2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 DROPOUT VOLTAGE The TPS7A7300 maintains its output voltage regulation with a dropout voltage (VIN – VOUT) greater than 0.24 V under the test conditions specified in the Electrical Characteristics. In most power distribution tree (system) designs, the TPS7A7300 can be used with a 0.3-V difference in the common voltage rails (for example, from 3.3 VIN to 3.0 VOUT, from 1.8 VIN to 1.5 VOUT, or from 1.5 VIN to 1.2 VIN). INPUT CAPACITOR REQUIREMENTS As a result of its very fast transient response and low-dropout operation support, it is necessary to reduce the line impedance at the input pin of the TPS7A7300. The line impedance depends heavily on various factors, such as wire (PCB trace) resistance, wire inductance, and/or output impedance of the upstream voltage supply (power supply to the TPS7A7300). Therefore, a specific value for the input capacitance cannot be recommended until the previously listed factors are finalized. In addition, simple usage of large input capacitance is known to form unwanted LC resonance in combination with input wire inductance. For example, a 5-nH inductor and a 10-µF input capacitor form an LC filter that has a resonance at 712 kHz. This value of 712 kHz is well inside the bandwidth of the TPS7A7300 control loop. The best guideline is to use a capacitor of up to 1 µF with well-designed wire connections (PCB layout) to the upstream supply. In case it is difficult to optimize the input line, use a large tantalum capacitor in combination with a good-quality, low-ESR, 1-µF ceramic capacitor. OUTPUT CAPACITOR REQUIREMENTS The TPS7A7300 is designed to be stable with standard ceramic capacitors with capacitance values greater than or equal to 4.7 μF. The TPS7A7300 is evaluated using an X5R-type, 10-μF ceramic capacitor. X5R- and X7Rtype capacitors are highly recommended because they have minimal variation in value and ESR over temperature. Maximum ESR should be below 1.0 Ω. As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude, but increases duration of the transient response. UNDERVOLTAGE LOCK-OUT (UVLO) The TPS7A7300 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when the device powers on. As explained in the INPUT CAPACITOR REQUIREMENTS section, the input line impedance should be well-designed. SOFT-START The TPS7A7300 has a SS pin that provides a soft-start (slow start) function. By leaving the SS pin open, the TPS7A7300 performes a soft-start by its default setting. As shown in Figure 1, by connecting a capacitor between the SS pin and the ground, the CSS capacitor forms an RC pair together with the integrated 50-kΩ resistor. The RC pair operates as an RC-delay circuit for the soft-start together with the internal 700-µs delay circuit. The relationship between CSS and the soft-start time is shown in Figure 31 through Figure 33. CURRENT LIMIT The TPS7A7300 internal current limit circuitry protects the regulator during fault conditions. During a current limit event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any applications to use this current limit function as a part of expected normal operation. Extended periods of current limit operation degrade device reliability. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com ENABLE AND SHUTDOWN THE DEVICE The EN pin switches the enable and disable (shutdown) states of the TPS7A7300. A logic high input at the EN pin enables the device; a logic low input disables the device. When disabled, the device consumption current is reduced. POWER GOOD The TPS7A7300 has a power good function that works with the PG output pin. When the output voltage undershoots the threshold voltage VIT(PG) during normal operation, the PG open-drain output turns from a highimpedance state to a low-impedance state. When the output voltage exceeds the VIT(PG) threshold by an amount greater than the PG hysteresis, Vhys(PG), the PG open-drain output turns from a low-impedance state to highimpedance state. By connecting a pull-up resistor (usually between OUT and PG), any downstream device can receive an active-high enable logic signal. When setting the output voltage to less than 1.8 V and using a pull-up resistor between OUT and PG, depending on the downstream device specifications, the downstream device may not accept the PG output as a valid highlevel logic voltage. In such cases, put a pull-up resistor between IN and PG, not between OUT and PG. Figure 19 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is calculated using Figure 19, and is approximately 200 Ω. Any pull-up resistor greater than 10 kΩ works fine for this purpose. THERMAL INFORMATION Thermal Protection The thermal protection feature disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A7300 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A7300 into thermal shutdown degrades device reliability. Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 1: P D + ǒVIN * VOUTǓ I OUT (1) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 On the QFN (RGW) package, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 2: RqJA = +125°C - TA PD (2) Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 41. 120 100 qJA (°C/W) 80 60 qJA (RGW) 40 20 0 0 1 2 3 4 5 7 6 8 9 10 2 Board Copper Area (in ) 2 NOTE: θJA value at a board size of 9-in (that is, 3-in × 3-in) is a JEDEC standard. Figure 41. θJA vs Board Size Figure 41 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. Estimating Junction Temperature Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older θJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD YJB: TJ = TB + YJB · PD Where: PD is the power dissipation shown by Equation 2. TT is the temperature at the center-top of the IC package. TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 43 shows). (3) NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see Application Report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19 TPS7A7300 SBVS190B – MARCH 2012 – REVISED APRIL 2012 www.ti.com By looking at Figure 42, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 3 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 12 YJT and YJB (°C/W) 10 YJB (RGW) 8 6 4 2 YJT (RGW) 0 0 2 4 6 8 10 2 Board Copper Area (in ) Figure 42. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to Application Report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to Application Report SPRA953, IC Package Thermal Metrics, also available on the TI website. TB on PCB TT on top of IC 1mm (a) Example RGW (QFN) Package Measurement Figure 43. Measuring Points for TT and TB 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7300 www.ti.com SBVS190B – MARCH 2012 – REVISED APRIL 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2012) to Revision B • Page Changed Thermal Information table note (3b) copper coverage from 20% to 4% ............................................................... 3 Changes from Original (March 2012) to Revision A • Page Changed from product preview to production data ............................................................................................................... 1 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS7A7300RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS7A7300RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A7300RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS7A7300RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A7300RGWR VQFN RGW 20 3000 346.0 346.0 29.0 TPS7A7300RGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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