TS612 DUAL WIDE BAND OPERATIONAL AMPLIFIER WITH HIGH OUTPUT CURRENT ■ LOW NOISE : 3nV/√Hz, 1.2pA/√Hz ■ HIGH OUTPUT CURRENT : 200mA ■ VERY LOW HARMONIC AND INTERMODULATION DISTORTION ■ HIGH SLEW RATE : 40V/µs ■ SPECIFIED FOR 25Ω LOAD DESCRIPTION The TS612 is a dual operational amplifier featuring a high output current (200mA min.), large gain-bandwidth product (130MHz) and capable of driving a 25Ω load with a 160mA output current at ±6V power supply. D SO-20 Batwing (Plastic Micropackage) PIN CONNECTIONS (top view) This device is particularly intended for applications where multiple carriers must be amplified simultaneously with very low intermodulation products. 20 Vcc+ 1 19 Output 1 18 Vcc- 4 17 Vcc - Vcc - 5 16 Vcc - Vcc - 6 15 Vcc - Vcc - 7 14 Vcc - Non-Inverting input 2 8 13 GND Inverting input 2 9 Power Down 1 1 Inverting input 1 2 Non-inverting input 1 3 Vcc - APPLICATION ■ UPSTREAM line driver for Assymetric Digital The TS612 is housed in SO20 batwing plastic package for a very low thermal resistance. The TS612 is fitted out with Power Down function in order to decrease the consumption. Subscriber Line (ADSL) (NT). ORDER CODE Package Part Number Temperature Range D TS612ID -40, +85°C • Power Down 2 _ + + _ 10 12 Output 2 11 Vcc+ 2 Top view D = Small Outline Package (SO) - also available in Tape & Reel (DT) May 2000 1/11 TS612 ABSOLUTE MAXIMUM RATINGS Symbol VCC Vid Vin Parameter Supply voltage 1) Differential Input Voltage Input Voltage Range 2) 3) Value Unit ±7 V ±2 V ±6 V Toper Operating Free Air Temperature Range TS612ID -40 to + 85 °C Tstd Storage Temperature -65 to +150 °C Tj Maximum Junction Temperature 150 °C Rthjc Thermal Resistance Junction to Case 25 °C/W Rthja Thermal Resistance Junction to Ambient Area 45 °C/W Pmax. Maximum Power Dissipation (@25°C) 2.6 W Output Short Circuit Duration 4) 1. All voltages values, except differential voltage are with respect to network terminal. 2. Differential voltages are non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of input and output voltages must never exceed VCC +0.3V. 4. An output current limitation protects the circuit from transient currents. Short-circuits can cause excessive heating. Destructive dissipation can result from short circuit on amplifiers. OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vicm Common Mode Input Voltage Value Unit ±2.5 to ±6 V (VCC) +2 to (VCC+) -1 V 2/11 TS612 ELECTRICAL CHARACTERISTICS VCC = ±6Volts, Tamb = 25°C (unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max -6 -1 6 Unit DC PERFORMANCE Vio ∆Vio Input Offset Voltage Differential Input Offset Voltage Iio Input Offset Current Iib Input Bias Current CMR SVR ICC Common Mode Rejection Ratio Supply Voltage Rejection Ratio Total Supply Current per Operator Tamb Tmin. < Tamb < Tmax. 10 Tamb = 25°C 6 Tamb 0.2 Tmin. < Tamb < Tmax. 3 5 Tamb 5 Tmin. < Tamb < Tmax. 15 30 Vic = 2V to 2V, Tamb 90 Tmin. < Tamb < Tmax. 70 Vic = ±6V to ±4V, Tamb 70 Tmin. < Tamb < Tmax. 50 No load, Vout = 0 108 mV mV µA µA dB 88 dB 14 mA 4.5 V DYNAMIC PERFORMANCE VOH High Level Output Voltage Iout = 160mA RL connected to GND VOL Low Level Output Voltage Iout = 160mA RL connected to GND AVD Large Signal Voltage Gain 4 -4.5 Vout = 7V peak RL = 25Ω, Tamb 6500 Tmin. < Tamb < Tmax. 5000 -4 V 11000 V/V Gain Bandwidth Product AVCL = +11, f = 20MHz RL = 100Ω 80 130 MHz SR Slew Rate AVCL = +7, RL = 50Ω 23 40 V/µs Iout Output Short Circuit Current ±320 mA Isink Output Sink Current GBP Vic = ±6V, Tamb +200 Tmin. < Tamb < Tmax. +180 mA Vic = ±6V, Tamb -200 Tmin. < Tamb < Tmax. -180 Isource Output Source Current ΦM14 Phase Margin at AVCL = 14dB RL = 25Ω//15pF 60 ° ΦM6 Phase Margin at AVCL = 6dB RL = 25Ω//15pF 40 ° 3/11 mA TS612 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max Unit NOISE AND DISTORTION en Equivalent Input Noise Voltage f = 100kHz 3 nV/√Hz in Equivalent Input Noise Current f = 100kHz 1.2 pA/√Hz THD Total Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 RL = 25Ω//15pF -69 dB HD2-10 2nd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω//15pF -70 dBc HD2+2 2nd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = +2 Load =25Ω//15pF -74 dBc HD3+2 3rd Harmonic Distortion Vout = 4Vpp, f = 1MHz AVCL = +2 Load =25Ω//15pF -79 dBc HD3-10 3rd Harmonic Distortion Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω//15pF -80 dBc IM2-10 2nd Order Intermodulation Product F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω//15pF -77 dBc IM3-10 3rd Order Intermodulation Product F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω//15pF -77 dBc 4/11 TS612 POWER DOWN MODE VCC = ±6Volts, Tamb = 25°C Symbol Parameter Pin (1)(7) Thershold Voltage for Power Down Mode Vpdw Iccpdw Rpdw Cpdw Typ. Max Unit 0 3.3 0.8 V 2 75 3 TBD µA Ω µA Low Level High Level Power Down Mode Current Consumption Power Down Mode Ouput Impedance Power Down Mode Output Capacitance STANDBY CONTROL OPERATOR STATUS pin (1) pin (7) operator 1 operator 2 Vhigh level operator 1 operator 2 Vlow level Standby Active Vhigh level Vhigh level Standby Standby Vlow level Vlow level Active Active Vlow level Vhigh level Active Standby POWER DOWN EQUIVALENT SHEMATIC Vcc + + _ Vcc - 5/11 Min. .. 32:(5 '2:1 .. . Ouput OUPUT IMPEDANCE IN POWER DOWN MODE In Power Down Mode the output of the driver is in "high impedance" state. It is really the case for the static mode. Regarding the dynamic mode, the impedance decreases due to a capacitive effect of the collector-substrat and base collector junction. The impedance behaviour comes capacitive, typically: 1.4MΩ // 33pF. TS612 INTERMODULATION DISTORTION The curves shown below are the measurements results of a single operator wired as an adder with a gain of 15dB. The operational amplifier is supplied by a symmetric ±6V and is loaded with 25Ω. Two synthesizers (Rhode & Schwartz SME) generate two frequencies (tones) (70 & 80kHz or 180 & 280kHz). An HP3585 spectrum analyzer measures the spurious level at different frequencies. The curves are traced for different output levels (the value in the X ax is the value of each tone). The output levels of the two tones are the same. The generators and spectrum analyzer are phase locked to enhance measurement precision. 3rd ORDER INTERMODULATION (2 tones : 180kHz and 280kHz) 0 0 -10 -10 -20 -20 -30 -30 -40 IM3 (dBc) IM3 (dBc) 3rd ORDER INTERMODULATION (2 tones : 70kHz and 80kHz) 90kHz -50 230kHz -60 -40 -50 80kHz -60 380kHz -70 -70 -80 -80 60kHz -90 220kHz -100 1 1,5 2 640kHz -90 2,5 740kHz -100 3 3,5 4 4,5 Vout peak (V) 1 1,5 2 2,5 3 3,5 4 4,5 Vout peak (V) 2nd ORDER INTERMODULATION Spurious measurement @ 100kHz (2 tones : 180kHz and 280kHz) IM2 (dBc) -55 -60 -65 -70 1,5 2 2,5 3 3,5 4 4,5 Vout peak (V) 6/11 TS612 Closed Loop Gain and Phase vs. Frequency Gain=+6, Vcc=±6V, RL=25Ω Closed Loop Gain and Phase vs. Frequency Gain=+2, Vcc=±6V, RL=25Ω 10 200 200 20 Gain Gain 15 0 -20 -100 5 Gain (dB) Phase -10 100 10 Phase 0 0 -5 Phase (degrees) 100 Phase (degrees) Gain (dB) 0 -100 -10 -15 -30 -200 10kHz 100kHz 1MHz 10MHz -20 100MHz -200 10kHz 100kHz 1MHz Frequency 10MHz 100MHz Frequency Closed Loop Gain and Phase vs. Frequency Gain=+11, Vcc=±6V, RL=25Ω 30 Equivalent Input Voltage Noise Gain=+100, Vcc=±6V, no load 200 20 100 15 Gain Phase 0 0 -10 en (nV/VHz) Gain (dB) 10 Phase (degrees) 20 + _ 10k 100 10 -100 5 -200 0 -20 -30 10kHz 100kHz 1MHz 10MHz Frequency 100Hz 100MHz 100kHz 1MHz Channel Separation (Xtalk) vs. Frequency XTalk=20Log(V2/V1), Vcc=±6V, RL=25Ω VIN 5 + 49.9Ω _ -10 4 output -20 3 -40 Xtalk (dB) input 1 0 -1 -2 -3 V1 1kΩ 100Ω -30 2 swing (V) 10kHz Frequency Maximum Output Swing Vcc=±6V, RL=25Ω + 49.9Ω _ -50 100Ω -60 25Ω V2 1kΩ 25Ω -70 -80 -4 -90 -5 0 2 4 6 Time (µs) 7/11 1kHz 8 10 -100 10kHz 100kHz 1MHz Frequency 10MHz TYPICAL APPLICATION : TS612 AS DRIVER FOR ADSL LINE INTERFACES A SINGLE SUPPLY IMPLEMENTATION WITH PASSIVE OR ACTIVE IMPEDANCE MATCHING by C. PRUGNE ADSL CONCEPT Asymmetric Digital Subscriber Line (ADSL), is a new modem technology, which converts the existing twisted-pair telephone lines into access paths for multimedia and high speed data communications. ADSL transmits more than 8 Mbps to a subscriber, and can reach 1Mbps from the subscriber to the central office. ADSL can literally transform the actual public information network by bringing movies, television, video catalogs, remote CD-ROMs, LANs, and the Internet into homes. An ADSL modem is connected to a twisted-pair telephone line, creating three information channels: a high speed downstream channel (up to 1.1MHz) depending on the implementation of the ADSL architecture, a medium speed upstream channel (up to 130kHz) and a POTS (Plain Old Telephone Service), split off from the modem by filters. The TS612 is used as a dual line driver for the upstream signal. For the remote terminal it is required to create an ADSL modem easy to plug in a PC. In such an application, the driver should be implemented with a +12 volts single power supply. This +12V supply is available on PCI connector of purchase. The figure 2 shows a single +12V supply circuit that uses the TS612 as a remote terminal transmitter in differential mode. Figure 2 : TS612 as a differential line driver with a +12V single supply 1µ 100n 3 +12V high output current digital to analog emission (analog) LP filter digital treatment upstream TS612 Line Driver impedance matching HYBRID CIRCUIT analog to digital 8/11 reception (analog) reception circuits downstream twisted-pair telephone line 12.5 1:2 R2 47k Vo 25Ω R1 10µ Vi 100n Figure 1 : Typical ADSL Line Interface 10n 19 2 _ 47k 100n GND R3 9 + 8 _ The Figure1 shows a typical analog line interface used for ADSL. The upstream and downstream signals are separated from the telephone line by using an hybrid circuit and a line transformer. On this note, the accent will be made on the emission path. +12V 1k Vi 1k THE LINE INTERFACE - ADSL Remote Terminal (RT): + 20 11 Hybrid & Transformer 100Ω Vo +12V 12.5 12 GND 4,5,6,7,14,15,16,17,18 The driver is biased with a mid supply (nominaly +6V), in order to maintain the DC component of the signal at +6V. This allows the maximum dynamic range between 0 and +12 V. Several options are possible to provide this bias supply (such as a virtual ground using an operational amplifier), such as a two-resistance divider which is the cheapest solution. A high resistance value is required to limit the current consumption. On the other hand, the current must be high enough to bias the inverting input of the TS612. If we consider this bias current (5µA) as the 1% of the current through the resistance divider (500µA) to keep a stable mid supply, two 47kΩ resistances can be used. The input provides two high pass filters with a break frequency of about 1.6kHz which is necessary to remove the DC component of the input signal. To avoid DC current flowing in the primary of the transformer, an output capacitor is used. The TS612 1µF capacitance provides a path for low frequencies, the 10nF capacitance provides a path for high end of the spectrum. Component calculation: Let us consider the equivalent circuit for a single ended configuration, figure4. In differential mode the TS612 is able to deliver a typical amplitude signal of 18V peak to peak. Figure 4 : Single ended equivalent circuit The dynamic line impedance is 100Ω. The typical value of the amplitude signal required on the line is up to 12.4V peak to peak. By using a 1:2 transformer ratio the reflected impedance back to the primary will be a quarter (25Ω) and therefore the amplitude of the signal required with this impedance will be the half (6.2 V peak to peak). Assuming the 25Ω series resistance (12.5Ω for both outputs) necessary for impedance matching, the output signal amplitude required is 12.4 V peak to peak. This value is acceptable for the TS612. In this case the load impedance is 25Ω for each driver. For the ADSL upstream path, a lowpass filter is absolutely necessary to cutoff the higher frequencies from the DAC analog output. In this simple non-inverting amplification configuration, it will be easy to implement a Sallen-Key lowpass filter by using the TS612. For ADSL over POTS, a maximum frequency of 135kHz is reached. For ADSL over ISDN, the maximum frequency will be 276kHz. INCREASING THE LINE LEVEL BY USING AN ACTIVE IMPEDANCE MATCHING With passive matching, the output signal amplitude of the driver must be twice the amplitude on the load. To go beyond this limitation an active maching impedance can be used. With this technique it is possible to keep good impedance matching with an amplitude on the load higher than the half of the ouput driver amplitude. This concept is shown in figure3 for a differential line. Figure 3 : TS612 as a differential line driver with an active impedance matching 3 +12V + 20 +12V 10µ 1k 25Ω R5 R4 9 + 8 _ 100n 1:2 R3 47k 100n GND _ Vi Vo° Vo R2 -1 R3 1/2R1 1/2RL Let us consider the unloaded system. Assuming the currents through R1, R2 and R3 as respectively: 2Vi ( Vi – Vo° ) ( Vi + Vo ) --------- , -------------------------- and -----------------------R1 R2 R3 As Vo° equals Vo without load, the gain in this case becomes : 2R2 R2 1 + ---------- + ------( noload ) R1 R3 G = Vo ------------------------------ = ---------------------------------Vi 1 – R2 ------R3 The gain, for the loaded system will be (1): 2R2 R2 1 + ---------- + ------1 R1 R3 ( withload ) Vo GL = ------------------------------------ = --- ----------------------------------- ,( 1 ) 2 Vi 1 – R2 ------R3 As shown in figure5, this system is an ideal generator with a synthesized impedance as the internal impedance of the system. From this, the output voltage becomes: Vo = ( ViG ) – ( RoIout ) ,( 2 ) with Ro the synthesized impedance and Iout the output current. On the other hand Vo can be expressed as: Vo R1 Vi Vo° R2 47k 10n 19 2 _ 1k Vi 12.5 Rs1 2R2 Vi 1 + ----------- + R2 ------- R1 R3 Rs1Iout Vo = ----------------------------------------------- – --------------------- ,( 3 ) 1 – R2 ------1 – R2 ------R3 R3 1µ 100n + 11 Vo° +12V Hybrid & Transformer 100Ω Vo 12.5 12 GND 4,5,6,7,14,15,16,17,18 9/11 TS612 By identification of both equations (2) and (3), the synthesized impedance is, with Rs1=Rs2=Rs: Rs Ro = ----------------- ,( 4 ) 1 – R2 ------R3 GL (gain for the loaded system) R1 R2 (=R4) R3 (=R5) Figure 5 : Equivalent schematic. Ro is the synthesized impedance Rs GL is fixed for the application requirements GL=Vo/Vi=0.5(1+2R2/R1+R2/R3)/(1-R2/R3) 2R2/[2(1-R2/R3)GL-1-R2/R3] Abritrary fixed R2/(1-Rs/0.5RL) 0.5RL(k-1) CAPABILITIES Ro Iout Vi.Gi 1/2RL The table below shows the calculated components for different values of k. In this case R2=1000Ω and the gain=16dB. The last column displays the maximum amplitude level on the line regarding the TS612 maximum output capabilities (18Vpp diff.) and a 1:2 line transformer ratio. Active matching k Unlike the level Vo° required for a passive impedance, Vo° will be smaller than 2Vo in our case. Let us write Vo°=kVo with k the matching factor varying between 1 and 2. Assuming that the current through R3 is negligeable, it comes the following resistance divider: kVoRL Ro = --------------------------RL + 2Rs1 After choosing the k factor, Rs will equal to 1/2RL(k-1). A good impedance matching assumes: 1 R o = --- RL ,( 5 ) 2 From (4) and (5) it becomes: 2Rs R2 ------- = 1 – ---------- , ( 6 ) RL R3 By fixing an arbitrary value for R2, (6) gives: R2 R3 = ------------------2Rs 1 – ---------RL Finally, the values of R2 and R3 allow us to extract R1 from (1), and it comes: 2R2 R1 = --------------------------------------------------------- ,( 7 ) R2 2 1 – ------- GL – 1 – R2 ------ R3 R3 with GL the required gain. 10/11 1.3 1.4 1.5 1.6 1.7 R1 (Ω) 820 490 360 270 240 Passive R3 (Ω) Rs (Ω) 1500 3.9 1600 5.1 2200 6.2 2400 7.5 3300 9.1 matching TS612 Output Level to get 12.4Vpp on the line (Vpp diff) 8 8.7 9.3 9.9 10.5 12.4 Maximum Line level (Vpp diff) 27.5 25.7 25.3 23.7 22.3 18 MEASUREMENT OF THE POWER CONSUMPTION IN THE ADSL APPLICATION Conditions: Passive impedance matching Transformer turns ratio: 2 Maximun level required on the line: 12.4Vpp Maximum output level of the driver: 12.4Vpp Crest factor: 5.3 (Vp/Vrms) The TS612 power consumption during emission on 900 and 4550 meter twisted pair telephone lines: 450mW TS612 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) Millimeters Inches Dim. Min. A a1 a2 b b1 C c1 D E e e3 F L M S Typ. Max. Min. 2.65 0.3 2.45 0.49 0.32 0.1 0.35 0.23 Typ. 0.104 0.012 0.096 0.019 0.013 0.004 0.014 0.009 0.5 Max. 0.020 45° (typ.) 12.6 10 13.0 10.65 0.496 0.394 1.27 11.43 7.4 0.5 0.512 0.419 0.050 0.450 7.6 1.27 0.75 0.291 0.020 0.299 0.050 0.030 8° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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