TSC TSM4944DCSRL

TSM4944D
Preliminary
30V Dual N-Channel MOSFET
SOP-8
Pin Definition:
1. Source 1
8. Drain
2. Gate 1
7. Drain
3. Source 2
6. Drain
4. Gate 2
5. Drain
PRODUCT SUMMARY
VDS (V)
RDS(on)(mΩ)
1
1
2
2
30
Features
●
●
ID (A)
13.2 @ VGS = 10V
12.2
18 @ VGS = 4.5V
9.4
Block Diagram
Advance Trench Process Technology
High Density Cell Design for Ultra Low On-resistance
Application
●
●
Load Switch
Dc-DC Conversion
Ordering Information
Part No.
Package
Packing
TSM4944DCS RL
SOP-8
2.5Kpcs / 13” Reel
Dual N-Channel MOSFET
Absolute Maximum Rating (Ta = 25oC unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
VDS
30
V
Gate-Source Voltage
VGS
±20
V
ID
12.2
A
IDM
30
A
IS
1.9
A
Continuous Drain Current
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
a,b
o
Maximum Power Dissipation
Ta = 25 C
PD
o
Ta = 75 C
Operating Junction Temperature
W
1.2
+150
o
TJ, TSTG
-55 to +150
o
Symbol
Limit
TJ
Operating Junction and Storage Temperature Range
2.3
C
C
Thermal Performance
Parameter
Junction to Case Thermal Resistance
RӨJC
Junction to Ambient Thermal Resistance (PCB mounted)
RӨJA
Unit
1.8
o
40
o
C/W
C/W
Notes:
a. Maximum DC current limited by the package
b. Surface Mounted on 1” x 1” FR4 Board, t ≤ 10 sec.
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Version: Preliminary
TSM4944D
Preliminary
30V Dual N-Channel MOSFET
Electrical Specifications (Ta = 25oC unless otherwise noted)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Static
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250uA
BVDSS
30
--
--
V
Gate Threshold Voltage
VDS = VGS, ID = 250uA
VGS(TH)
1.0
1.8
3.0
V
Gate Body Leakage
VGS = ±20V, VDS = 0V
IGSS
--
--
±100
nA
Zero Gate Voltage Drain Current
VDS = 30V, VGS = 0V
IDSS
--
--
1.0
uA
On-State Drain Current
VDS ≥5V, VGS = 10V
ID(ON)
30
--
--
A
--
11
13.2
--
15.4
18
Drain-Source On-State Resistance
VGS = 10V, ID = 12.2A
VGS = 4.5V, ID = 9.4A
RDS(ON)
mΩ
Forward Transconductance
VDS = 15V, ID = 15A
gfs
--
32
--
S
Diode Forward Voltage
IS = 1.9A, VGS = 0V
VSD
--
0.85
1.3
V
Qg
--
26
--
Qgs
--
6
--
Qgd
--
5
--
Ciss
--
2134
--
Coss
--
343
--
Crss
--
134
--
td(on)
--
17
--
tr
--
3.5
--
td(off)
--
40
--
--
6
--
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS = 15V, ID = 12.2A,
VGS = 10V
VDS = 15V, VGS = 0V,
f = 1.0MHz
nC
pF
c
Switching
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
VDD = 15V, RL = 15Ω,
ID = 1A, VGEN = 10V,
RG = 6Ω
Turn-Off Fall Time
tf
Notes:
a. pulse test: PW ≤300µS, duty cycle ≤2%
b. For DESIGN AID ONLY, not subject to production testing.
b. Switching time is essentially independent of operating temperature.
2/4
nS
Version: Preliminary
TSM4944D
Preliminary
30V Dual N-Channel MOSFET
SOP-8 Mechanical Drawing
DIM
A
B
C
D
F
G
K
M
P
R
SOP-8 DIMENSION
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX.
4.80
5.00
0.189
0.196
3.80
4.00
0.150
0.157
1.35
1.75
0.054
0.068
0.35
0.49
0.014
0.019
0.40
1.25
0.016
0.049
1.27BSC
0.05BSC
0.10
0.25
0.004
0.009
0º
7º
0º
7º
5.80
6.20
0.229
0.244
0.25
0.50
0.010
0.019
Marking Diagram
Y = Year Code
M = Month Code
(A=Jan, B=Feb, C=Mar, D=Apl, E=May, F=Jun, G=Jul, H=Aug,
I=Sep, J=Oct, K=Nov, L=Dec)
L = Lot Code
3/4
Version: Preliminary
Preliminary
TSM4944D
30V Dual N-Channel MOSFET
Notice
Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf,
assumes no responsibility or liability for any errors or inaccuracies.
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and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability,
or infringement of any patent, copyright, or other intellectual property right.
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Version: Preliminary